CHAPTER 1 Introduction
1.1 General Background
In modern times, the application of Flash memory is indispensable. Flash memory not only has wide and practical applications extremely but also is considered as a technology driver for semiconductor industry in the next decade.
It can be classified into two major applications: code storage application and data storage application. NOR type Flash memory is the most suitable for code storage application, such as DVD player, PC bios, and cellular phones; NAND type Flash memory has been targeted at data storage application, such as USB flash personal disc, memory cards, MP3 audio players, digital cameras, and PDA. In short, the 3C products are almost based on Flash memory.
Flash memory is a kind of nonvolatile memory that can keep stored information even though the power supply is switched off. It also has exhibited several advantages, like the ability to be electrical programmed and fast simultaneously block electrical erased in a single-cell, the smallest cell size to own the highest chip density, and the good flexibility. Furthermore, the fabrication process of Flash memory is compatible with the current CMOS process and is a suitable solution for embedded memory applications. Therefore, Flash memory is easily a scalable replacement for Erasable Programmable Read Only Memory (EPROM) and Electrically Erasable Programmable Read Only Memory (EEPROM). We will compare Flash memory with other nonvolatile memories later.
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Since the first MOSFET device was invented by Ligenza and Spitzer in 1960, one of the most revolutionary technology drivers to settle the direction of the development of semiconductor industries is the semiconductor memory.
Magnetic-core memory is the large volume, high cost, and high power consumption so that the electronic industries urgently needed new species of memory devices to replace the magnetic-core memory. For this reason, D.
Kahng and S. M. Sze invented the first floating-gate (FG) nonvolatile semiconductor memory at Bell Labs [1] in 1967. To date, the stacked-gate floating gate device structure, as shown in Fig. 1-1, has been the most prevailing nonvolatile-memory implementation, and has used widely in both standalone and embedded memories. The invention of FG memory not only affects to replace magnetic-core memory but also creates a monumental industry of portable electronic systems. Flash memory is the most wide spread FG memory array organization, and it has a byte-selectable write operation combined with a sector “flash” erase.
In the past decade, the booming market of portable electronic devices such as digital cameras and cellular phones makes memory chips with low power consumption and low cost get more and more attention. These applications want the memory to have ten years data retention time; hence, the nonvolatile memory (NVM) device has become indispensable. There are four major types of nonvolatile memory technology: Flash memory, Ferro-electric Random Access Memory (FeRAM), Magnetic Random Access Memory (MRAM) and Phase Change Memory (PCM).
Among these types of nonvolatile memory, Flash memory is presently the
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most suitable option for the following reasons:
(1) Flash memory can accomplish the highest chip density, as a Flash memory cell consists of only one transistor [2]. A MRAM cell needs a transistor and a magnetic tunnel junction [4], while a FeRAM memory cell generally comprises one transistor and one capacitor [3]. PCM was considered as a promising nonvolatile memory [5], but its memory cell consists of one resistor and a bipolar junction transistor. Until now, only a 256MB PCM chip has been developed. It needs taking more effort to develop if PCM is really a promising technology.
(2)FeRAM is not an idea nonvolatile memory because its reading mode is a destructive type of operation. A programming verification is required to restore the data after reading. On opposite sides, Flash memory doesn’t need the additional action. In other words, the reading operation of Flash memory is not destructive, and it affects slighter data retention disturbance than FeRAM.
(3) The fabrication process of Flash memory is compatible with the current CMOS process and is a suitable solution for embedded memory applications. A Flash memory cell is similar to a MOSFET cell, except that a poly-silicon floating gate [9] (or Silicon Nitride charge trapping layer [8]) is placed in between a tunnel oxide and an inter-poly oxide to form a charge storage layer.
All other nonvolatile memories require integration of new materials that are not compatible with a conventional CMOS process. Therefore, it is easier and more reliable to integrate Flash memory than other nonvolatile memories with logic and analog devices to achieve better chip performance for wireless computation and wireless communication [10].
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(4) Four distinct threshold voltage (Vth) states can be achieved in a Flash memory cell by trapping the number of charges in the charge storage layer.
Hence, Flash memory can possess the multi-bit per cell storage property [6].
Two-bits/cell (with four Vth states) Flash memory cells have already been commercialized; four-bits/cell Flash memory device is feasible and is under development now [7]. Multi-bit storage increases memory density and reduces the cost per bit significantly. In addition, Matrix Semiconductor Inc.
demonstrated multi-layer SONOS Flash memory [8]. This novel structure makes another possibility to achieve even higher density and lower cost technologies based on Flash memory. On account of these critical advantages, Flash memory has turned into the chief nonvolatile memory device in this generation.
The Flash memory cell structure was invented originally by D. Kahng and S.
M. Sze in 1967, and Intel ETOX (EPROM Tunnel Oxide) structure, shown in Fig. 1-2 , is the famously commercial Flash memory in 1988 [11]. The operation principal is using the poly-silicon which is above the tunnel oxide layer and named Floating Gate as the charge store unit for the device. ETOX could be programmed or erased by Channel-Hot-Electron-Injection (CHEI), Fowler-Nordheim tunneling (F-N), or Band-to-Band-Hot-Hole (BTBHH). The threshold voltage of Flash memory will be shifted after electrons are injected into the FG from the channel. Therefore, the logical “0”and “1” of nonvolatile memory devices can be defined by the different states of the threshold voltage (Fig. 1-3). The specification of the concept will be described in Chapter 2.
Even though conventional FG devices achieve a great commercial success, there are some limitations. Two of the most dominant limitations are: (1) the
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potential for continued scaling down of the device structure. This scaling down limitation results from the tunnel oxide layer. The tunnel oxide should be thin enough so that carriers can transport to and from the floating gate quickly and efficiently. On the other hand, the tunnel oxide also is required to supply well isolation to retain information integrity over periods of up to a decade under retention, endurance, and disturbed conditions. If the tunnel oxide is thinner for the faster operation speed consideration, characteristics of the retention will be degraded. On the contrary, if the tunnel oxide is thicker for the superior isolation account, the operation speed will be slower. There is a trade-off between the operation speed and the reliability. Hence, we need to find the proper tunnel oxide thickness for the better product functions. (2) As plenty of program/erase cycles, the strength and quality of tunnel oxide will degrade. Once a leaky path is created in the tunnel oxide, all the charges stored in the floating gate will be lost.
Two suggestions, Poly-Silicon/Oxide/Nitride/Oxide/Silicon (SONOS) [12-14]
and nanocrystal nonvolatile memory devices [15-17], have been demonstrated to lead to an improvement in retention time and endurance compared with conventional floating gate memory. Hence, the tunnel oxide thickness can be reduced to allow faster program speed and lower operation voltage.
1.1.1 Nanocrystal Nonvolatile Memory Devices
Nanostructure nonvolatile memory is introduced in the early 1990s firstly.
IBM researchers proposed flash memory with a granular floating gate made of silicon nanocrystals [73]. The term “nanocrystal” refers to a crystalline structure
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with a nanoscale dimension and its electronic properties seem more similar to an atom or molecule rather than the bulk crystal. Fig. 1-4 illustrates conventional nanocrystal nonvolatile memory (NVM) device structure. It could be found that the nanocrystals are separated by the isolation within the gate dielectric. For a nanocrystal NVM device, the charge storage media is in the form of mutually isolated nanocrystals rather than the continuous poly-silicon layer. The limited size and capacitance of nanocrystals limit the numbers of stored electrons;
collectively the stored charges screen the gate charge and control the channel conductivity of the memory transistor.
Nanocrystal-based NVM devices have recently attracted much attention in consequence of their potential to overcome the limitations of conventional poly-silicon-based flash memory. There are several advantages of using nanocrystals as charge storage media. The main one is the potential to use thinner tunnel oxide without sacrificing retention. This is an entirely attractive proposition since reducing the tunnel oxide thickness is a key to lowering operation voltage and increasing operation speed. The claim of improving scalability results from the local charge storage in discrete nodes, which make the storage more fault-tolerant and immune to the leakage current caused by localized oxide defects. In addition, the lateral charge migration effect between nanocrystal can be diminished by the strongly isolation of surrounded dielectric.
There are other important advantages. First, nanocrystal memory uses the more simplified fabrication process as is compared to conventional stacked-gate FG NVM’s avoiding the fabrication complications and costs of a dual-poly process.
Second, due to the absence of drain to FG coupling, nanocrystal memory suffers
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the less from drain-induced-barrier-lower (DIBL) so that it has the better suppressing punch through characteristic. One way to utilize this advantage is using a higher drain bias during the read operation, thus reducing memory access time [74]. Furthermore, it allows the use of shorter channel length and therefore higher cell density. Finally, nanocrystal memory owns excellent immunity to stress induced leakage current (SILC) and oxide defects on account of the discrete charge storage nodes in the nanocrystal layer.
Research in this structure has focused on the development of fabrication processes and nanocrystal materials, and on the integration of nanocrystal-based storage layers in actual memory devices.
1.1.2 SONOS Nonvolatile Memory Devices
The originally nitride-base device is metal-gate nitride device Metal/Nitride/Oxide/Silicon (MNOS) which was introduced in 1967 by Wegener et al [65]. Silicon nitride film contains many carrier traps which could trap carriers and cause threshold voltage shift. Then the silicon nitride trap-based devices are extensively studied for charge storage device application in the early 70s. Fig. 1-5 illustrates the progression of device structure, which has led to the present poly-Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) device structure. In the early 1970s, the initial device structure was p-channel MNOS structure with aluminum gate electrode and thick (45 nm) silicon nitride charge storage layer.
Program/erase voltages were about 25-30 V. In the late 1970s and early 1980s, the device structure developed to n-channel SNOS device with program/erase voltages of 14-18 V. In the late 1980s and early 1990s, n- and p-channel
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SONOS devices emerged with program/erase voltages of 5-12 V. The advantages of the ONO triple dielectric layer are: (1) that charge injection from and to the gate electrode is minimized for both gate polarities, particularly for hole injection; (2) lower program voltage since the blocking action of the top oxide removes any limitation on reducing the nitride thickness; (3) improving memory retention since there is minimal loss of charge to the gate electrode.
The SONOS memory device, shown in Fig. 1-6, has received much attention due to its advantages over the traditional floating-gate flash devices. These include reducing process complexity, higher operation speed, lower operation voltage, improving cycling endurance, and elimination of drain-induced turn-on [66-68]. The significant difference between floating-gate and SONOS structure is the way of charge storage. The charge storage media is the conductive poly-silicon floating-gate electrode. In the SONOS memory structure, charges are stored in the physical discrete traps of silicon nitride dielectric layer. A typical trap has a density of the order 1018-1019 cm-3 according to Yang et al [69]
and stores both holes and electrons injected from the channel. The charges cannot move freely between the discrete trap locations so that the SONOS memory device is very hardy against the defects inside the tunnel oxide and has good endurance.
The SONOS memory device still encounters challenges in the future for high density nonvolatile memory application, which requires low voltage (< 5V), low power consumption, excellent retention, and superior endurance. Various methods have been proposed for improving the SONOS performance and reliability. For instance, Chen et al. demonstrated a Si3N4 band-gap engineering
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(BE) control method for better endurance and retention. A nitride with varied relative Si/N ratio throughout the film has increased the charge-trapping efficiency significantly [70]. Besides, Tan et al. proposed that over-erase phenomenon in SONOS memory structure can be minimized by replacing silicon nitride with HfO2 as the charge storage layer. HfAlO composed of 10%
Al2O3 and 90% HfO2 improves the charge retention and endurance, while it maintains the over-erase resistance of HfO2 [71]. She et al. showed that high-quality nitride is applied as the tunnel dielectric layer for a SONOS-type memory device. Compared with SiO2 as tunnel dielectric layer, faster program speed and better retention time are achieved with low operation voltage [72].
Lee et al. demonstrated a device structure of SiO2/Si3N4/Al2O3 (SANOS) with TaN metal gate. TaN metal gate is more effective than a traditional poly-silicon gate to obstruct electron current through Al2O3 layer, resulting in faster program/erase speed and significantly decreasing the saturation level of the erase threshold voltage [73].
Chen et al. researched a polycrystalline silicon thin-film transistor (poly-Si TFT) with oxide/nitride/oxide (ONO) gate dielectric layers and multiple nanowire channels for the applications of both SONOS memory and switch transistor [75]. The proposed NW SONOS-TFT exhibits superior memory device characteristics with high program/erase efficiency and stable retention at high temperature. Such a SONOS-TFT is thereby highly promising for applications of system-on-panel display in the future.
New device structures are also indispensable in making flash memory more scalable, since SONOS flash memory offers a thinner gate stack than floating
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gate flash memory and a Fin-FET structure controls the short channel effect much better than a bulk structure. It has been demonstrated that the Fin-FET SONOS flash memory device with a much smaller cell size can achieve both remarkable performance and reliability. Hence, Fin-FET SONOS memory has potential to become the candidate for the next generation flash memory [76-77].
In past decade, about 20% of semiconductor market is given by the semiconductor memory, and the output value of Flash memory is expected to reach US$ 60 billion in 2010. The Development of the higher capacity and faster Flash nonvolatile memory is always one of the most important issues for technologic applications. In order to arrive at the goal, downsizing or multi-bit is the key point for pushing next generation development. In addition, the most important performance of Flash memory is reliability characteristic, such as program/erase cycling and data retention. It is well known that the tunnel oxide degradation during Fowler-Nordheim (FN) stress results from the oxide trap and interface trap generation. In conclusion, how to improve the reliability of Flash memory is the emphasis in this study.