We probe into the electrical characteristics of the capacitors and the SOHOS memory devices in this section. The electrical characteristics of capacitors and SOHOS memory device are measured by HP4284 Precision LCR Meter and HP4156C Precision Semiconductor Parameter Analyzer.
3.3.1 Electrical Characteristic of HfO
2Capacitor
Fig 3-4(a) is the C-V hysteresis curve of capacitors with RTA and CF4 plasma treatment after bidirectional sweeps. Because electrons inject into trapping layer from substrate the counterclockwise direction of the hysteresis curve is present.
At first the upper electrode of capacitor was biased from positive voltage to negative voltage, and the inversion layer of silicon substrate turned into the accumulation layer gradually. When the capacitor was operated in the positive gate voltage, the electrons of inversion layer inject into the trapping layer
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through F-N tunneling mode. Then these electrons will be trapped in the HfO2
layer and let the VFB (flat-band voltage) of capacitor shift to the positive side.
On the other hand, when the capacitor is biased from negative voltage to positive voltage, the trapped electrons maybe tunnel back to substrate or the holes can also inject into the trapping layer and combine with the trapped electrons. These two phenomena can reduce the amount of trapped electrons in charge storage layer and form the left C-V curve. The memory window characteristics of capacitors with RTA and CF4 plasma treatments form capacitance-voltage (C-V) hysteresis are respectively shown in Fig 3-4(b) and (c). In general, the larger operation voltage should cause larger memory window.
The different treatments are confirmed to this rule in our experiment. From Fig 3-4(b), the memory window is depended on the temperature and duration of the RTA treatments. Because the higher temperature and the longer duration RTA make HfO2 more crystallized, the more traps are induced. Therefore, the carriers are easily trapped in HfO2 trapping layer and then they result the larger memory window. The memory window of Cap-P6 and Cap-P7, shown in Fig 3-4(c), are almost the same as they make HfO2 similarly crystallized. In addition, the memory window characteristics of capacitors with the RTA and CF4 plasma treatment also are compared in Fig 3-4(d). The memory window of Cap-P6 and Cap-P7 are like Cap-R1 and lower than Cap-R2 and Cap-R3 for the level of HfO2 crystallized. According to the x-ray diffraction (XRD) spectra of crystallized HfO2 with RTA and CF4 plasma treatment, shown in Fig 3-5, we can certify the level of HfO2 crystallized. It shows HfO2 with Cap-P5 is slightly crystallized and others are resembled. The gate leakage current-voltage (IG-V)
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characteristics of different treatments by gate voltage sweeping from 0 V to 12 V and 0 V to -12 V are shown in Fig 3-6. It is clear that the gate leakage current of the capacitors containing RTA and CF4 plasma treatment are low regardless of forward bias or reverse bias. Even thought Cap-R3 is higher than others because of seriously HfO2 crystallized, it is still lower than 10-9A. This result can verify that CF4 plasma treatment would not induce more gate leakage current than RTA treatment and there is no critically gate injection problem which will affect the memory window of capacitors.
Next, we begin to concern about the reliability of capacitors. Fig 3-7(a),(b) show the retention characteristic of capacitors with RTA and CF4 plasma treatment at room temperature. From Fig 3-7(a), there is the larger VFB shift window between program state and initial state in Cap-R1 than Cap-R2 and Cap-R3 after 104 second. The capacitors, underwent lower temperature and shorter duration RTA treatments, performs the better retention characteristic.
The data retention degradation attributes to the charge loss. Some possible causes of charge loss are defects in tunnel oxide, defects in blocking oxide or mobile ion contamination. Therefore, we thought that higher temperature and longer duration will induce more traps with shallower energy level in the trapping layer, which give rise to larger memory window and poor charge retention [64]. Besides, the higher temperature and longer duration make HfO2
more crystallized and there are the leakage paths formed by grain boundary.
From Fig 3-7(b), we discuss capacitors with CF4 plasma treatment ,including Cap-P4、Cap-P5、Cap-P6 and Cap-P7, and find that the retention performance is improved with increasing the power of CF4 plasma treatment. In other words,
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Cap-P7 owns the best retention performance in all capacitors. We consider the power of Cap-P7 has enough energy to make the fluorine incorporated into the HfO2 trapping layer and then formed of Hf-F bonding with hafnium [79]. Hence, the shallow traps would be recovered by the fluorine but the deep traps would still be left. The carriers’ de-trapping effect is decreased after program operation.
The Fig 3-7(c) is the Comparisons of the retention characteristics for RTA and CF4 plasma treatment capacitors. The retention performance of Cap-P7 is better than Cap-R1 for the shallow traps recovered by the fluorine even though they make HfO2 similarly crystallized. In order to confirm that Hf-F bonding is formed, we analyze the XPS spectra for Hf 4f core levels from HfO2. The peak of binding energy with 600℃ 30sec RTA treatment, shown in Fig 3-8(a), at 16.26 eV is evident and with 70W 30sec CF4 plasma treatment is at 16.64eV as we can see in Fig 3-8(c). The bonding energy of Cap-P7 is higher than Cap-R1.
This phenomenon means that there is another Hf bonding formation in Cap-P7.
Hence, we consider the HfO2 with the CF4 plasma treatment reveals the Hf–F bonding, indicating fluorine incorporation after carried out the CF4 plasma treatment.
However, we should discuss whether the CF4 plasma treatment causes damage on HfO2 surface in our experiment or not. The comparisons of the surface roughness for HfO2 with RTA and CF4 plasma treatment by AFM are shown in Fig 3-9. The surface roughnesses of them are all similar. In addition, if the CF4
plasma treatment causes damage on HfO2 surface, it will decrease thickness of HfO2. The Fig 3-10 shows the difference of the thicknesses for HfO2 between RTA and CF4 plasma treatment. The RTA treatment sample is thinner than
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as-deposit sample because the HfO2 is densified by the RTA treatment. The CF4
plasma treatment samples are thicker than as-deposit sample. Since fluorine atom has the highest electronegativity, the incorporated fluorine atoms from the CF4 plasma treatment exhibit high potential to substitute the oxygen atoms, then replace the Hf–O bonds with the Hf–F bonds. Part of the residual oxygen may diffuse toward the interface between HfO2/SiO2 layer and underneath silicon substrate, and then react with the silicon dangling bonds at the interface to growth the interfacial layer. Therefore, the thicknesses of the CF4 plasma treatment samples are increased [80]. The mechanism of the interfacial re-oxidation is also shown in Fig 3-11. According to those results, we consider there is not significant damage which is formed by the CF4 plasma treatment in our experiment.
3.3.2 Electrical Characteristic of HfO
2Memory Device
This section will analyze the electric characteristics of the SOHOS Flash memory using HfO2 as trapping layer. The split table of memory devices is listed in Table 3.2. Fig 3-12(a) shows the IDS-VDS curve and Fig 3.12(b) shows the IDS-VGS curve of Flash memory devices including flesh, program state, and erase state. When the device is programmed, the electrons will be trapped in the HfO2 layer and then make the Vth increased. When the device is erased, the holes will be trapped and electrons will be de-trapped and then make the Vth decreased to the initial state. The memory devices are programmed by CHEI (channel hot electron injection), as shown in Fig 3-13(a), Fig 3-14(a) and Fig 3-15(a).
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The CHE program option are set to VDS=VGS=7V, VDS=VGS=8V and VDS=VGS=9V. We can observe that the program speed of P50 and Control are alike. The reason for the similar program speed is that HfO2 trapping layer of them are the same crystallized almost. The memory devices are erased by The BTBT tunneling, as shown in Fig 3-13(b), Fig 3-14(b) and Fig 3-15(b). The BTBT erase option are set to VGS=-6V VDS=6 V, VGS=-7V VDS=7 V and VGS=-8V VDS=8V.
Subsequently, the comparisons of the retention characteristic for Control, P40 and P50 at room temperature are shown in Fig 3-16. There is the larger Vth shift in P50 than P40 and Control after 108 second since the shallow traps of P40 is recovered by the fluorine. Besides, the Vth shift of P40 is larger than Control due to the same reason. Then, the Fig 3-17 also shows the comparisons of the retention characteristic for Control and P50 at different temperatures. From Fig 3-18, we compare the retention performance of the devices which underwent 104 program/erase cycles and then observe that P40 performs the better retention characteristic than P50 because of the fluorine implantation and Control is still the worst. The fluorine implantation of P40 would diminish defects of the blocking oxide and tunnel oxide and then suppress leakage paths, formed by P/E operation, so that the retention performance is improved. Similarly, the Fig 3-19 shows the comparisons of the endurance characteristic for Control and CF4
plasma treatment devices and the CF4 plasma treatment devices is better and Control. This result reveals that the CF4 plasma treatment process can recover the defects from the deposition process by the fluorine.
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