In Chapter 1, the potential memory devices about nonvolatile memory
(NVM), conventional Flash SONOS and SOHOS devices are introduced in this chapter.
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In Chapter 2, basic principle of nonvolatile memory is introduced.
In Chapter 3, the device characteristics will be discussed In Chapter 4, Materials Analysis
In Chapter 5, this section includes the conclusions and the future work of this study.
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Table 1.1: Performance Comparison is between volatile memory (DRAM and SRAM) and nonvolatile memory (Flash, FRAM, MRAM and phase change memory) devices. Among the nonvolatile memories, Flash memory is the only memory compatible with the current CMOS process flow. Overall, the Flash memory exhibits the best performance except for the disadvantages of high programming voltage and slow program/erase speed.
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Fig 1-1: Schematic cross section of the conventional floating gate nonvolatile memory device. Poly-Si floating gate is used as the charge storage element
Fig 1-2: Schematic cross section of ETOX device
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Fig 1-3: I-V curves of a floating gate device when there is no charge stored in the FG (“1”-curve) and when a negative charge Q is stored in the FG (“0”-curve).
Fig 1-4: The structure of the nanocrystal nonvolatile memory device. The semiconductor nanocrystals or metal nanocrystals are used as the charge storage element instead of the continuous poly-Si floating gate.
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Fig 1-5: The development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years.
Fig 1-6: The structure of the SONOS nonvolatile memory device. The nitride layer is used as the charge-trapping element.
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Fig 1-7: Energy band diagrams of SONOS Flash memory. Large ϕ0 will block electron leakage effectively and improve retention time.
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CHAPTER 2
Basic Principles of Nonvolatile Memory
2.1 Program/Erase Operation Mechanisms
Most of operations on novel nonvolatile memories, such as nanocrystal and SONOS memories are base on the concept of Flash memory. If charge has to be stored in a bit of the memory, there are some different procedures. The threshold voltage shift of a Flash memory transistor can be written as [31-32]:
∆𝑉𝑇𝐻 = − 𝑄
𝐶𝐹𝐶… … 𝑒𝑞. 2 − 1
Where Q is a negative charge stored in the FG, and FC C is the capacitances between the floating gate (FG) and control gate. The threshold voltage of the memory cell can be altered by changing the amount of charge present between the gate and the channel, corresponding to the two states of the memory cell, i.e., the binary values (“1” and “0”) of the stored bit. Figure 1-3 shows the threshold voltage shift between two states in a Flash memory. Regarding a nonvolatile memory, it can be “written” into either state “1” or “0” by either “programming”
or “erasing” operation, which are decided by the definition of memory cell itself.
There are many solutions to achieve “programming” or “erasing”. In general, hot carrier electron injection (HCEI) F-N tunneling and band to band tunneling (BTBT), are three kinds of common operation mechanism employed in novel nonvolatile memories. The three mechanisms will lead difference characteristics for nonvolatile memories.
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2.1.1 Channel Hot-Electron Injection (CHEI)
The physical mechanism of CHEI is relatively simple to understand qualitatively. An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [33]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase.
Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Figure 2-1 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields. On the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation. For an electron to overcome this potential barrier, three conditions must hold [34].
(1) Its kinetic energy has to be higher than the potential barrier.
(2) It must be directed toward the barrier.
(3)The field in the oxide should be collecting it.
During programming, the positive voltages applied to the gate and drain while the source is grounded. These voltages generate a lateral and vertical electric field along the channel. The electrons will move from the source to the drain and be accelerated by high lateral field near the drain junction in the channel. Once the electrons gain enough energy, they can surpass the energy barrier of the
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oxide layers and inject into trapping layer and be trapped. The current density of CHEI is expressed as
𝐼𝑖𝑛𝑗 = 𝐴𝑑𝐼𝑑𝑠(𝜆𝐸𝑚
𝛷𝑏 )2𝑒𝑥𝑝 �−𝛷𝑏
𝐸𝑚𝜆� … … 𝑒𝑞. 2 − 2
Here Ids is the channel current and Ad is a constant.
2.1.2 Tunneling Injection
Tunneling mechanisms are demonstrated in quantum mechanics. Basically, tunneling injection must to have available states on the other side of the barrier for the carriers to tunnel into. If we assume elastic tunneling, this is a reasonable assumption due to the thin oxide thickness involved. Namely, no energy loss during tunneling processes. The tunneling probability, depending on electron barrier height (ϕ (x)), tunnel dielectric thickness (d), and effective mass (me), is express as
𝑇 = 𝑒𝑥𝑝 �−2 � �𝛷(𝑥)∗𝑚𝑒 ħ
𝑑
0 𝑑𝑥� … … 𝑒𝑞. 2 − 3
Tunneling through the oxide can be attributed to different carrier-injection mechanisms. Which process applies depends on the oxide thickness and the applied gate field or voltage. Direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT) are the main programming mechanisms employed in memory [35-38].
2.1.2-(a) Direct Tunneling (DT)
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For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [39]. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. The direct tunneling is employed in nanocrystal memories instead. In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height, two to four orders of magnitude reduction in leakage current can still be achieved if large work function metals, such as Au or Pt [40].
2.1.2-(b) Fowler–Nordheim Tunneling (FN)
The Fowler–Nordheim (FN) tunneling mechanism occurs when applying a strong electric field (in the range of 8~10MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very steep. Therefore, there is a high probability of electrons’ passing through the energy barrier itself.
Using a free-electron gas model for the metal and the WKB (Wentzel-Kramers-Brillouim) approximation for the tunneling probability [41], one obtains the following expression for current density [42]:
𝐽 = 𝐸𝑜𝑥2 𝑒𝑥 𝑝 �−8𝜋(2𝑚𝑜𝑥∗ )12(𝑞𝛷𝑏)32
3ℎ𝑞𝐸𝑜𝑥 � … … 𝑒𝑞. 2 − 4
Where 𝛷𝑏 is the barrier height (3.1eV for Si-SiO2), ox m is the effective mass of the electron in the forbidden gap of the dielectric, h is the Planck’s constant, q is the electronic charge, and Eox is the electric field which is defined as the applied voltage divided by total thickness of the tunnel and control oxide.
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Figure 2-2 shows the F-N tunneling mechanism.
2.1.2-(c) Modified Fowler–Nordheim Tunneling (MFN)
Modified Fowler–Nordheim tunneling (MFN) is similar to the traditional FN tunneling mechanism, yet the carriers enter the nitride at a distance further from the tunnel oxide-nitride interface. MFN mechanism is frequently observed in SONOS memories. The SONOS memory is designed for low-voltage operation (<10V, depending on the Equivalent oxide thickness), a relatively weak electrical field couldn’t inject charges by DT or FN tunneling mechanism.
Figure 2-3 shows the MFN tunneling mechanism.
2.1.2-(d) Trap Assistant Tunneling (TAT)
The charge storage mediums with many traps may cause another tunneling mechanism. For example, the charges tunnel through a thin oxide and arrive to the traps of nitride layer at very low electrical field in SONOS systems. During trap assisted injection the traps are emptied with a smaller time constant then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection. Because of the sufficient injection current, trap assistant tunneling may influence in retention [43]. Figure 2-4 shows the TAT tunneling mechanism.
2.1.3 Band to Band Tunneling (BTBT)
In MOS structures, band-to-band tunneling typically occurs at high source or drain voltage and low gate voltage. In Flash memory devices, these conditions
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take place in cells under erase operations, or in unselected cells sharing the same bit line with a cell under programming. BTBT contributes to the so called Gate Induced Drain Leakage current (GIDL) [44-45] , which can be a significant fraction of the subthreshold drain leakage current and can compromise proper functioning of the substrate bias generators.
Band to band tunneling application to nonvolatile memory was first proposed in 1989. I. C. Chen and et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [46]. Band-to-band Tunneling (BTBT) process occurs in the deeply depleted doped surface region under the gate to drain or gate to source overlap region. Figure 2-5 shows the band diagram of a MOS and illustrates BTBT mechanism. In this condition, the band-to-band tunneling current density is expressed as
𝐽𝑏−𝑏 =√2𝑚∗𝑞3𝜀𝑉𝑎𝑝𝑝
2.1.3-(a) Band to Band Hot Electron Tunneling Injection
When band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant. The mechanism is at the condition for positive gate voltage and negative drain voltage. Hence, the hot electrons are injected through the tunnel oxide and then recombine the stored holes as shown in Figure 2-6.
2.1.3-(b) Band to Band Hot Hole Tunneling Injection
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The injection is applied for p-type substrate nonvolatile memory device. The mechanism is at the condition for negative gate voltage and positive drain voltage. Hence, the hot holes are injected through the tunnel oxide and then recombine the stored electrons as shown in Figure 2-7.
2.2 Nonvolatile Memory Device Reliability
For a nonvolatile memory, the performance worthy to concern is distinguishing between two states of memory cell. However, in many times operation and charges storage for a long term, the states are not easily distinguishable because of charges loss. The nonvolatility of NVM implies at least 10 years of charge retention, and the cell has to store information also after many read/program/erase cycles. Endurance (also called Cycling) and retention experiments are performed to investigate Flash memory cell reliability.
2.2.1 Retention
In any nonvolatile memory technology, it is essential to maintain data for over ten years. This means the loss of charge stored in the storage medium must be as minimal as possible. For instance, in 16Mbit Flash cell, floating gate capacitance is approximately 1fF, a threshold voltage shift of 3V is requested, and a programmed cell stores around 10,000 electrons in its floating gate. A loss of only 10% in this number can lead to a wrong read of the cell; therefore a loss of less than 2 electrons per week can be tolerated.
For SONOS memory devices, data are represented as electrons stored in the silicon nitride layer, the stored electrons leak away from the trapping layer
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through the tunnel oxide or through the interpoly dielectrics; moreover, the lateral migration of charges trapped in the silicon nitride layer also result in the wrong information [47-48]. Possible causes of charge loss are: (1) by tunneling or thermionic emission mechanisms; (2) defects in the tunnel oxide; and (3) de-trapping of charge from insulating layers surrounding the storage medium.
First, several discharge mechanisms may be responsible for time and temperature dependent retention behavior of nonvolatile memory devices.
Figure 2-8 shows a band gap diagram of a SONOS device in the excess electron state, illustrating trap-to-band tunneling, trap-to-trap tunneling, and band-to-trap tunneling, thermal excitation and Poole-Frenkel emission retention loss mechanisms [49]. These mechanisms may be classified into two categories. The first category contains tunneling processes which are not temperature sensitive (trap-to-band tunneling, trap-to-trap tunneling and band-to-trap tunneling). The second category contains the other mechanisms which are temperature dependent. Moreover, trapped electrons may redistribute vertically inside the nitride by Poole–Frenkel emission, which will give rise to a shift in the threshold voltage.
Secondly, the generation of defects in the tunnel oxide can be divided into an extrinsic and an intrinsic one. The former is due to defects in the device structure; the latter to the physical mechanisms which are used to program and erase the cell. Finally, electrons can be trapped in the insulating layers surrounding the storage medium during wafer processing. The electrons can subsequently de-trap with time, especially at high temperature. However, the charge variation results in a variation of the storage medium potential.
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Retention capability of Flash memories has to be checked by using accelerated tests which usually adopt high electric fields and hostile environments at high temperature.
2.2.2 Endurance
Endurance is the number of erase/write operations that the memory can still complete and continue to operate as specified in the data sheet. In general, Flash cells are requested to guarantee 105 program/erase cycles. This endurance requirement is sufficient for the user to take 700 photos with a 1MB size every day for 10 years [48]. As the experiment was performed applying constant pulses, the variations of program and erase threshold voltage levels are described as “program/erase threshold voltage window closure” and give a measure of the tunnel oxide aging [50-51]. In particular, the reduction of the programmed threshold with cycling is due to traps generation in the oxide and interface state generation at the drain side of the channel. The evolution of the erase threshold voltage reflects the dynamics of net fixed charge in the tunnel oxide as a function of the injected charge. The initial lowering of the erase is due to a pile-up of positive charge which enhances tunneling efficiency, while the long-term increase of the erase is due to a generation of negative traps.
The endurance characteristics give the memory threshold voltage window, which is the threshold voltages difference between the programmed state and the erased state. It is the parameters to describe how reliable is a nonvolatile memory cell. The program/erase cycles are usually measured by the FN tunneling or channel hot electron injection mechanism under room temperature
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environment.
2.3 High-k Material as Trapping Layer
In order to improve the programming speed and/or lower the programming voltage of a SONOS-type memory device, it is desirable to use a trapping material with a lower conduction band edge (higher electron affinity) to achieve a larger offset φo, as well as to provide for programming by direct tunneling at low voltages. Recently, high-k (“high-permittivity”) dielectric materials such as HfO2 and ZrO2 have been investigated to replace thermal oxide as the MOSFET gate dielectric [52-53]. A comparison of dielectric material properties is given in Table 2.1. Such materials have a lower conduction band edge than does silicon nitride. Thus, it should be advantageous to use a high-k material as the trapping layer in a SONOS-type memory device, provided that it contains a sufficient density of deep trap states. The electron trap level Et has been reported to be 1.0 eV for ZrO2 [52]; it has been reported to be 1.5eV for JVD HfO2 [53]. In principle, the trap density and trap energy level in a high-k trapping layer can be tuned by adjusting the deposition process parameters.
For SOHOS (Poly-Silicon/Oxide/High-k/Oxide/Silicon) devices, the charges may be trapped in electron and hole traps in the HfO2 layer or by charge confinement in the quantum well. From the ideal energy band diagrams of SONOS and SOHOS structures shown in Fig. 2-9 (a) and (b), respectively, the quantum well formed by the conduction band is deeper for the SOHOS structure as compared to the SONOS structure (1.6 eV compared to 1.05 eV) [54-55].
Therefore, at the same gate bias where modified Fowler–Nordheim (MFN)
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tunneling dominates, the electrons must tunnel through a thicker energy barrier in SONOS to the conduction band of the charge storage layer (Si3N4) as compared to SOHOS. The conduction band offset of Si3N4 with respect to silicon is 2.05 eV, as compared to a 1.5 eV conduction band offset of HfO2 with respect to silicon. This is illustrated in Fig. 2-10, where the modified F–N tunneling consists of direct tunneling through the thin tunnel oxide layer and F–N tunneling through the charge storage layer. Hence, electron tunneling and storage in the quantum well will be easier in SOHOS as compared to SONOS devices.
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Table 2.1: Trapping material properties
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Fig 2-1: The procedure of channel hot electrons injection (CHEI).
Fig 2-2: The approach of FN programming method, when
|𝐸𝑜𝑥| > 𝛷1 𝑋𝑂𝑇
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Fig 2-3: The approach of MFN programming method, when 𝛷1−𝛷2
𝑋𝑂𝑇 > |𝐸𝑂𝑇| > 𝛷1−𝛷2 𝑋𝑂𝑇+ (𝜀𝜀𝑂𝑋𝑁 )𝑋𝑁
Fig 2-4: The approach of TAT programming method, when 𝛷3
𝑋𝑂𝑇 > |𝐸𝑂𝑇| > 𝛷3
𝑋𝑂𝑇 + (𝜀𝜀𝑂𝑋𝑁 )𝑋𝑁
, 𝛷3 = 𝛷1 − 𝛷2−𝛷𝑡
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Fig 2-5: Band diagram of a MOS structure along the vertical direction through the depletion region illustrating band-to-band and trap-to-band tunneling mechanisms.
V
G>0Fig 2-6: The procedure of band to band hot electron injection.
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Fig 2-7: The procedure of band to band hot holes injection.
Fig 2-8: Bandgap diagram of a SONOS device in the excess electron state, showing retention loss mechanisms: trap-to band tunneling (T-B), trap-to-trap tunneling (T-T), band-to-trap tunneling (B-T), thermal excitation (TE) and Pool-Frenkel emission (PF).
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Fig 2-9: Ideal energy band diagrams for (a) SONOS and (b) SOHOS structures.
Fig 2-10: Energy band diagram schematic of the SONOS structure with HfO2
(solid lines) or Si3N4 (dashed lines) as the charge storage layer during write (program) operations.
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CHAPTER 3
Device Fabrication and Characterization 3.1 Introduction
Poly silicon–oxide–nitride–oxide–silicon (SONOS) Flash memory is one of the most attractive candidates to realize Flash memory vertical scaling.
Reducing the tunnel oxide thickness has been previously accomplished in order to increase the program speed and decrease the operation voltage of SONOS devices. However, this degrades the charge-retention capability of the device seriously. To overcome those limitations, the poly silicon–oxide–high-k–oxide–silicon (SOHOS) Flash memory has been attempted by replacing the silicon nitride layer with a high-dielectric constant (high-k) material.
The high-k memory structure has attracted much attention for nonvolatile Flash memory device due to its superior charge trapping properties compared to the conventional poly silicon floating gate. The SOHOS structure stores charges in spatial deep level traps, making it less vulnerable to a single defect in the tunnel oxide. This significantly helps to minimize the discharge of the memory cell [56]. During the program operation of the SOHOS n-channel transistor device, electrons tunnel through the tunnel oxide and are stored in the deep level traps [57]. During the erase operation under negative gate bias, electrons, trapped in the high-k material, are de-trapped and tunnel through the oxide layer from the charge storage layer into the silicon substrate. The SOHOS structure, using hafnium oxide (HfO2) as the charge storage layer, demonstrates a superior charge storage capability at low operation voltages, faster programming, and
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less over-erase problems compared to conventional SONOS devices. Therefore, the HfO2 material is selected in our research [78].
While there are many advantages of using HfO2 as trapping layer, the retention performance of HfO2 is worse than Si3N4 actually. In order to improve the retention performance, we use CF4 plasma treatment to diffuse fluorine into HfO2 after HfO2 is deposited. The fluorine is incorporated into the HfO2 trapping layer and then formed of Hf-F bonding with hafnium. Because of CF4 plasma treatment, the shallow traps would be recovered by the fluorine but the deep traps would still be left. The carriers’ de-trapping effect is decreased after program operation. Hence, the retention performance would be better.
We probe into the electrical characteristics of the capacitors and the HfO2
SOHOS memory devices. From fundamental electric characteristic data, we could know retention information. In materials analysis, we also use XPS and to analyze the devices which were carried out CF4 plasma treatment to confirm if there is the Hf-F bonding. Besides, SIMS analyses show depth profiles of fluorine in the devices.
3.2 Experimental Procedures
In this study, we make the HfO2 capacitors and the SOHOS memory device of different recipes. The detail of all process parameters (also called split table)
In this study, we make the HfO2 capacitors and the SOHOS memory device of different recipes. The detail of all process parameters (also called split table)