The SOHOS structure using HfO2 as trapping layer has attracted much attention for nonvolatile Flash memory device. While there are many advantages of it, the retention performance of HfO2 is worse than Si3N4 actually. In this study, we use CF4 plasma treatment process on the trapping layer to improve the retention performance. We fabricate the capacitors and devices with and without CF4 plasma treatment and probe into the electrical characteristics of them.
Moreover, we confirm results by material analysis. From the electrical measurement, those results indicate that the CF4 plasma treatment process is applied not only in capacitor structures but also in integrated Flash memory cells and can improve the data retention all. Hence, we consider the CF4 plasma treatment process can modify the reliabilities of Flash memory indeed. In addition, we adopt standard CMOS manufacturing processes in this study. It means that the improvement method doesn’t need impracticable process in industry manufacturing. So the CF4 plasma treatment process is suitable for the foundries which request low cost and efficiency today.
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Post deposition treatment of
HfO2
Temperature(℃) Power(W) Time(sec) Gas
Cap-R1 RTA 600 ━ 30 N2
Cap-R2 RTA 600 ━ 60 N2
Cap-R3 RTA 700 ━ 30 N2
Cap-P4 Plasma ━ 40 30 CF4
Cap-P5 Plasma ━ 50 30 CF4
Cap-P6 Plasma ━ 60 30 CF4
Cap-P7 Plasma ━ 70 30 CF4
Table 3.1: The split table of capacitors
Post deposition treatment of HfO2
Fluorine Implant
Power(W) Time(sec) Gas
Control NO treatment No ━ ━ ━
P40 Plasma Yes 40 30 CF4
P50 Plasma No 50 30 CF4
Table 3.2: The split table of SOHOS Flash memory devices
- 48 - Fig 3-1(a): Schematic cross section of the HfO2 capacitors.
150 Å Blocking oxide
5000 Å Backside Al 5000 Å Al electorde
50 Å HfO2 B.O.E strip backside oxide 30 Å Dry oxide
6” P-type Si wafer
CF4 plasma treatment
RTA
Fig 3-1(b): Process flows for fabricating various HfO2 capacitors.
- 49 -
Poly Gate 2000 Å LPCVD TEOS 200 Å HfO2 layer 50 Å
Dry Oxide 30Å
S /D junction formation P-type Si substrate
Fig 3-2(a): Schematic cross section of the HfO2 SOHOS device.
6” P-type Si wafer
400℃H2/N2 Sintering Contact hole and
metallization 5000Å Passivation oxide
LOCOS W/O fluorine implantation
2000Å Poly gate
S/D implantation & 950℃
30s activation
30 Å Dry oxide
50 Å HfO2
W/O CF4 plasma treatment
100 Å Blocking oxide
Fig 3-2(b): Process flows for fabricating HfO2 SOHOS device.
- 50 -
Fig. 3-3: SIMS profile of capacitors with CF4 plasma treatment
-10 -8 -6 -4 -2 0 2 4 6 8 10
treatment after bidirectional sweeps- 51 -
M e m or y W indow (V ) 600
oC 30S
600
oC 60S
M e m or y W indow ( V ) 60W 30S
70W 30S
Fig 3-4(c): The memory window characteristic of capacitors with CF4 plasma treatment
- 52 -
Fig 3-4(d): The comparisons of the memory window characteristic for RTA and CF4 plasma treatment capacitor
20 30 40 50 60 70
- 53 -
Fig 3-6: The comparisons of the gate leakage current-voltage (IG-V) characteristics for RTA and CF4 plasma treatment capacitors
100 101 102 103 104
Fig 3-7(a): The retention characteristics of capacitors with RTA treatment at room temperature
- 54 -
Fig 3-7(b): The retention characteristics of capacitors with CF4 plasma treatment at room temperature
- 55 -
600oC 30S 50W30S 60W30S 70W30S 0.10
Fig 3-9: The comparisons of the surface roughness for HfO2 with RTA and CF4
plasma treatment by AFM
- 56 -
600o C 30S 60W 30S 70W 30S
as-de posi t 4.8
5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8
T h ickn e ss( n m )
Fig 3-10: The comparisons of the thickness for HfO2 with RTA and plasma treatments
Fig 3-11: Schematic diagram of the capacitor with CF4 plasma treatment.
Oxygen vacancy is defined as OV in the figure
- 57 -
- 58 -
Fig 3-13(a): Program characteristics of P40 with different operating condition
1E-6 1E-5 1E-4 1E-3 0.01 0.1 1
Fig 3-13(b): Erase characteristics of P40 with different operating condition
- 59 -
Fig 3-14(a): Program characteristics of P50 with different operating condition
1E-6 1E-5 1E-4 1E-3 0.01 0.1 1
Fig 3-14(b): Erase characteristics of P50 with different operating condition
- 60 -
Fig 3-15(a): Program characteristics of Control with different operating condition
Fig 3-15(b): Erase characteristics of Control with different operating condition
- 61 -
Figure 3-16: The comparisons of the retention characteristic for Control and CF4
plasma treatment devices at room temperature
101 102 103 104
Figure 3-17: The comparisons of the retention characteristic for Control and P50 at different temperatures
- 62 -
Figure 3-18: The comparisons of the retention characteristic for Control and CF4
plasma treatment devices at room temperature after 104 cycles
1 10 100 1000 10000
0.6
Figure 3-19: The comparisons of the endurance characteristic for Control and CF4 plasma treatment devices
- 63 -
CHAPTER 4
Conclusion and Suggestion for Future Work 4.1 Conclusion
In order to improve the programming speed and lower the programming voltage of SONOS Flash memory, Si3N4 trapping layer is replaced by HfO2 trapping layer and called SOHOS-type Flash memory. While there are many advantages of SOHOS, the retention performance of SOHOS is worse than SONOS.
In this study, we focus on how to improve the reliability of SOHOS-type Flash memory. The CF4 plasma treatment process is proposed here and it can promote the reliability characteristics. From the measurement results of capacitors and devices, we confirm that the CF4 plasma treatment process is practicable. It can promote the data retention of Flash memory. The better performance attributes to that the CF4 plasma treatment process can diffuse the fluorine into the trapping layer. The fluorine is incorporated into the HfO2 trapping layer and then formed of Hf-F bonding with hafnium. Because of CF4
plasma treatment, the shallow traps would be recovered by the fluorine but the deep traps would still be left. Hence, the carriers’ de-trapping effect is decreased after program operation and the retention performance is improved.
According to the experiment result, the retention performance of SOHOS-type Flash memory, carried out CF4 plasma treatment, is actually improved. Moreover, CF4 plasma treatment is compatible with the conventional SONOS memory process and is also the low thermal budget process which
- 64 -
would not make the HfO2 film more crystallized. Therefore, we all consider the process technology is potential and expectable gradually for the memory device in the future.
4.2 Suggestions of the Future Work
1. More HRTEM images to evidence the precise thickness of the every layer.
2. Find the optimum condition of CF4 plasma treatment for memory device.
3. Apply to other memory structure using HfO2 as trapping layer.
(a) Tunnel layer ex: BE-SONOS (b) Blocking layer ex: Al2O3
(c) Gate ex: metal gate TaN
- 65 -
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