In order to improve the programming speed and/or lower the programming voltage of a SONOS-type memory device, it is desirable to use a trapping material with a lower conduction band edge (higher electron affinity) to achieve a larger offset φo, as well as to provide for programming by direct tunneling at low voltages. Recently, high-k (“high-permittivity”) dielectric materials such as HfO2 and ZrO2 have been investigated to replace thermal oxide as the MOSFET gate dielectric [52-53]. A comparison of dielectric material properties is given in Table 2.1. Such materials have a lower conduction band edge than does silicon nitride. Thus, it should be advantageous to use a high-k material as the trapping layer in a SONOS-type memory device, provided that it contains a sufficient density of deep trap states. The electron trap level Et has been reported to be 1.0 eV for ZrO2 [52]; it has been reported to be 1.5eV for JVD HfO2 [53]. In principle, the trap density and trap energy level in a high-k trapping layer can be tuned by adjusting the deposition process parameters.
For SOHOS (Poly-Silicon/Oxide/High-k/Oxide/Silicon) devices, the charges may be trapped in electron and hole traps in the HfO2 layer or by charge confinement in the quantum well. From the ideal energy band diagrams of SONOS and SOHOS structures shown in Fig. 2-9 (a) and (b), respectively, the quantum well formed by the conduction band is deeper for the SOHOS structure as compared to the SONOS structure (1.6 eV compared to 1.05 eV) [54-55].
Therefore, at the same gate bias where modified Fowler–Nordheim (MFN)
- 29 -
tunneling dominates, the electrons must tunnel through a thicker energy barrier in SONOS to the conduction band of the charge storage layer (Si3N4) as compared to SOHOS. The conduction band offset of Si3N4 with respect to silicon is 2.05 eV, as compared to a 1.5 eV conduction band offset of HfO2 with respect to silicon. This is illustrated in Fig. 2-10, where the modified F–N tunneling consists of direct tunneling through the thin tunnel oxide layer and F–N tunneling through the charge storage layer. Hence, electron tunneling and storage in the quantum well will be easier in SOHOS as compared to SONOS devices.
- 30 -
Table 2.1: Trapping material properties
- 31 -
Fig 2-1: The procedure of channel hot electrons injection (CHEI).
Fig 2-2: The approach of FN programming method, when
|𝐸𝑜𝑥| > 𝛷1 𝑋𝑂𝑇
- 32 -
Fig 2-3: The approach of MFN programming method, when 𝛷1−𝛷2
𝑋𝑂𝑇 > |𝐸𝑂𝑇| > 𝛷1−𝛷2 𝑋𝑂𝑇+ (𝜀𝜀𝑂𝑋𝑁 )𝑋𝑁
Fig 2-4: The approach of TAT programming method, when 𝛷3
𝑋𝑂𝑇 > |𝐸𝑂𝑇| > 𝛷3
𝑋𝑂𝑇 + (𝜀𝜀𝑂𝑋𝑁 )𝑋𝑁
, 𝛷3 = 𝛷1 − 𝛷2−𝛷𝑡
- 33 -
Fig 2-5: Band diagram of a MOS structure along the vertical direction through the depletion region illustrating band-to-band and trap-to-band tunneling mechanisms.
V
G>0Fig 2-6: The procedure of band to band hot electron injection.
- 34 -
Fig 2-7: The procedure of band to band hot holes injection.
Fig 2-8: Bandgap diagram of a SONOS device in the excess electron state, showing retention loss mechanisms: trap-to band tunneling (T-B), trap-to-trap tunneling (T-T), band-to-trap tunneling (B-T), thermal excitation (TE) and Pool-Frenkel emission (PF).
- 35 -
Fig 2-9: Ideal energy band diagrams for (a) SONOS and (b) SOHOS structures.
Fig 2-10: Energy band diagram schematic of the SONOS structure with HfO2
(solid lines) or Si3N4 (dashed lines) as the charge storage layer during write (program) operations.
- 36 -
CHAPTER 3
Device Fabrication and Characterization 3.1 Introduction
Poly silicon–oxide–nitride–oxide–silicon (SONOS) Flash memory is one of the most attractive candidates to realize Flash memory vertical scaling.
Reducing the tunnel oxide thickness has been previously accomplished in order to increase the program speed and decrease the operation voltage of SONOS devices. However, this degrades the charge-retention capability of the device seriously. To overcome those limitations, the poly silicon–oxide–high-k–oxide–silicon (SOHOS) Flash memory has been attempted by replacing the silicon nitride layer with a high-dielectric constant (high-k) material.
The high-k memory structure has attracted much attention for nonvolatile Flash memory device due to its superior charge trapping properties compared to the conventional poly silicon floating gate. The SOHOS structure stores charges in spatial deep level traps, making it less vulnerable to a single defect in the tunnel oxide. This significantly helps to minimize the discharge of the memory cell [56]. During the program operation of the SOHOS n-channel transistor device, electrons tunnel through the tunnel oxide and are stored in the deep level traps [57]. During the erase operation under negative gate bias, electrons, trapped in the high-k material, are de-trapped and tunnel through the oxide layer from the charge storage layer into the silicon substrate. The SOHOS structure, using hafnium oxide (HfO2) as the charge storage layer, demonstrates a superior charge storage capability at low operation voltages, faster programming, and
- 37 -
less over-erase problems compared to conventional SONOS devices. Therefore, the HfO2 material is selected in our research [78].
While there are many advantages of using HfO2 as trapping layer, the retention performance of HfO2 is worse than Si3N4 actually. In order to improve the retention performance, we use CF4 plasma treatment to diffuse fluorine into HfO2 after HfO2 is deposited. The fluorine is incorporated into the HfO2 trapping layer and then formed of Hf-F bonding with hafnium. Because of CF4 plasma treatment, the shallow traps would be recovered by the fluorine but the deep traps would still be left. The carriers’ de-trapping effect is decreased after program operation. Hence, the retention performance would be better.
We probe into the electrical characteristics of the capacitors and the HfO2
SOHOS memory devices. From fundamental electric characteristic data, we could know retention information. In materials analysis, we also use XPS and to analyze the devices which were carried out CF4 plasma treatment to confirm if there is the Hf-F bonding. Besides, SIMS analyses show depth profiles of fluorine in the devices.