4.3.1 Low Voltage Opamp
The major building block in switched-capacitor is the opamp which forms a negative feedback loop. However, the opamp denotes high power and occupies a significant silicon area. Figure 4-5 shows a general differential opamp. It has extra bias circuit to provide M3, M4 and ISS. Thus, the opamp can be replaced by an inverter using a proper offset cancellation technique. Figure 4-6 (a) shows a general
M2 M1
M3
ISS
1
Vout 1
CL
M4
2
CL
Vin
Vb
VDD
2
Vout
Figure 4-5 General differential opamp.
M1 M2
M1 M2 M4
M3 Vout Vin
Vout Vin
VDD
VDD VDD
VSS
(a) (b) Figure 4-6 (a) CMOS inverter and (b) Cascode inverter.
CMOS inverter. It is obvious that the CMOS inverter has no extra bias circuit and belongs to a single-end opamp. Therefore, the opamp with CMOS inverter architecture has the lower power consumption. Moreover, since it cascodes only two transistors, it adapts to low supply voltage as long as the supply voltage is over the overdrive voltage of cascode transistors.
Figure 4-7 shows the CMOS inverter transfer curve. The state of each transistor in each region is shown in Table 4-1. The inverter opamp is operated in region B, C, and D. When input voltage rise from analog ground (VDD /2), n-device enters in
Figure 4-7 CMOS inverter transfer curve.
A B
C
D E
Table 4-1 Summary of CMOS inverter operation.
Region p-device n-device
A Linear Cutoff
B Linear Saturated
C Saturated Saturated
D Saturated Linear
E Cutoff Linear
linear region, i.e. region D. On the other hand, the input voltage comes down and p-device is linear, i.e. region B. The operation is push-pull when the input voltage changes. In other words, it belongs to class AB. Hence, the CMOS inverter has the high power efficiency. Moreover, the push-pull inverter has a higher gain because both transistors are driven by input voltage. The gain of push-pull inverter can be derived as
(
m1 m2)(
o1 o2)
v g g r //r
A = + (4.8)
From (4.8), two transconductance amplifiers amplify the input signal to provide high gain. A high resolution sigma-delta modulator needs a high enough gain. For the conventional switched-capacitor integrator in Figure 3-17, suppose that the opamp and switches are ideal, it can be derived as
( ) ( )
V(
n 1)
When the gain is finite, A, the inverting inputs of the opamp is not virtual grounded but A
If the opamp gain is high enough, the above equation approaches to (4.9). Although the (4.8) shows that the proposed opamp can provide the gain, it is only a one-stage opamp. The simulated gain is only 42.5dB as shown in Figure 4-8. It does not provide enough gain for a high resolution sigma-delta modulator. Therefore, the gain can be a inserting the resistor into the output of the CMOS inverter as shown in Figure 4-6 (b).
Figure 4-8 AC response simulation of CMOS inverter.
The gain of the cascode inverter achieves 65.5dB with a phase margin of 80 degrees as shown in Figure 4-9.
Of course, there are other problems. The output of CMOS inverter is affected by the process variation. Also, it is sensitive to clock feed-through in a switched-capacitor integrator since the opamp is single ended. Moreover, how to decide the capacitor size to reduce the thermal noise without increasing the silicon size too much is important. These problems will be discussed in the following section.
Figure 4-9 AC response simulation of cascode inverter.
4.3.2 Integrator with Inverter Opamp
Figure 4-10 shows a general non-inverting integrator with proposed inverter opamp. The virtual ground is set to VDD /2 by tuning the size of the transistors.
However, the error of offset voltage is generated via process variation and it introduces the errors. Figure 4-11 shows the simulation results of switched-capacitor integrator in Figure 4-10 (with C1 =C2 =0.5pF and 1φ , 2φ are non-overlap clocks) at different corner case (TT, FF, SS, FS, SF). Only at TT case, the switched-capacitor integrator can correctly operate. At other cases, the input offset voltage is amplified and exceeds output swing of opamp. Therefore, the technique of auto-zeroed integrator is used to cancel input offset voltage [23-25]. Figure 4-12 shows the auto-zeroed technique on inverter opamp. During sampling period 1φ ,
φ1
φ1 φ2
φ2
Vin Vout
C1
C2
Figure 4-10 Non-inverting integrator with proposed opamp of inverter.
Figure 4-11 Simulation result of integrator in Figure 4-10 at different corner cases.
TT
FF SS
FS SF
Vin
φ1
φ2
φ1 φ2
Vos
Vin Vout
C2 C1
Figure 4-12 Auto-zeroed integrator using opamp of inverter.
Vout is at virtual ground and the input signal is sampled by C1. C1 is charged to )
V V ( C
QC1 = 1 in − os (4.11)
During integrating period 2φ , C1 is charged to
os 1 1
C C V
Q =− (4.12)
Thus, the charge is transferred from C1 to C2 and the transferred charge is
in 1 1
C C V
Q =−
∆ (4.13)
From (4.13), it is obvious that the input offset voltage can be eliminated and only input signal is transferred to the output of integrator. Figure 4-13 shows the simulation result of auto-zeroed inverter integrator at different corner cases. The input offset is canceled at all the corner cases and the output of integrator is equal to Vin +Vos, i.e.
only output offset exists and it does not effect the operation of integrator. In order to ensure correct operation of the integrator, the simulations on temperature variation are shown in Figure 4-14. It can operate at 140°C, 25°C, and −40°C.
Figure 4-13 Simulation of integrator in Figure 4-12 at different corner cases.
Figure 4-14 Simulation of integrator in Figure 4-12 at different temperatures.
TT
FF
SS
SF
FS V in
140°C
25°C
40°C
− V in
4.3.3 Switch Consideration with Single-end Opamp
For a switched-capacitor integrator with single-end opamp, it is more sensitive to clock feed-through than with fully differential opamp. Figure 4-15 shows a fully differential switched-capacitor integrator. C11 and C12 are both equal to C1, and
C21 and C22 are both equal to C2. Noise N
( )
ti is caused by clock at time t , i the output can be derived as [26]( )
[( ) ( )
]Hence, subtracting (4.14) from (4.15), it yields
( ) ( )
From (4.16), the clock feed-through noise can be removed in an ideal fully differential switched-capacitor integrator. However, the output of a single-end switched-capacitor integrator in Figure 4-12 is seriously impacted by the clock feed-through. It can be
φ1
Figure 4-15 Fully differential switched-capacitor integrator.
derived as
( ) ( )
V(
n 1)
N(
n 1)
C 1 C n V 1 n
V in
2 out 1
out − = − + − + − (4.17)
From (4.17), the clock feed-through is difficult to be eliminated. In order to reduce the clock feed-through, Figure 4-12 can be modified as shown in Figure 4-16. The clock feed-through in integrating capacitor, C2, can be reduced by S4 and S5. However, the clock noise in sampling capacitor, C1, can not be decreased from circuit structure.
Hence, the clock feed-through is only reduced from switch element. Figure 4-17 shows a switch with dummy transistors. It can reduce the clock feed-through for the sampling capacitor in single-end switched-capacitor integrator. The dummy transistors, MD1 and MD2, are used to apply the clock feed-through oppositive from M1. The area of dummy transistors can be designed to provide minimum clock feed-through.
φ1
φ2
φ1
φ2 φ2 C2 C1
Vin S1 Voutt
S2
S3
S4 S5
Figure 4-16 New integrator with low clock feed-through.
φ φ
φ
M1
MD1 MD2
Figure 4-17 Switch with dummy transistors.
4.3.4 Thermal & Flicker Noises in the Proposed Architecture
The opamp is sensitive to the effects of both thermal noise and flicker noise. The following analysis uses the models in Section 3.3. Figure 4-18 shows the noise model of the proposed inverter opamp. The noise, e , as a mean-square voltage generator ni2 in series with the gate is
f
The output noise can be derived as
( )
are the output resistances. M3 and M4 can be ignored at low frequency. From (4.19) and (4.20), the equivalent input-voltage-noise spectral density function is given by(
m1 m2)
2Figure 4-18 Noise model of proposed opamp of inverter.
C2
Figure 4-19 Opamp with capacitive feedback and capacitive loading.
The flicker noise is usually reduced by increasing gate area WL. Thus, the thermal noise dominates the noise source. Equivalent input noise with only the thermal noise is inverter opamp. The following analysis will concentrate on thermal noise.
The opamp under negative feedback is considered, as shown in Figure 4-19.
Note that no signal is presented since only the noise amplification is analyzed. The close-loop transfer function can be approximated by an one-pole expression
( ) ( )
Since the settling time is determined by how fast output current can charge the load capacitor, it can be written by
m
In other words, C is the capacitance of the dominate pole. The PSD of the white 0 input noise (4.22) is shaped at the output by the first-order low-pass filter given in (4.24). The mean-square value of the output noise from dc to infinite can be calculated as
( ) ( )
Following the above analysis, the noise in the sampling capacitor (C1) in Figure 4-16 can be derived. Assuming that all switches are modeled as V and n Ron, during 1φ , S1 and S3 are turned on and the noise model is shown in Figure 4-20. It is obvious that the PSD is
Also, the transfer function can be derived as
( ) ( )
and opamp with feedback noises are estimated. Figure 4-21 shows the small-signal and noise model in Figure 4-16 to analyze the transfer function. From Figure 4-21 (a),C1
+ the transfer function can be derived as
( ) ( )
switch is calculated by( ) ( )
From (4.30), (4.32), and (4.33), since these noises are uncorrelated, their power can be
added. Hence, the total noise power is
Using (4.35), the noise power of sampling capacitance can be given by
1
Considering an SNR of 80dB for a sigma-delta modulator, the noise power is
2
where V is a full-scale sine wave input. Substituting (4.37) into (4.36) and OSR is S set to 50 in the proposed modulator, the sampling capacitor can be estimated as
pF
Hence, the sampling capacitor must be at least 0.13pF for an SNR of 80dB.
HSPICE provides the noise simulation including thermal noise and flicker noise.
Since it is only an AC simulation, the noise of switched-capacitor can not be simulated. Hence, only the noise of the proposed opamp can be simulated as shown in Figure 4-22. The unit of y-axis is
Hz
V . The noise power can be integrated from 0 to
Figure 4-22 Noise simulation result.
( Hz V )
20k Hz (audio bandwidth) by
( ) ( )
2k 20 0
N 2 2
) rms (
N V ( f ) df 27.10
V =
∫
= µ (4.39)From the above calculation and (4.37), the proposed opamp can provide an SNR over 80dB.