Summary

The sampling rate of Nyquist A/D converters is only twice of the signal band.

However, it is difficult to achieve high resolution A/D conversion due to requirements of accurate anti-aliasing filters. The oversampling technique is a good approach to achieve high resolution A/D converters. The sigma-delta modulator is the most used architecture in the oversampling A/D converters. There are two types of quantizers in the sigma-delta modulator. One is a single-bit quantizer and another is a multi-bit quantizer. The quantization noise power of single-bit quantizer is higher than the multi-bit quantizer. However, multi-bit quantizers have much more issues than single-bit quantizers such as linearity, offset, and gain error. In order to achieve high resolution A/D conversion, high OSRs or high-order sigma-delta modulators are required. High OSR sigma-delta modulators need to have better component matching rate. High-order sigma-delta modulators have the stability problems.

Chapter 3

Design Considerations for Low-Voltage Low-Power Sigma-Delta Modulator

3.1 Introduction

Design considerations for low-voltage and low-power sigma-delta modulator will be discussed in this chapter. First the trends of low-voltage and low-power integrated circuits are presented in Section 3.2. The performance of the sigma-delta modulator is easily influenced by noises in the low-voltage system. So the noise in the sigma-delta modulator is introduced in Section 3.3. In Section3.4, they discuss power dissipation of the integrators. It includes power comparisons of switched-capacitor, continuous-time, and switched-current integrators. In Section 3.5, the driving problems of switches are discussed. It considers how the switches can be driven when the power supply of system is low.

3.2 Trends of Low-Voltage Low-Power IC

Integration of all different circuit blocks on a chip at low supply voltage is a necessary trend for the future. There are two main factors to accelerate the reduction

in the supply voltage. One is the technology scale down and another is battery life extension in portable electronics.

Although the scaling of transistor dimensions can increase the speed and density of the components on chip, the total heat dissipation has a limitation. Hence, the power must be lowered in proportional to the increase in circuit density. Decreasing supply voltage is a straight forward method to lower the power. Besides, the supply voltage needs to be decreased to prevent p-n junction break down as gate oxide thickness and channel length are scaled down. However, there is a great challenge to low-voltage circuit design since the threshold voltage is not scale down in proportion to device dimensions.

A battery is composed of one or more battery cells that are connected either in parallel or in serial. A battery cell is a device that converts chemical energy into electrical energy through a reduction-oxidation process [11]. The theoretical maximum voltage of a cell is the sum of the anode oxidation potential and the cathode reduction potential. Therefore, it is important to decrease supply voltage of system for portable electronics in order to extend the battery life is long under the same volume of the batteries.

3.3 Noises in Sigma-Delta Modulator

3.3.1 Introduction to Noises in Sigma-Delta Modulator

There are three main noises in a sigma-delta modulator as shown in Figure 3-1

BW

Power Spectrum Density

Flicker Noise

Quantization Noise White Noise

( )

f log Figure 3-1 Three main noises in a sigma-delta modulator.

[12]. One is flicker noise. It occupies main component of noises at low frequency band. Another is the thermal noise which is white noise in spectrum. For a sigma-delta modulator, the thermal noise power is usually larger than flicker noise power in the signal frequency band. The third one is the quantization noise. It had been introduced in Chapter 2. Hence, only thermal noise and flicker noise are discussed in this section.

3.3.2 Flicker Noise

There is a phenomenon between the gate oxide and the silicon substrate in a MOSFET. When the silicon crystal reaches the end at its interface, many “dangling”

bonds appear as shown in Figure 3-2. It provides an extra energy states. As charge carriers move at the interface, some are randomly trapped and released later by such energy states. This introduces “flicker” noise in the drain current [13].

The average power of flicker noise can not be predicted easily. Since it depends on the “cleanness” of the oxide-silicon interface, the flicker noise may be assumed quite different values from one CMOS technology to another [13]. It is usually modeled by a serial noise voltage source connected to the gate as shown in Figure 3-3.

The power spectral density (PSD) of this voltage is approximately given by

( )

/Hz)

f WLC f K

S

ox

vf = (V2 (3.1)

where W and L are the width and length of the channel, C_ox is the gate capacitance per unit area, f is the frequency, and K is a fabrication parameter.

Polysilicon SiO2

Silicon Crystal

Dangling Bonds

Figure 3-2 Dangling bonds at the oxide-silicon interface.

( )

^f

V_g²

Figure 3-3 The flicker noise model in a MOSFET.

3.3.3 Thermal Noise

Thermal noise is caused by the thermal motion of the charge carriers in the channel as shown in Figure 3-4. This causes a small amount of random fluctuation in the drain current. Thus, the noise is random at time domain and white in spectrum.

Note that the noise voltage has a zero mean value, but a non-zero mean-square value.

If the transistor operates in the triode region, as it does for a conducting switch, the noise can be represented by a voltage source in series with the device. The PSD of its voltage is white and can be given by

( )

f 4kTR /Hz)

S_vt = _ON (V² (3.2)

where k is the Boltzmann constant, k =1.38×10⁻²³ J/K, T is the absolute temperature of the device in degrees Kelvin, and R_ON is its on-resistance in ohms.

For a MOSFET operates in the active region, the thermal noise can be modeled by a current source in parallel with the channel as shown in Figure 3-5. The PSD of the noise current is approximately given by

( )

^{kTg /Hz)}

3 f 8

S_it = _m (A² (3.3)

Vn

Vn

t

(a) (b)

Figure 3-4 (a) Brown motion and (b) thermal noise at time domain.

( )

^f

I_d²

Figure 3-5 The thermal noise model in a MOSFET.

( )

f V_g²

( )

^f

I_d²

( )

f V_i²

Figure 3-6 A simplified equivalent model.

However, the analysis may be simplified by an equivalent input noise source as shown in Figure 3-6. In the Figure 3-6, it is an equivalent model which includes flicker and thermal noise. The (3.3) divides by g_m² results in the simplified MOSFET model. Hence, the PSD of an equivalent input noise is calculated as

( )

WLC f

K g

kT 1 3 f 8 S

ox m

eq = + (3.4)

The above equation and model will be used to analyze the impact of noise on a sigma-delta modulator.

3.4 Power Dissipation of Integrators

3.4.1 Introduction to Power Dissipation of Integrators

This section describes three architectures of integrators, switched-capacitor, continuous-time, and switched-current. It discusses the suitable architecture for a low-power sigma-delta modulator in terms of power efficiency. The power efficiency is based on the relationship between power and SNR. Since the thermal noise power is usually larger than flicker noise power and quantization noise is dominated by the architecture of sigma-delta modulator, the noise power is only considered thermal noise in this section.

3.4.2 Switched-Capacitor Integrators

The switched-capacitor circuits take advantages of the linear, well-matched capacitors available in CMOS technologies [14]. The OP amp together with the switches which are provided by MOS transistors make it possible to accurately transfer charges between capacitors. The power consumption in a switched-capacitor

Vcmi

Figure 3-7 Switched-capacitor integrator.

integrator is generally proportional to the loading. Thus, in order to minimize the power dissipation, the smallest capacitor sizes can be calculated to satisfy the SNR requirement.

Figure 3-7 shows a fully differential switched-capacitor integrator. In the following equations, it is assumed that the OP amp has infinite bandwidth and gain.

Also there are no parasitic capacitances and the only noise in the integrator is from the sampling switches. The noise power within the signal band in the integrator is calculated as

s

If the maximum amplitude of the differential input signal to the modulator is V , the _s power of a full-scale sinusoidal input is

2 P V

s2

s = (3.6)

Thus, the SNR is derived as

kT

The average power dissipation in the integrator is class A amplifier, the quiescent current is also the maximum current that can be delivered to the load. Hence, the quiescent current must be large enough to ensure that the load can be charged quickly enough to accommodate the largest expected output voltage step within the integration period [14]. Thus,

2 sampling period, and it is assumed that the integration must be completed in half the clock period. ∆V_out is given by

where V_ref is the amplitude of the differential feedback reference voltage of the modulator. By substituting (3.11) into (3.10), I_amp can be rewritten as

( ) ( )

From (3.8), (3.9) and (3.12), the power dissipation in the integrator is given by

( ) ( )

For a class B amplifier, the quiescent power consumption is zero but the power is dissipated at output voltage changes. The average power dissipation of a fully differential integrator implemented with a class B amplifier is [15]

out

where ∆V_out is the average differential output voltage step size, which can be given

in

where ∆V_in is the average input voltage of the integrator. Substituting (3.8) and (3.16) into (3.15) results in

( )

The above equation and (3.14) indicate that the minimum power dissipation in the first integrator stage of the modulator relate to SNR. Also, the class A amplifier has larger power consumption than class B amplifier. However, the above analysis is assumed that the OP amp is ideal regardless class A or B amplifier. In real cases, the linearity of class B amplifier is not as good. Thus, in order to balance power dissipation and performance, the class AB amplifier is used to implement the integrators. The relationship of power and SNR in class AB amplifier is almost identical to class B. The only difference is that the class AB has quiescent current and this quiescent current is usually much smaller than the peak load current. Thus, the relationship of power and SNR in the class AB amplifier is between class A and class B amplifiers.

3.4.3 Continuous-Time Integrators

An alternative to the switched-capacitor approach to realizing an integrator is a continuous-time integrator. Figure 3-8 shows a continuous-time integrator. The resistor noise power in the continuous-time integrator with two resistors is given by

(

_B

)

_B

Vout

Vin

R

ref fV G

Ci

R Ci

Figure 3-8 Continuous-time integrator.

Following the method in Section 3.4.2, the minimum power dissipation for the class A amplifier can be estimated as

( )

s B DD

V SNR V kTf

64

P= (3.22)

Also, the power dissipation for class B amplifier is derived as

( )

s2 in B DD

V V SNR V

kTf 32

P ∆

= (3.23)

For the continuous-time integrators, the amplifier settling requirements are generally more relaxed than switched-capacitor integrators since charge transfer takes place uniformly over the entire clock period [14]. However, the continuous-time integrators are sensitive to timing jitter and hysteresis in the feedback reference signal. Besides, it needs either off-chip resistors or highly linear on-chip resistors. Due to these implementation difficulties, the continuous-time integrator is not very popular.

3.4.4 Switched-Current Integrators

The switched-current integrator is another alternative to the switched-capacitor approach. The advantage of switched-current integrator is that it does not need linear capacitors and might be attractive for low-voltage system. Figure 3-9 shows a simple switched-current integrator. In the following analysis, the MOS transistors are viewed as square-law devices with infinite output resistance, and the switches are modeled as ideal switches in series with a resistor. The noise power within the signal band in the

VDD V_DD

Figure 3-9 Switched-current integrator.

drain current of M1 is calculated as

2

If there are only two settling time constants during the sampling interval (rising edge and falling edge), the duration of the sampling phase is

( )

Substituting (3.26) into (3.24) results in

(

_gs1¹ _th

)

Figure 3-9 includes the drain current noise of M2 in addition to that of M1. The noise in the drain current of M3 is spectrally shaped and is therefore ignored here [14].

Hence, the noise power is approximately twice and can be derived as

(

_gs ¹ _th

)

The power of the integrator input current signal is

2 P I

in2

s = (3.29)

where I is the amplitude of a full-scale sinusoidal input to the modulator. When _in

1 in I

I << , it follows square-law model of an MOS transistor and can be approximated as

where V is the amplitude of the voltage swing at the gate of M1. Substituting (3.30) _in into (3.29) results in

(

_{gs th}

)

²

From (3.28) and (3.31), the SNR can be calculated as

(

gs th

)

The power dissipation of the switched-current integrator in the Figure 3-9 is

( ) ( )

From (3.34), (3.14) and (3.18), it can be found that the switched-capacitor integrator has a better power efficiency than a switched-current integrator. Moreover, since V _in is smaller than V_DD, the power efficiency will be degraded. Also, it is difficult to achieve high linearity in a switched-current integrator when operating at a low supply voltage.

3.5 Low-Voltage Switch Techniques

3.5.1 The Problem of Low-Voltage Switches

Capacitor properties are not strongly affected by supply voltage reduction. It is difficult to properly operate the MOS switches at a low supply voltage [16]. The overdrive voltage of MOS transistor is lowered for a classical transmission gate with the supply voltage reduction. The switch conductance for different input voltages changes depending on the supply voltage as shown in Figure 3-10. In Figure 3-10 (a),

NMOS PMOS

SWING

NMOS PMOS

SWING SWING

gds

min

gds

Vthp V_dd −V_thn V_dd

Vov V_ov

Vin V_in

Vov thn

dd V

V − V_thp V_dd

Vov

gds

min

gds

(a) (b)

Figure 3-10 Transmission gate conductance at (a) standard and (b) low supply voltage.

(a) V_dd =1.8V (b) V_dd =1.0V

Figure 3-11 Switch conductance using TSMC CMOS 0.18 mµ process.

when supply voltage is the standard voltage, it is conducting around V_DD /2. In Figure 3-10 (b), however, there is a critical voltage region around V_DD /2 such that the switch is not conducting. Figure 3-11 shows that the simulation results of a transmission gate at V_dd =1.8V and V_dd =1.0V using TSMC CMOS 0.18 mµ process. It is obvious that when supply voltage is 1v, it is almost not conducting around V_DD/2. Hence, it must be operated at proper voltage or by alternative approach such that the switch is conducting. In this section, there are four approaches being pointed out when the supply voltage is low voltage.

3.5.2 Low-Threshold Voltage

Low-threshold voltage is a necessity for low supply voltage. There are two ways to obtain low threshold voltage MOS transistors. One is to use multi-threshold process.

The series connection of low threshold voltage devices shows relatively good conductance and low leakage current as shown in Figure 3-12 [12]. However, this

Vt

Low φ

φ

Figure 3-12 A composite switch with low threshold voltage.

kind of solution has the expense of extra mask steps and higher cost. Another way is to use circuit techniques to reduce the threshold voltage. The threshold voltage is given by

BS F F

ox GB ox

th 2 2 V

C

V =φ −Q + φ +γ φ − (3.35)

The above equation shows that V depends on _th V_BS. The bulk to source junction is reverse biased and causes a threshold voltage increase due to the body effect. If the body effect is reversed, the threshold voltage will be decreased.

It is difficult to overcome the problem of the current leakage using low threshold voltage when switch is off. When switch is in off-state, i.e. the weak inversion, the drain current is

⎟⎟

⎟⎟

⎠

⎞

⎜⎜

⎜⎜

⎝

⎛

⎟⎟=

⎠

⎞

⎜⎜⎝

= ⎛

q nkT exp V nV I

exp V I

I ₀ ^gs

th gs 0

D (3.36)

From (3.36), it is obvious that there is leakage current when the threshold voltage is reduced. This leakage limits the resolution of switched-capacitor circuits due to the break of the charge conservation function.

3.5.3 Voltage Multiplier

In order to guarantee an adequately low switch resistance in a low voltage environment, the clock voltage used to drive at least one of the two switch transistors can be bootstrapped beyond the supply voltage range. Therefore, voltage multiplier technique is implemented. It converts available voltage to a higher voltage. Figure 3-13 shows a voltage boosted clock driver. C₁ and C₂ are charged to V_DD via the cross-coupled NMOS M1 and M2. When the input clock, CK, goes high, the

CK

Vbulk

Vdd

CKsw

C2

M1 M2

M3

C1

Figure 3-13 Voltage boosted clock driver.

Vbulk

Vdd

CK

Figure 3-14 Voltage doubler.

output voltage, CK_sw, approaches 2V_DD. The output voltage does not actually reach 2V_DD due to charge sharing with parasitic capacitances. C₂ must be large enough to boost the gates of many MOS transistors to reduce the impact of charge sharing. To decrease the potential for latch-up, the bulk of the PMOS M3 is tied to an on-chip voltage doubler. The bulk of the PMOS switch is biased by the circuit shown in Figure 3-14 [17].

3.5.4 Clock Bootstrapped Switch

Figure 3-15 shows the clock bootstrapped switch composed of a capacitor, a NMOS switch, and several switches. In the phase 2φ , the capacitor is pre-charged to VDD and the signal switch is turned off as the gate of switch is connected to V_SS. While in 1φ , the gate of signal switch is V_DD +V_in such that the signal switch provides a constant conductance. Hence, it can handle the rail-to-rail input signal.

N-switch Coffset

VDD

VSS

VSS

Vin

S1 S2

S3 S4

S5

φ2 φ2

φ1 φ1

φ2

Figure 3-15 The architecture of clock bootstrapped switch.

Figure 3-16 shows the real transistor-level implementation of the switch bootstrapping circuit. Transistors MN1, MP1, MN2, MP2, and MN4 correspond to the five ideal switches S1-S5 respectively. MN3S triggers MP1 at the beginning of 1φ while MN3

φ1

φ2

φ2 φ₂

MN1 MN2

MN3

MNT4

MN4 MN3S

N-switch MP1

MP2 MP3

Coffset

VDD

VDD

Vout Vin

A

Figure 3-16 Transistor-level implementation of bootstrapped switch.

keeps it on as the voltage on node A rises to V . MNT4 has been added to prevent _in the gate-drain of MN4 from exceeding V_DD during 1φ while it is off [18].

3.5.5 Switched Opamp Technique

Figure 3-17 shows a classic non-inverting integrator. For switch driving problem, the switches in Figure 3-17 can be classified into two types. One is that the switches having one channel terminal connected to the level of reference voltage (S2 and S3) or virtual ground (S4). Another is that the switch is not connected to ground but to a signal source (S1). The first type of switches can always be turned on if the switch driving voltage is at least a threshold voltage above its source which is at ground level.

However, the second type of switches needs to be switched over the entire signal range. Therefore, the switched opamp technique can be used to replace this critical switch as shown in Figure 3-18. In phase 1φ , the opamp is turned off and samples

Vout

Vin

S1

S2 S3

C1 S4

C2

φ2 φ1

φ1 φ2 φ2

Figure 3-17 Non-inverting integrator.

Vin V^out

S1

S4

S2 S3

C1

C2

φ1 φ2

φ1 φ2

φ1 φ2

φ2

Figure 3-18 The switched opamp principle.

signal from the output of opamp inside the dotted box. In phase 2φ , the opamp is turned on to transfer charge to the output. However, this approach introduces extra active elements such that the chip area is increased. Fortunately, the power consumption is not affected since these opamps are turned on half of the period [19].

3.6 Summary

There are many details to take care in the design of a low-voltage, low-power sigma-delta modulator. The low-voltage system is sensitive to the noise interference.

The quantization noise is dominated by noise transfer function. The thermal noise can be reduced by increasing capacitance. The switched-capacitor integrator is a better architecture to implement a sigma-delta modulator. It has higher power efficiency and can be easily realized in practical circuits. Also, the switch driving problem is an important issue in a low voltage system. Several techniques used to solve low supply voltage switched-capacitor integrator, such as low threshold process, voltage multiplier, clock bootstrapped switch, and switched opamp. In the following section,

The quantization noise is dominated by noise transfer function. The thermal noise can be reduced by increasing capacitance. The switched-capacitor integrator is a better architecture to implement a sigma-delta modulator. It has higher power efficiency and can be easily realized in practical circuits. Also, the switch driving problem is an important issue in a low voltage system. Several techniques used to solve low supply voltage switched-capacitor integrator, such as low threshold process, voltage multiplier, clock bootstrapped switch, and switched opamp. In the following section,

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