This section presents the test setup for the DUT (device under test), as shown in Figure 4-36. The input signal of the sigma-delta modulator is generated by a low distortion double balanced sine waveform generator, Precision Audio Analyzer as shown in Figure 4-37 (a). The output bit streams of the DUT are fed to a logic analyzer, HP 16702B, as shown in Figure 4-37 (b).
However, the Precision Audio Analyzer only provides the AC components of the balanced signal. Thus, the AC coupled and input termination circuit provides the DC components of the balanced signal, as shown in Figure 4-38. This circuit limits the signal bandwidth to prevent the aliasing of the high-frequency noise. Moreover, it
DUT
Vin Vcmi
Vref Vclk
Vdd,D
Digital Output Vdd,A
Power Regulator
&
Reference Voltage Generator
AC Coupled Circuit &
Input Termination Circuit
Clock Generator Audio
Precision
Logic Analyzer
Power Regulator
&
1.0-V Voltage Generator
Figure 4-36 Experimental test setup.
(a) (b)
Figure 4-37 (a) Precision Audio Analyzer and (b) Logic Analyzer.
C1
C2
C3
C4 R5
R6 R7
R8 R1
R3
R2
R4
+
VSRC
−
VSRC
+
Vin
−
Vin
VDD
VDD Vcmi
Figure 4-38 AC coupled and input termination circuit.
attenuates charge kickback from the sampling switches in the DUT into the source.
The loading imposed on the source by this circuit can lead to obtain harmonic distortion if the capacitors in the filter output are too large [14].
Since the sigma-delta modulator is a mixed-mode system, the digital and analog power lines must be separated. The analog and digital powers are generated by LM317 regulators as shown in Figure 4-39. The input of the regulator is connected to
LM317
R1
R2 C2
C1 Vin
Vout
Vin Vout ADJ
Figure 4-39 The application of LM317 regulator.
a 9.0V power supply or battery. Of course, battery is better than the power supply because it can provide cleaner voltage. The output of regulator circuit is set by two external resistors, R1 and R2. The output voltage can be predicted by
R R I
1 R 25 . 1
V ADJ
1
out 2⎟⎟+ ⋅
⎠
⎜⎜ ⎞
⎝
⎛ +
= (4.45)
where IADJ is the DC current which flows out of the adjustment terminal ADJ of the regulator. C1 is the input bypass capacitor and C2 is the output capacitor. Both of them improve transient response [27].
The minimum output voltage of the LM317 regulator is about 1.5V. In order to generator a 1.0V supply voltage for the sigma-delta modulator, the analog and digital voltage sources for DUT is implemented using OP27 as shown in Figure 4-40. The OP27 acts as a unity gain buffer for the voltage set by R1 potentiometer at its input.
The 6V voltage is generated by LM317 regulator in Figure4-39. The DC voltages for
+9V
-9V +6V
R1
R2 R3
R4 C4
C1 C6
C2 C5
Vout
Figure 4-40 Reference (1.0V) voltage generator.
L1
Vout
Vin
H 100µ C1
F
10µ 1C2µF 0.1C3µF 0.01C4µF
Figure 4-41 Bypass filter at reference voltage generator.
the DUT must be connected to a bypass circuit as shown in Figure 4-41. It can decouple low frequency noise for large input and high frequency noise for small input.
Chapter 5 Conclusions
5.1 The Figure-Of-Merit (FOM)
Table 5-1 shows the comparisons of sigma-delta modulators for the audio applications. The range of paper survey is below 1mW and above 60dB of SNR. It is difficulty to compare power efficiency. In general, the figure-of-merit (FOM) is a criterion for the power efficiency of sigma-delta modulators. The FOM is defined as
P DR f kT FOM 4 ⋅ B⋅
= (5.1)
where k is Boltzmann’s constant, T is the absolute temperature, fB is the signal bandwidth, and P is the power consumption. Although the signal bandwidth and power consumption are considered in FOM, the supply voltage is not taken into account [29]. To make a fair comparison, Table 5-2 shows the FOM comparisons for the sigma-delta modulators in Table 5-1. This work achieves the highest FOM except [29] with 90nm process. The area is not included into FOM and it is difficulty to compare due to different capacitor processes (poly-to-poly, metal-to-metal, and so on) and structures. In general, the area is dominated by capacitors for sigma-delta
Table 5-1 The comparison of sigma-delta modulator for the audio application.
Name & Year VDD SNDR SNR DR BW Power Process
Tille, 2004 [28] 1.8V 72dB 77dB - 8kHz 1mW 0.25µ m CMOS Yao, 2004 [29] 1.0V 81dB 85dB 88dB 20kHz 140µ W 90nm CMOS Nielsen,2004 [30] 1.8V 62dB - 67dB 3.6kHz 108µ W 0.35 µ m CMOS Safarian, 2003 [31] 2.5V - 83dB 86dB 4kHz 125µ W 0.25 µ m CMOS Gerfers, 2003 [32] 1.5V 70dB 73dB 80dB 25kHz 135µ W 0.5 µ m CMOS
Hu, 2003 [33] 0.9V - 74dB - 10kHz 38µ W 0.18 µ m CMOS
Samid, 2003 [34] 1.5V 60dB 62dB - 50kHz 50µ W 0.5 µ m CMOS Sauerbrey, 2002 [35] 0.7V 67dB 70dB 75dB 8kHz 80µ W 0.18 µ m CMOS Qunying, 2001 [36]* 1.2V 63dB 75dB 75dB 3.4kHz 38µ W 0.35 µ m CMOS Gerfers, 2001 [37] 1.5V 65dB - 75dB 25kHz 230µ W 0.5 µ m CMOS Dessouky, 2000 [38] 1.0V 85dB 87dB 88dB 25kHz 950µ W 0.35 µ m CMOS Peluso, 1998 [39] 0.9V 62dB 76dB 77dB 16kHz 40µ W 0.5 µ m CMOS Peluso, 1997 [19] 1.5V 66dB - 74dB 3.4kHz 100µ W 0.7 µ m CMOS vanderZwan, 1996 [40] 2.2V - - 80dB 3.4kHz 200µ W 0.5 µ m CMOS This Work 1.0V 69dB 75.7dB 76.6dB 20kHz 40µ W 0.18 µ m CMOS
* Only simulation results.
Table 5-2 The FOM comparison.
Name & Year VDD DR BW Power Area Process FOM
Yao, 2004 [29] 1.0V 88dB 20kHz 140µW 0.18mm 2 90nm CMOS 1493e-6 Gerfers, 2003 [32] 1.5V 80dB 25kHz 135µW - 0.5µ m CMOS 306.8e-6 Sauerbrey, 2002 [35] 0.7V 75dB 8kHz 80µW 0.082mm2 0.18µ m CMOS 52.39e-6 Qunying, 2001 [36]* 1.2V 75dB 3.4kHz 38µW - 0.35µ m CMOS 46.88e-6 Gerfers, 2001 [37] 1.5V 75dB 25kHz 230µW 1.2mm 2 0.5µ m CMOS 56.95e-6 Dessouky, 2000 [38] 1.0V 88dB 25kHz 950µW 0.63mm 2 0.35µ m CMOS 275.1e-6 Peluso, 1998 [39] 0.9V 77dB 16kHz 40µW 0.85mm 2 0.5µ m CMOS 332.2e-6 Peluso, 1997 [19] 1.5V 74dB 3.4kHz 100µW 0.5mm 2 0.7µ m CMOS 14.15e-6 This Work 1.0V 76.6dB 20kHz 40µW 0.54mm2 0.18µ m CMOS 378.7e-6
* Only simulation results.
5.2 Conclusions
The sigma-delta modulators have been proposed to achieve the high resolution A/D converters. This thesis presents the simple switched-capacitor structure with inverters to implement a 40µW third-order sigma-delta modulator with single-loop architecture. In Table 5-1, almost all the lower power modulators are single-loop due to less circuit blocks and component matching requirements. Also, the switched-capacitor circuits provide more accurate integrators and higher power efficiency. Moreover, the inverter opamp consumes less chip area and power consumption than the general opamp structures. Therefore, this thesis achieves a peak SNDR of 69.01dB, SNR of 75.74dB, and DR of 76.61dB at a sampling rate 2M Hz and a signal bandwidth of 20k Hz under single 1.0V supply voltage.
However, there are problems in this architecture, offset and clock feed-through due to inverter opamp and single ended integrators. The clock feed-through noise is still lager in proposed single-end integrators with dummy switches than differential-end integrators.
Although the SNDR in the proposed sigma-delta modulator is only 69.01dB, it is high enough for the hearing aids applications [21]. Only 40µW power consumption extends battery life longer. The chip area is also reduced by using inverter opamp.
Therefore, the proposed sigma-delta modulator is suitable for hearing aids and other similar audio applications.
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