Low-Voltage Switch Techniques

From (3.34), (3.14) and (3.18), it can be found that the switched-capacitor integrator has a better power efficiency than a switched-current integrator. Moreover, since V _in is smaller than V_DD, the power efficiency will be degraded. Also, it is difficult to achieve high linearity in a switched-current integrator when operating at a low supply voltage.

3.5 Low-Voltage Switch Techniques

3.5.1 The Problem of Low-Voltage Switches

Capacitor properties are not strongly affected by supply voltage reduction. It is difficult to properly operate the MOS switches at a low supply voltage [16]. The overdrive voltage of MOS transistor is lowered for a classical transmission gate with the supply voltage reduction. The switch conductance for different input voltages changes depending on the supply voltage as shown in Figure 3-10. In Figure 3-10 (a),

NMOS PMOS

SWING

NMOS PMOS

SWING SWING

gds

min

gds

Vthp V_dd −V_thn V_dd

Vov V_ov

Vin V_in

Vov thn

dd V

V − V_thp V_dd

Vov

gds

min

gds

(a) (b)

Figure 3-10 Transmission gate conductance at (a) standard and (b) low supply voltage.

(a) V_dd =1.8V (b) V_dd =1.0V

Figure 3-11 Switch conductance using TSMC CMOS 0.18 mµ process.

when supply voltage is the standard voltage, it is conducting around V_DD /2. In Figure 3-10 (b), however, there is a critical voltage region around V_DD /2 such that the switch is not conducting. Figure 3-11 shows that the simulation results of a transmission gate at V_dd =1.8V and V_dd =1.0V using TSMC CMOS 0.18 mµ process. It is obvious that when supply voltage is 1v, it is almost not conducting around V_DD/2. Hence, it must be operated at proper voltage or by alternative approach such that the switch is conducting. In this section, there are four approaches being pointed out when the supply voltage is low voltage.

3.5.2 Low-Threshold Voltage

Low-threshold voltage is a necessity for low supply voltage. There are two ways to obtain low threshold voltage MOS transistors. One is to use multi-threshold process.

The series connection of low threshold voltage devices shows relatively good conductance and low leakage current as shown in Figure 3-12 [12]. However, this

Vt

Low φ

φ

Figure 3-12 A composite switch with low threshold voltage.

kind of solution has the expense of extra mask steps and higher cost. Another way is to use circuit techniques to reduce the threshold voltage. The threshold voltage is given by

BS F F

ox GB ox

th 2 2 V

C

V =φ −Q + φ +γ φ − (3.35)

The above equation shows that V depends on _th V_BS. The bulk to source junction is reverse biased and causes a threshold voltage increase due to the body effect. If the body effect is reversed, the threshold voltage will be decreased.

It is difficult to overcome the problem of the current leakage using low threshold voltage when switch is off. When switch is in off-state, i.e. the weak inversion, the drain current is

⎟⎟

⎟⎟

⎠

⎞

⎜⎜

⎜⎜

⎝

⎛

⎟⎟=

⎠

⎞

⎜⎜⎝

= ⎛

q nkT exp V nV I

exp V I

I ₀ ^gs

th gs 0

D (3.36)

From (3.36), it is obvious that there is leakage current when the threshold voltage is reduced. This leakage limits the resolution of switched-capacitor circuits due to the break of the charge conservation function.

3.5.3 Voltage Multiplier

In order to guarantee an adequately low switch resistance in a low voltage environment, the clock voltage used to drive at least one of the two switch transistors can be bootstrapped beyond the supply voltage range. Therefore, voltage multiplier technique is implemented. It converts available voltage to a higher voltage. Figure 3-13 shows a voltage boosted clock driver. C₁ and C₂ are charged to V_DD via the cross-coupled NMOS M1 and M2. When the input clock, CK, goes high, the

CK

Vbulk

Vdd

CKsw

C2

M1 M2

M3

C1

Figure 3-13 Voltage boosted clock driver.

Vbulk

Vdd

CK

Figure 3-14 Voltage doubler.

output voltage, CK_sw, approaches 2V_DD. The output voltage does not actually reach 2V_DD due to charge sharing with parasitic capacitances. C₂ must be large enough to boost the gates of many MOS transistors to reduce the impact of charge sharing. To decrease the potential for latch-up, the bulk of the PMOS M3 is tied to an on-chip voltage doubler. The bulk of the PMOS switch is biased by the circuit shown in Figure 3-14 [17].

3.5.4 Clock Bootstrapped Switch

Figure 3-15 shows the clock bootstrapped switch composed of a capacitor, a NMOS switch, and several switches. In the phase 2φ , the capacitor is pre-charged to VDD and the signal switch is turned off as the gate of switch is connected to V_SS. While in 1φ , the gate of signal switch is V_DD +V_in such that the signal switch provides a constant conductance. Hence, it can handle the rail-to-rail input signal.

N-switch Coffset

VDD

VSS

VSS

Vin

S1 S2

S3 S4

S5

φ2 φ2

φ1 φ1

φ2

Figure 3-15 The architecture of clock bootstrapped switch.

Figure 3-16 shows the real transistor-level implementation of the switch bootstrapping circuit. Transistors MN1, MP1, MN2, MP2, and MN4 correspond to the five ideal switches S1-S5 respectively. MN3S triggers MP1 at the beginning of 1φ while MN3

φ1

φ2

φ2 φ₂

MN1 MN2

MN3

MNT4

MN4 MN3S

N-switch MP1

MP2 MP3

Coffset

VDD

VDD

Vout Vin

A

Figure 3-16 Transistor-level implementation of bootstrapped switch.

keeps it on as the voltage on node A rises to V . MNT4 has been added to prevent _in the gate-drain of MN4 from exceeding V_DD during 1φ while it is off [18].

3.5.5 Switched Opamp Technique

Figure 3-17 shows a classic non-inverting integrator. For switch driving problem, the switches in Figure 3-17 can be classified into two types. One is that the switches having one channel terminal connected to the level of reference voltage (S2 and S3) or virtual ground (S4). Another is that the switch is not connected to ground but to a signal source (S1). The first type of switches can always be turned on if the switch driving voltage is at least a threshold voltage above its source which is at ground level.

However, the second type of switches needs to be switched over the entire signal range. Therefore, the switched opamp technique can be used to replace this critical switch as shown in Figure 3-18. In phase 1φ , the opamp is turned off and samples

Vout

Vin

S1

S2 S3

C1 S4

C2

φ2 φ1

φ1 φ2 φ2

Figure 3-17 Non-inverting integrator.

Vin V^out

S1

S4

S2 S3

C1

C2

φ1 φ2

φ1 φ2

φ1 φ2

φ2

Figure 3-18 The switched opamp principle.

signal from the output of opamp inside the dotted box. In phase 2φ , the opamp is turned on to transfer charge to the output. However, this approach introduces extra active elements such that the chip area is increased. Fortunately, the power consumption is not affected since these opamps are turned on half of the period [19].

3.6 Summary

There are many details to take care in the design of a low-voltage, low-power sigma-delta modulator. The low-voltage system is sensitive to the noise interference.

The quantization noise is dominated by noise transfer function. The thermal noise can be reduced by increasing capacitance. The switched-capacitor integrator is a better architecture to implement a sigma-delta modulator. It has higher power efficiency and can be easily realized in practical circuits. Also, the switch driving problem is an important issue in a low voltage system. Several techniques used to solve low supply voltage switched-capacitor integrator, such as low threshold process, voltage multiplier, clock bootstrapped switch, and switched opamp. In the following section, the voltage multiplier will be used as the basic components to implement the sigma-delta modulator.

Chapter 4

A 40- µ W Switched-Capacitor Sigma-Delta Modulator

4.1 Introduction

Problems and existing solutions of the low-voltage sigma-delta modulator have been introduced in the previous chapter. Some of them are used in this chapter. A 40-µ W switched-capacitor sigma-delta modulator with TSMC CMOS 0.18µ m process is realized. In order to save power and decrease chip size, the opamp is implemented using the modulated inverter. The modulated inverter is a single-end opamp with no extra bias circuit for low power consumption. The simulation results show that peak SNDR is 69.01dB, ENOB is 11-bit, and dynamic range is 76.61dB with oversampling ratio of 50 is audio applications (signal bandwidth is 20k Hz).

4.2 System Architecture and Specifications

In Chapter 2, the design consideration for sigma-delta modulator has been introduced, SNR performance and stability issues. Similar analysis method is used in

)

1I(z

a a₂I(z) ^y

x

Figure 4-1 Single-loop and multiple-feedback topology.

this section to design a third-order sigma-delta modulator. Figure 4-1 shows a single-loop and multiple-feedback topology of the sigma-delta modulator. ^I

( )

^z

represents integration, i.e. ^z−1/

(

^1−z−1

)

^. a is integrator coefficient and the i

quantizer is 1-bit. The advantage of this architecture is less component matching requirement. However, there is the instability problem for high-order design. Hence, the following analysis is concerntrated on the integrator coefficients for the third-order sigma-delta modulator. The noise transfer function of this topology can be calculated by [20]

∑∏

= =

where n is the order and k is the quantizer’s gain which is considered to be a constant.

The amplitude of the noise transfer function can be approximated (for low frequency) by

Hence, the noise power is calculated by

∫

∫

Form (4.4), it is obvious that increasing integrator coefficient, a , improves the _i performance of SNR. In Section 2.4, however, there is the stability criterion, i.e.^maxNTF

( )

^ejω <^1.5

ω . Hence, SNR is limited by stability. According to [20], it can be concluded that the SNR of the loops is maximized when the product of all effective integrator coefficients is approximately

4 Following (4.5) and general audio applications specification (like [21]), the value of the effective integrator coefficient can be chosen through MATLAB simulation. For a third-order sigma-delta modulator, the loop coefficients are set to [0.2, 0.4, 0.4]. The noise transfer function is derived as

( )

and signal transfer function is

( )

Also substituting these loop coefficients into (4.4) with OSR=128. SNR can be calculated and is approximately equal to 98dB. Figure 4-2 shows a system simulation result of power spectrum density with the third-order sigma-delta modulator. From the simulation results, SNR is also equal to 98dB. Figure 4-3 shows the simulation of SNR versus the input signal amplitudes and the dynamic range is roughly 102dB.

Figure 4-2 System simulation result of the third-order sigma-delta modulator.

Figure 4-3 Simulation of SNR versus input amplitude.

Figure 4-4 shows the pole-zero plot of the noise transfer function with these loop coefficients. These poles of the noise transfer function are at [0.7409, 0.9295+j0.3444, 0.9295-j0.3444]. These poles are in the region of convergence (ROC), i.e. this transfer function is convergent. In other words, the third-order sigma-delta modulator is stable if overall system is a linear model. Since the improvement of SNR can be obtained by using more general functions with spreading zeros, it reduces the total noise power in the signal band. Moving the poles closer to the zeros reduces the gain of out-of-band noise transfer function [22]. However, it must increase feedback path otherwise will have the difficulties in the implementation. Moreover, it will increase power consumption if zeros are spread over the signal range.

Figure 4-4 Pole-zero plot of noise transfer function.

4.3 Implementation of Integrators

4.3.1 Low Voltage Opamp

The major building block in switched-capacitor is the opamp which forms a negative feedback loop. However, the opamp denotes high power and occupies a significant silicon area. Figure 4-5 shows a general differential opamp. It has extra bias circuit to provide M3, M4 and I_SS. Thus, the opamp can be replaced by an inverter using a proper offset cancellation technique. Figure 4-6 (a) shows a general

M2 M1

M3

ISS

1

Vout 1

CL

M4

2

CL

Vin

Vb

VDD

2

Vout

Figure 4-5 General differential opamp.

M1 M2

M1 M2 M4

M3 Vout Vin

Vout Vin

VDD

VDD VDD

VSS

(a) (b) Figure 4-6 (a) CMOS inverter and (b) Cascode inverter.

CMOS inverter. It is obvious that the CMOS inverter has no extra bias circuit and belongs to a single-end opamp. Therefore, the opamp with CMOS inverter architecture has the lower power consumption. Moreover, since it cascodes only two transistors, it adapts to low supply voltage as long as the supply voltage is over the overdrive voltage of cascode transistors.

Figure 4-7 shows the CMOS inverter transfer curve. The state of each transistor in each region is shown in Table 4-1. The inverter opamp is operated in region B, C, and D. When input voltage rise from analog ground (V_DD /2), n-device enters in

Figure 4-7 CMOS inverter transfer curve.

A B

C

D E

Table 4-1 Summary of CMOS inverter operation.

Region p-device n-device

A Linear Cutoff

B Linear Saturated

C Saturated Saturated

D Saturated Linear

E Cutoff Linear

linear region, i.e. region D. On the other hand, the input voltage comes down and p-device is linear, i.e. region B. The operation is push-pull when the input voltage changes. In other words, it belongs to class AB. Hence, the CMOS inverter has the high power efficiency. Moreover, the push-pull inverter has a higher gain because both transistors are driven by input voltage. The gain of push-pull inverter can be derived as

(

_{m1 m2}

)(

_{o1 o2}

)

v g g r //r

A = + (4.8)

From (4.8), two transconductance amplifiers amplify the input signal to provide high gain. A high resolution sigma-delta modulator needs a high enough gain. For the conventional switched-capacitor integrator in Figure 3-17, suppose that the opamp and switches are ideal, it can be derived as

( ) ( )

V

(

n 1

)

When the gain is finite, A, the inverting inputs of the opamp is not virtual grounded but A

If the opamp gain is high enough, the above equation approaches to (4.9). Although the (4.8) shows that the proposed opamp can provide the gain, it is only a one-stage opamp. The simulated gain is only 42.5dB as shown in Figure 4-8. It does not provide enough gain for a high resolution sigma-delta modulator. Therefore, the gain can be a inserting the resistor into the output of the CMOS inverter as shown in Figure 4-6 (b).

Figure 4-8 AC response simulation of CMOS inverter.

The gain of the cascode inverter achieves 65.5dB with a phase margin of 80 degrees as shown in Figure 4-9.

Of course, there are other problems. The output of CMOS inverter is affected by the process variation. Also, it is sensitive to clock feed-through in a switched-capacitor integrator since the opamp is single ended. Moreover, how to decide the capacitor size to reduce the thermal noise without increasing the silicon size too much is important. These problems will be discussed in the following section.

Figure 4-9 AC response simulation of cascode inverter.

4.3.2 Integrator with Inverter Opamp

Figure 4-10 shows a general non-inverting integrator with proposed inverter opamp. The virtual ground is set to V_DD /2 by tuning the size of the transistors.

However, the error of offset voltage is generated via process variation and it introduces the errors. Figure 4-11 shows the simulation results of switched-capacitor integrator in Figure 4-10 (with C₁ =C₂ =0.5pF and 1φ , 2φ are non-overlap clocks) at different corner case (TT, FF, SS, FS, SF). Only at TT case, the switched-capacitor integrator can correctly operate. At other cases, the input offset voltage is amplified and exceeds output swing of opamp. Therefore, the technique of auto-zeroed integrator is used to cancel input offset voltage [23-25]. Figure 4-12 shows the auto-zeroed technique on inverter opamp. During sampling period 1φ ,

φ1

φ1 φ2

φ2

Vin V_out

C1

C2

Figure 4-10 Non-inverting integrator with proposed opamp of inverter.

Figure 4-11 Simulation result of integrator in Figure 4-10 at different corner cases.

TT

FF SS

FS SF

Vin

φ1

φ2

φ1 φ2

Vos

Vin V_out

C2 C1

Figure 4-12 Auto-zeroed integrator using opamp of inverter.

Vout is at virtual ground and the input signal is sampled by C₁. C₁ is charged to )

V V ( C

Q_C1 = _{1 in} − _os (4.11)

During integrating period 2φ , C₁ is charged to

os 1 1

C C V

Q =− (4.12)

Thus, the charge is transferred from C₁ to C₂ and the transferred charge is

in 1 1

C C V

Q =−

∆ (4.13)

From (4.13), it is obvious that the input offset voltage can be eliminated and only input signal is transferred to the output of integrator. Figure 4-13 shows the simulation result of auto-zeroed inverter integrator at different corner cases. The input offset is canceled at all the corner cases and the output of integrator is equal to V_in +V_os, i.e.

only output offset exists and it does not effect the operation of integrator. In order to ensure correct operation of the integrator, the simulations on temperature variation are shown in Figure 4-14. It can operate at 140°C, 25°C, and −40°C.

Figure 4-13 Simulation of integrator in Figure 4-12 at different corner cases.

Figure 4-14 Simulation of integrator in Figure 4-12 at different temperatures.

TT

FF

SS

SF

FS V in

140°C

25°C

40°C

− V in

4.3.3 Switch Consideration with Single-end Opamp

For a switched-capacitor integrator with single-end opamp, it is more sensitive to clock feed-through than with fully differential opamp. Figure 4-15 shows a fully differential switched-capacitor integrator. C₁₁ and C₁₂ are both equal to C₁, and

C21 and C₂₂ are both equal to C₂. Noise N

( )

t_i is caused by clock at time t , _i the output can be derived as [26]

( )

[

( ) ( )

]

Hence, subtracting (4.14) from (4.15), it yields

( ) ( )

From (4.16), the clock feed-through noise can be removed in an ideal fully differential switched-capacitor integrator. However, the output of a single-end switched-capacitor integrator in Figure 4-12 is seriously impacted by the clock feed-through. It can be

φ1

Figure 4-15 Fully differential switched-capacitor integrator.

derived as

( ) ( )

V

(

n 1

)

N

(

n 1

)

C 1 C n V 1 n

V _in

2 out 1

out − = − + − + − (4.17)

From (4.17), the clock feed-through is difficult to be eliminated. In order to reduce the clock feed-through, Figure 4-12 can be modified as shown in Figure 4-16. The clock feed-through in integrating capacitor, C₂, can be reduced by S4 and S5. However, the clock noise in sampling capacitor, C₁, can not be decreased from circuit structure.

Hence, the clock feed-through is only reduced from switch element. Figure 4-17 shows a switch with dummy transistors. It can reduce the clock feed-through for the sampling capacitor in single-end switched-capacitor integrator. The dummy transistors, MD1 and MD2, are used to apply the clock feed-through oppositive from M1. The area of dummy transistors can be designed to provide minimum clock feed-through.

φ1

φ2

φ1

φ2 φ2 ^C2 C1

Vin S1 V_outt

S2

S3

S4 S5

Figure 4-16 New integrator with low clock feed-through.

φ φ

φ

M1

MD1 MD2

Figure 4-17 Switch with dummy transistors.

4.3.4 Thermal & Flicker Noises in the Proposed Architecture

The opamp is sensitive to the effects of both thermal noise and flicker noise. The following analysis uses the models in Section 3.3. Figure 4-18 shows the noise model of the proposed inverter opamp. The noise, e , as a mean-square voltage generator _ni² in series with the gate is

f

The output noise can be derived as

( )

are the output resistances. M3 and M4 can be ignored at low frequency. From (4.19) and (4.20), the equivalent input-voltage-noise spectral density function is given by

(

_{m1 m2}

)

²

Figure 4-18 Noise model of proposed opamp of inverter.

C2

Figure 4-19 Opamp with capacitive feedback and capacitive loading.

The flicker noise is usually reduced by increasing gate area WL. Thus, the thermal noise dominates the noise source. Equivalent input noise with only the thermal noise is inverter opamp. The following analysis will concentrate on thermal noise.

The opamp under negative feedback is considered, as shown in Figure 4-19.

Note that no signal is presented since only the noise amplification is analyzed. The close-loop transfer function can be approximated by an one-pole expression

( ) ( )

Since the settling time is determined by how fast output current can charge the load capacitor, it can be written by

m

In other words, C is the capacitance of the dominate pole. The PSD of the white ₀ input noise (4.22) is shaped at the output by the first-order low-pass filter given in (4.24). The mean-square value of the output noise from dc to infinite can be calculated as

( ) ( )

Following the above analysis, the noise in the sampling capacitor (C₁) in Figure 4-16 can be derived. Assuming that all switches are modeled as V and _n R_on, during 1φ , S1 and S3 are turned on and the noise model is shown in Figure 4-20. It is obvious that the PSD is

Also, the transfer function can be derived as

( ) ( )

and opamp with feedback noises are estimated. Figure 4-21 shows the small-signal and noise model in Figure 4-16 to analyze the transfer function. From Figure 4-21 (a),

C1

+ the transfer function can be derived as

( ) ( )

switch is calculated by

( ) ( )

switch is calculated by

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