Introduction

In order to improve device performance, thinner gate insulators are required for deep sub-micron metal semiconductor field effect transistors (MOSFETs). In this situation, high-k dielectrics are effective for suppressing gate leakage current. However, a major issue in applying high-k dielectrics is that it inherently possess a high density of structural defects, both intrinsic and process/integration related. Thus, Performance degradation for high-k is a concern, particularly for the low power applications where the high-k dielectric thickness is in the range containing high defect density. High defect density in the bulk of high-k gate dielectric and the interfaces in the gate stack structure are the major causes for bias temperature instability (BTI) of V_Th instability (or reliability degradation) [1] as

well as mobility degradation [2-3]. In order to eliminate these traps, a variety of nitridation techniques were proposed to incorporate nitrogen into the high-k films. Previous studies show that fluorine passivation is very robust and can be used to improve the reliability of high-κ dielectric MOSFETs [4-6]. Several research studies have demonstrated the application of fluorine ion implantation techniques to improve the electrical characteristics of high-k dielectric MOSFETs

by eliminating inherent bulk traps. However, it is worth pointing out that an additional thermal annealing process is required to activate the fluorine ions and cure the damage created by fluorine ion implantation, which can result in forming thicker EOT.

In this work, we studied the defect passivation with fluorine in a hafnium oxide High-K gate dielectric with poly-si gate. The novel fluorinated gate stack device exceeds the BTI targets with sufficient margin. Fluorinated silicate glass (FSG) films have also been utilized in the intermetal dielectric (IMD) layer, and in the fluorinated gate dielectric for integrated circuit (IC) manufacturing technology [7-8].

It has been demonstrated that the addition of fluorine atoms into SiO2

can reduce the film dielectric constant to 3.2 or lower, which leads to reduced cross-talk, RC time delay, and power consumption. Using FSG film to serve as IMD can meet the requirement of multilevel interconnection in ultralarge-scale integrated circuit (ULSI) applications. Moreover, the fluorinated gate dielectric can improve the gate oxide/Si substrate interface immunity against hot-carrier impact, and exhibits better dielectric breakdown characteristics [9]. On the other hand, Kim et al. have proposed using the FSG film to serve as a diffusion source to introduce fluorine atoms into the poly-Si film [10].

2.2 Experimental Procedure

The experiment propose a simple and effective fluorine passivation technique that involves the use of a FSG passivation layer

embedded in the HfO2/SiON gate dielectric. In the proposed fluorine passivation method, we introduce the fluorine atoms into the HfO2

bulk material and other interfaces from the FSG passivation layer.

2.2.1 Device Fabrication Flow

First, we use local oxidation of silicon (LOCOS) process was used for device isolation. n-MOSFET device was fabricated on 6-inch p-type Si with (1 0 0)-oriention. After removing the 300Å sacrificial oxide, RCA clean was performed with HF-dip last, and immediately followed by a conventional RTA at 800 °C for 30 sec in N2O ambient to form about 1 nm interfacial oxynitride layer (SiON). Afterwards, HfO2 film of approximately 30Å was deposited by atomic vapor deposition (AVD^TM) in an AIXTRON Tricent○^R system at a substrate temperature

of 500 °C, followed by 600 °C N2 RTA for 30 sec in order to improve the film quality. The physical thickness of the SiON and HfO2 films was measured by optical N&K analyzer. A 200 nm poly-silicon was deposited by low pressure chemical vapor deposition (LPCVD).

Subsequently, gate electrode was defined by I-line lithography stepper and etched by ECR etching system. After removing sidewall spacer, S/D extension implantation was implemented by As implantation. Spacer formation was carried out by plasma-enhance chemical vapor deposition (PECVD) and then S/D implantation was executed by Arsenic implantation. Rapid thermal anneal (RTA) was performed at 950 °C for 30 sec in N₂ ambient to activate dopants.

Afterward, a 3000Å-thick FSG passivation layer (or PMD dielectric) was deposited by PECVD at 300 °C with SiH4, N2O, and CF4 as precursor gases (see Fig. 2-1). To investigate the effect of various fluorine contents on the device performances, the SiH4 and N2O flow rates were adjusted at 4 and 60 sccm, and a variety of flow rates 10, 20, and 30 sccm were used to introduce CF4 into the PECVD chamber and deposit various FSG passivation layers. The various CF4 flow rates of 10, 20, and 30 sccm correspond to the FSG A, FSG B, and FSG C passivation layers, respectively. Table 2.1 lists the conditions of precursors to grow FSG passivation layers. For comparison, the control sample was deposited with a 3000Å-thick conventional PECVD-TEOS passivation layer. Since the FSG film shows poor thermal stability and the fluorine atoms may diffuse out of the FSG film during post thermal annealing, a 1000 Å-thick SiNx capping layer on the FSG film was successively deposited by PECVD to improve the thermal stability of the FSG film and avoid the diffusion of fluorine atoms out of the FSG film [11]. After passivation layer formation and contact hole pattering. And Al-Si-Cu metallization was deposited by PVD system and then pattering. Finally, sintering process at 400 °C for 30 minutes in N₂ ambient is eventually executed to finish our novel fluorinated devices in this thesis.

The main process flow is summarized in Fig. 2-2 and schematic cross section of HfO₂/SiON n-MOSFETs with FSG passivation layer is illustrated in Fig. 2-3.

2.2.2 Suitable Measurement Setup

The experimental setup for the I-V, C-V, charge pumping and reliability measurements of MOS device is illustrated in Fig. 2-4.

Based on the PC controlled instrument environment, the complicated and long-term characterization procedures for analyzing the intrinsic and degradation behavior in MOSFET’s can be easily achieved.

Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were evaluated by a HP4156A precision semiconductor parameter analyzer and an HP4284 LCR meter, respectively. The capacitance equivalent thickness (CET) of the gate dielectrics was obtained from high frequency (100 KHz) capacitance-voltage (C-V) curve at strong inversion without considering quantum effect. The interface trap density (N_it) was analyzed using the charging pumping method. A 1MHz for frequency and 10 ns for rising/falling time square pulse waveform provided by HP8110A with fixed amplitude level (V_A) is applied to NMOS gate. We keep V_A at 1.2V while increase V_Base

frome -1.0V to 0.9V by step 0.1V, i.e., the base voltage varied from inversion to accumulation. The parameter analyzer HP4156A is used to measure the charge pumping current (I_CP). Fig. 2-5 shows the

configuration of measurement setup used in our charging pumping experiment. A MOSFET with gate area AG gives the charging pumping current as Equation (2-1) :

CP = G it

I qA fN (2-1)

Interface trap density could be extracted from the above equation.

The total trap density increase, ∆N_T, which includes the increase of interface trap density and bulk trap density was calculated from ∆V_Th

by assuming that the charge was trapped at the interface between the dielectric and the substrate. It expresses as follows Equation (2-2) :

∆ _T = ∆ ^Th

G

N C V

qA (2-2)

and bulk trap density also can be calculated as follows Equation (2-3) :

∆N_B = ∆N_T − ∆N_it (2-3)

For mobility characterization, the electron mobility for n-MOSFETs was extracted using split C-V method .

2.3 Result and Discussions

2.3.1 Basic Device Characteristics

The C-V curves (100 KHz) of FSG A, B, C, and control samples are show in Fig. 2-6. The capacitance of the sample with CF4 gas introduced decreases compared to that of the as-deposited sample, which no obvious difference in C-V curves in substance. When CF4 gas flow rate is lower than 20 sccm, it indicates a slight increase of CET in FSG A and FSG B. However, the introduced CF4 gas is much more than the allowable F concentration, residual damage for the CET after sintering step can be observed. The resultant CET increment faster may be an excess amount of F incorporation into high-k film stacks [12-13] or the absorption of moisture from the atmosphere in the

plasma-deposited FSG film is the principle root-cause, which many studies indicated that the phenomenon of moisture (H2O) absorption in the plasma-deposited FSG film has been observed because the Si–F bonds present are highly reactive with moisture [14-15]. Fig. 2-7 was investigated with respect to CET and flat-band voltage (V_FB , not shown) [16] for the samples. We can see the fact that the V_FB has

shifted to positive direction as the CF4 flow rate increases and EOT is also affected by the presence of F atoms. This is point out that decrease of positively charged traps or increase of negatively charged traps [17-19].

Fig. 2-8 shows the gate leakage current of n-MOSFET with HfO2/SiON gate stack under both inversion and accumulation modes.

It can obviously noted that with FSG passivation layer, the leakage current is significantly suppressed for both polarities. Specially, the reduction under normal operation condition, i.e., inversion mode, is around 40% of magnitude lower. One of the reasons for the exhibited gate leakage current reduction may be a thicker CET for two splits of fluorinated devices. Hence, it extrapolates that the CF4 gas flow rate even up to 30 sccm doesn’t deteriorate gate leakage current, and on the contrary, the reduction extent of gate leakage current is dependent on the flow rate of CF4 gas introduced into FSG passivation from measurement data of Weibull distributions shown in Fig. 2-9. Fig.

2-10 demonstrates the transconductance (Gm) as a function of gate voltage for both gate dielectrics. The Gm is normalized by CET

(Capacitance Equivalent Thickness), which is 37.9Å, 39.4Å, 42.1Å, and 38.3Å for FSG A, B, C, and control sample, respectively. The peak transconductance is 28%, 42%, and 67% for FSG passivation with respect to TEOS passivation. Fig. 2-11 shows the improved normalized linear drain–current I_D which FSG P.L. is 24% higher

above than TEOS P.L. and the inset of subthreshold slope (S.S.) reduced 9.6% for the CF4 introduced samples, indicating that fluorinated CMOS HfO2 has better interface characterization. Previous study [20] on Zr-silicate indicates that electron transport in the channel can be degraded by the coulomb scattering of negative charges in the bulk film, and Fischetti et. al [21] also points out that electron mobility in the inversion layer is affected by remote phonon scattering due to ionic polarization in high-k films. Therefore, the peak transconductance degradation in HfO2/SiON stack is probably due to charges or traps in the bulk film, as evidenced by the positive shift in C-V curve in Fig. 2-6, even if the interface-state densities are kept to be small. Besides, as shown Fig. 2-12, the V_Th distribution is less affected by the addition of F for FSG A and B wihile a increased V_Th can be observed for FSG C, which also corresponding with the V_FB

trend (not shown) due to negatively charged traps.

Fig. 2-13 presents the excellent output drive current characteristics ( I_D −V_DS ) under various normalized gate biases (V_GS −V_Th), which almost 12% enhancement in magnitude of I_{D Sat,}

for FSG P.L. with respect to TEOS P.L.. The gate voltage has been normalized with respect to threshold voltage to minimize the effect of threshold voltage. We also understand that normalized I_{D Sat,} and

transconductance max peak depends on the flow rate of CF4 gas or the amount of fluorine incorporated from Fig. 2-14. The improvements are believed to be intimately related not only to the better interface quality but also to the reduced bulk trap density. To quantify the interface state density by the CP current measurement, which the CP peak height is approximately proportional to the interface state density (N_it) along the channel, Fig. 2-15 can be seen that the trend

is quite consistent with that in subthreshold swing, as shown in inset of Fig. 2-11. Channel mobility is dependant on the nature of gate dielectric between Si substrate and high-k gate dielectric.

CF4-introduced high-k gate dielectrics suffer from CET increased whereas mobility can be enhanced shown in Fig. 2-16. The peak mobility for FSG C device is 7% higher than the control, and the high field mobility at 0.8MV/cm is 49% higher than the control, which is correlated with the higher Gm,max (see inset of Fig. 2-16) and higher output current characteristics. The electron mobility at 0.8MV/cm for the fluorinated device is 68% of SiO2 universal curve. Clearly, as the amount of introduced CF4 gas become elevated, peak mobility increasing with decreasing interface state density implying the weak and dangling bonds, associated with interface and trap states, are passivated and released strain bonds by fluorine atoms, leading to the

enhanced electrical characteristics show in Fig. 2-17.

Fig 2-18 indicates the subthreshold swing of devices with different passivation layers as a function of channel length. And we find that subthreshold swing for FSG P.L. shows the better interface states than TEOS P.L.. Thus, the FSG P.L. will improve the subthreshold swing in device. The relation between drain current and channel length for all splits of HfO2/SiON gate stack n-MOSFET is shown in Fig. 2-19 and Gm

is in Fig. 2-20. When channel length becomes shorter, the improvement is more obvious. Fig 2-21 shows the V_Th -roll-off

characteristics with different passivation layers. When channel length is less than 1µm, V_Th-roll-off phenomenon is more serious for TEOS

P.L. while the FSG devices effectively suppress this behaviour to the same extend with increasing the amount of CF4 gas flow. In short, it was found that all fundamental electrical properties, including the CET, flat-band voltage, threshold voltage, drive current, interface state density (N_it), swing, mobility, gate leakage current, and short channel

effect are almost non-degradation instead of surprise enhancement for device performance between the four splits with FSG and TEOS P.L..

2.3.2 Current Transport mechanism

Using the carrier separation method, the carrier type is investigated for the fresh devices. The carrier of gate leakage can be separated into holes and electrons. Fig 2-22 (a) and (b) are carrier

separation results for the TEOS sample under inversion and accumulation regions, respectively. It is shown that the S/D current that electrons tunnel through gate stack dominates the gate leakage for the inversion region while the substrate current that holes tunnel through gate stack dominates the gate leakage for the accumulation region. The carrier separation results for the FSG sample are shown in Fig. 2-23 (a). The case for the accumulation region is similar to the TEOS sample (see Fig. 2-23 (b)), i.e., holes from the substrate dominate the gate leakage. However, the case for the inversion region is different from the TEOS sample, where I_SD is obviously

suppressed.

These trends can be explained by the band diagram shown in Fig.

2-24 (a) and carrier separation experiment shown in Fig. 2-24 (b).

The substrate current I_SUB corresponds to the hole current from the gate, while the S/D current I_SD corresponds to the electron current

from Si substrate under inversion region. Holes supply from the gate valence band in n-MOSFETs is limited by the generation rate of minority holes in n⁺ gate. On the other hand, the probability of carriers from S/D that tunnel through gate stack is strongly affected by tunneling distance and barrier height of ~ 1.0 nm interfacial oxynitride layer. As a result of the asymmetry of the HfO2/SiON band structure, it is more difficult for holes to tunnel through gate stack, as compared to electrons. Consequently, the current through the gate stack should be smaller for holes, as compared to electrons. In

n-MOSFETs, electron current from the channel is the predominant injection current under stressing. The leakage component under accumulation region could also be explained by band diagrams shown in Fig. 2-25 (a), and the current component flow in carrier separation experiment is shown in Fig. 2-25 (b). In addition, we can see that the magnitude of the leakage current in inversion is larger than that in accumulation. A plausible explanation can be understand from the asymmetric band diagram’s point of view.

Fig. 2-26 (a) and (b) show gate current I_g as a function of V_g for

the HfO²/SiON gate stacks measured at several different temperatures up 100 °C in inversion and accumulation regions, respectively, for two different passivation layers. The current is temperature dependent that increases with increasing temperature.

This implies that the conduction mechanism of gate current is trap-related, i.e., trap-assisted tunneling (TAT), Frenkel-Poole, etc.

Base on the equation of Frenkel-Poole (F-P) :

2 φ Where B is a constant in terms of the trapping density in the HfO2

film, φ_B is the barrier height, E_ox is the electric field in HfO² film, ε₀

is the free space permittivity, εH is HfO2 dielectric constant, k_B is

Boltzmann constant, and T is the temperature measured in Kelvin. Fig.

2-27 shows the F-P plot for the source/drain current in inversion region. Fig. 2-28 shows the F-P plot for the substrate current in inversion region. The solid lines are fitting curves for all temperatures.

In the high voltage I_SD and I_SUB, an excellent linearity for each

current characteristic can be obtained, indicating that FSG and TEOS passivation layers exhibit the F-P conduction mechanism for the gate leakage current in nature. The barrier height φ_B and the dielectric constant ε_H of HfO²/SiON gate stacks can be calculated from the

intercept of y axis and the slope of the fitting curves according to Equation (2-6). The εH value is found to be around 21 for the TEOS

sample and around 23 for the FSG sample. On the other hand, the fitting parameters for the hole and electron barrier heights are 1.34eV and 1.12eV, respectively, for the FSG sample, as compared to 1.27eV and 1.07eV for the TEOS sample. Note that the barrier height for electrons has changed from 1.07eV for TEOS to 1.12eV for FSG sample, and for holes has changed from 1.27eV for TEOS to 1.34eV for FSG sample. This indicates that the trap position has moved closer to the conduction and valence band of the poly-si gate after FSG P.L.

process. The band diagrams are shown in Fig. 2-29 (a) and (b) for the TEOS and FSG P.L. sample, respectively. We consider the case when the injected carriers flow across HfO²/SiON by hopping via the trap

sites with energy barrier φB, whose value depends on the fabrication

process [22]. This experimental results indicate that the position of traps level in the FSG sample can be deeper than the TEOS sample, and the energy barrier φ_B for electrons is clearly lower than that for holes about 0.2eV in both samples.

2.4 GIDL Effect on Off-State Leakage

Gate-induced drain leakage (GIDL) is attributed to the band-to-band tunneling (BBT) process taking place in the deep-depleted drain region underneath the gate oxide. Electron-hole pairs are generated by the tunneling of valence band electrons into the conduction band and subsequently collected by the drain and substrate separately. The schematic energy band diagram of the gate-drain overlap region is shown in Fig. 2-30. The BBT (I_BBT) could be simplified as Equation (2-7) [23] :

= exp(− ) the energy bandgap. From these equations, it should be noted that

BBT current is dependent on E_g. Therefore, if E_g decreases, the band-to-band tunneling current (I_BBT) increases. Although Hf-based

high-k dielectrics have been investigated to reduce gate leakage current, it has been observed that bulk traps significantly enhance the GIDL current in devices with high-k dielectrics [24]. Hence, bulk traps enhanced gate-induced leakage (BTE-GIDL) current will be found to improve for the devices with FSG passivation layer.

To suppress the BTE-GIDL, the role of charge trapping in high-k film should be understood in detail. As shown in Fig. 2-31, the band diagrams before and after electron trapping are denoted by the solid line and the dashed line, respectively. At low V_DG (TAT mechanism),

the much lower electron barrier height for poly-gate/high-k than that for hole at high-k/I.L. interface, electron injected from poly-gate dominates trapping mechanism. The charges induced by injected

the much lower electron barrier height for poly-gate/high-k than that for hole at high-k/I.L. interface, electron injected from poly-gate dominates trapping mechanism. The charges induced by injected