Summary

In this chapter, a novel fluorinating technique method for high-k dielectric passivation, using a FSG process as n-MOSFETs passivation layer was presented. We have performaed a systematical investigation of electrical characteristics. Significant device performance improvement in devices with FSG P.L. were found, such as the excellent subthreshold swing, increased transconductance, higher current drive, improved channel electron mobility, and alleviated SCE etc., as compared to the control TEOS sample. As shown in Fig. 2-33, for FSG P.L., the number of interface states by using charge pumping method can be diminished that is attributed to the passivated interface traps by the incorporation of fluorine atoms generated from CF⁴ gas in deposition process of PECVD chamber.

Specially, the presence of fluorine in the FSG devices lead to a decrease in the numbers of bulk traps from intrinsic hysteresis effect

[25-26] shown in Table 2-2, which summarizing the impact of the FSG passivation layer for HfO2/SiON gate stack n-MOSFETs. Experimental results show a good correlation between the bulk trap density and the BTE-GIDL. It was observed that incorporating fluorine into HfO2/SiON gate stack to minimize the bulk traps could effectively reduce the BTE-GIDL.

2.5 References

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stacks for advanced CMOS devices”, IEDM Tech. Dig., pp451, 2001

[3] H. –J. Cho, C. Y. Kang, C. S. Kang, R. Choi, Y. H. Kim, M. S. Akbar, C. H. Choi, S. J. Rhee, and J. C. Lee, “The effects of nitrogen in HfO/sub 2/ for improved MOSFET performance”, IEEE

semiconductor Device Research Symposium. pp68, 2003.

[4] H.-H. Tseng, P. J. Tobin, E. A. Hebert, S. Kalpat, M. E. Ramon, L.

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C. Capasso, O. Adetutu, D. Sing, J. Conner, E. Luckowski, B.W.

Chan, A. Haggag, S. Backer, R. Noble, M. Jahanbani, Y. H. Chiu, and B. E. White, “Defect passivation with fluorine in a TaxCy/high-κ gate stack for enhanced device threshold voltage stability and performance,” in IEDM Tech. Dig., 2005, pp.

696–699.

[5] M. Inoue, S. Tsujikawa, M. Mizutani, K. Nomura, T. Hayashi, K.

Shiga, J. Yugami, J. Tsuchimoto, Y. Ohno, and M. Yoneda,

“Fluorine incorporation into HfSiON dielectric for Vth control and its impact on reliability for Poly-Si Gate pFET,” in IEDM Tech. Dig., 2005, pp. 413–416.

[6] K.-I. Seo, R. Sreeenivasan, P. C.McIntyre, and K. C. Saraswat,

“Improvement in high-κ (HfO2/SiO2) reliability by incorporation of fluorine,” in IEDM Tech. Dig., 2005, pp. 417–420.

[7] K. Y. Chou and M. J. Chen: IEEE Electron Device Lett. 22 (2001) 466.

[8] G. Q. Lo, W. Ting, J. H. Ahn, D. L. Kwong, and J. Kuehne: IEEE Trans. Electron Devices 39 (1992) 148.

[9] Y. Mitani, H. Satake, Y. Nakasaki, and A. Toriumi: IEEE Trans.

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Appl. Phys. 38 (1999) 2247.

[11] P. F. Chou and Y. L. Cheng: Int. Symp. VLSI Technology, Systems, and Applications, 2001, p. 257.

[12] L. Tsetseris, X. J. Zhou, D. M. Fleetwood, R. D. Schrimpf, and S. T. Pantelides, “Dual role of fluorine at the Si−SiO2 interface,”

Appl. Phys. Lett., vol. 85, no. 21, p. 4950, Nov. 2004.

[13] A. Kazor, C. Jeynes, and I. W. Boyd, “Fluorine enhanced oxidation of silicon at low temperatures,” Appl. Phys. Lett., vol. 65, no. 12, pp. 1572–1574, Sep. 1994

[14] H. Miyajima, R. Katsumata, Y. Nakasaki, Y. Nishiyama, and N.

Hayasaka: Jpn. J. Appl. Phys. 35 (1996) 6217.

[15] W. J. Chang, M. P. Houng, and Y. H. Wang: Jpn. J. Appl. Phys. 38 (1999) 4642.

[16] Chen Yong, Zhao J ianming, Han Dedong, Kang J infeng, andHan Ruqi, “Extraction of Equivalent Oxide Thickness for HfO2 High-k Gate Dielectrics,” CHINESE JOURNAL OF SEMICONDUCTORS, vol.

27, no. 5, 2006

[17] Seo, K.; Sreenivasan, R.; Mclntyre, P.C.; Saraswat, K.C.

“Improvement in High-k (HfO2/SiO2) Reliability by Incorporation of Fluorine,” in IEDM Tech. Dig., 2005, pp. 417-420.

[18] Inoue, M.; Tsujikawa, S.; Mizutani, M.; Nomura, K.; Hayashi, T.;

Shiga, K.; Yugami, J.; Tsuchimoto, J.; Ohno, Y.; Yoneda, M.,

“Fluorine Incorporation into HfSiON Dielectric for Vth Control and Its Impact on Reliability for Poly-Si Gate pFET,” in IEDM Tech. Dig., 2005, pp. 413-416.

[19] Raghavasimhan Sreenivasan and Pul C. Mclntyre, “Effect of impurities on the fixed charge of nanoscale HfO2 film grown by atomic layer deposition,” Appl. Phys. Lett., Vol. 89, pp. 112903, 2006.

[20] T. Yamaguchi, H. Satake, N. Fukushima, “Degradation of current drivability by the increase of Zr concentrations in Zr-silicate MISFET,” IEDM Technical Digest, 2001, p.663

[21] M. V. Fischetti, D. A. Neumayer, and E. A. Catier, “Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-k insulator: The role of remote phonon scattering,” J. Appl. Phys., vol.90, p.4587,2001.

[22] T. Yamaguchi, H. Satake, N. Fukushima, and A. Toriumi, “Band Diagram and Carrier Conduction Mechanism in ZrO2/Zr-silicate/Si MIS Structure Fabricated by Pulsed-laser-ablation Deposition, “ in IEDM Tech. Dig., pp. 19-22, 2000.

[23] J. Chen, T. Y. Chen, I. C. Chen, P. K. Ko, and C. Hu,

“Subbreakdown Drain Leakage Current in MOSFET,” IEEE Electron Device Lett., vol. 8, no. 11, pp. 515-517, 1987.

[24] M. Gurfinkel, J. S. Suehle, J. B. Bernstein, and Yoram Shapira,

“Enhanced gate induced drain leakage current n HfO2 MOSFETs due to remote interface trap-assisted tunneling”, Tech. Dig. IEEE International Electron Devices Meeting, S29-4, (2006).

[25] T. L. Meisenheimer, D. M. Fleetwood, M. R. Shanevfelt, L. C.

Riewe, “1/f noise In n- and p- channel MOS devices through irradiation and annealing”, IEEE Trans. Electron Devices, Vol. 38, p. 1297, 1991

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CF ⁴ N ² O SiH ⁴ Control 0

FSG A 10 FSG B 20 FSG C 30

60 4

Table 2.1 Conditions of gas flow rates to deposit FSG passivation layers.

Fig. 2.1 The PECVD system used in this experiment.

4 2 4

、 、

( SiH N O CF ) Gas

P.M.D.

Unit : sccm

Fig. 2.2 The process flow of n-MOSFETs with FSG passivation layer.

Standard NMOS flow before High-k depostion RCA clean + HF-last dip wet pre-cleaning

SiON target ~1nm : RTA 800 °C 30sec in N

2

O ambient MOCVD of 30Å HfO

2

(500 °C)

PDA 600 °C 30 sec in N

2

ambient

Undoped poly-Si deposition 200nm and pattering

Ext. S/D implant + Spacer formation + Deep S/D implant

Capping layer deposition : PECVD-SiN

x

Followed by NMOS BEOL process on bulk silicon, including metalliztion of 900nm Al-Si-Cu and N

2

sinter 30 min at 400 °C

Activation RTA 950 °C 30 sec in N

2

ambient

Passivation dielectric deposition by PECVD

Wafer Split – FSG P.L. : CF

4

- 10, 20, 30 sccm

Fig. 2.3 Cross section of HfO

2

/SiON n-MOSFET with FSG

passivation layer.

Fig. 2.4 The experimental setup for the basic electrical characteristics and long-term reliability test measurements.

Fig. 2.5 Basic experimental setup of charging pumping measurement.

Switch

HP 4156

GPIB n-substrate

p⁺ Source

p⁺ Drain p⁺

poly-Si

h⁺

e

-HP 81110A Pulse Generator

-2 -1 0 1 2 0.2

0.4 0.6 0.8 1.0

FSG A FSG B FSG C TEOS

C a p a c it a n c e [ µ F /c m 2 ]

Appiled Gate Voltage (V)

Fig. 2.6 The C-V characteristics of HfO

2

gate dielectrics with various CF

4

as precursor gas.

FSG A FSG B FSG C TEOS

3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3

CET

C E T [ n m ]

Fig. 2.7 Comparison of CET for all splits, including fluorinated and as-deposited samples.

Area:50µm×50µm Frequency:100 KHz

n-MOSFETs

Fig. 2.8 Gate leakage current as a function of gate voltages of HfO2/SiON gate stack with (symbol line) and without (solid line) CF

4

gas incorporation both under inversion and accumulation regions

Fig. 2.9 The Weibull plot distributions at V

GS

-V

Th

=1.0V of J

g

Fig. 2.10 Normalized transconductance as a function of gate voltage for TEOS and FSG passivation layer.

Fig. 2.11 Normalized NMOS I

DS

of fluorinated device is 24%

higher above than that for the control device, and the subthreshold properties is inset in the figure.

Å

-0.02 -0.01 0.00 0.01 0.02 0.03 0.04

0.0

Fig. 2.12 Cumulative probability of the threshold voltage (V

th

).

Fig. 2.13 Drain current versus drain voltage (I

D

-V

D

) curves

of FSG C and TEOS P.L. under various normalized

gate biases which 0V, 0.3V, 0.6V, 0.9V, and 1.2V,

respectively.

Fig. 2.14 Comparsion of normalized saturation drain current

Fig. 2.15 Interface states density as a function of V

Base

for

HfO

2

/SiON high-k gate stacks with FSG and TEOS

P.L..

Fig. 2.16 Electron mobility for fluorinated device is

enhanced as compared with the control device.

Inset comparison of transconductance max peak (G

m,max

).

Fig. 2.17 Comparsion of interface states density correlated with electron mobility for all splits.

0.0 0.5 1.0 1.5 2.0 2.5 3.0

0 1 2 3 60

80 100 120

S u b th re s h o ld S w in g [m V /d e c ]

Channel Length [ _µ m ]

FSG A FSG B FSG C TEOS

Fig. 2.18 The subthreshold swing versus channel length for all splits of HfO

2

/SiON gate stack n-MOSFETs.

Fig. 2.19 The drain current versus channel length for all splits of HfO

2

/SiON gate stack n-MOSFETs.

0 1 2 3

0.2 0.4 0.6 0.8 1.0 1.2 1.4

I D ,S a t @ V G S -V T h = 1 .2 V [m A ]

Channel Length [ µ m ]

FSG A FSG B FSG C TEOS

Fig. 2.20 The maximum transconductance versus channel length for all splits of HfO

2

/SiON gate stack

n-MOSFETs.

Fig. 2.21 Threshold voltage roll off characteristics for all splits of HfO

2

/SiON gate stack n-MOSFETs.

0 1 2 3

Fig. 2.22 Carrier separation under (a) inversion region and (b) accumulation region in the TEOS sample.

NMOSFET

-8 -6 -4 -2 0 2 4 6 8

samples under both inversion and accumulation

regions.

Fig. 2.24 Poly-gate n-MOSFET with HfO

2

/SiON gate stack under inversion region (a) band diagrams, and (b) schematic illustration of carrier separation

experiment.

n

⁺

n

⁺

n

⁺

Vg(+) _Hole

injection

Electron current Electron

injection (-)I

_SD

(-)I

_B

P-Sub

inversion layer

e

-I

_SD

(-)

h

⁺

I

_SUB

(-)

I.L.

HfO

₂

n

⁺

-gate P-Sub

(a)

(b)

Fig. 2.25 Poly-gate n-MOSFET with HfO

2

/SiON gate stack under accumulation region (a) band diagrams, and (b) schematic illustration of carrier separation experiment.

n

⁺

n

⁺

n

⁺

Vg(-) _Hole

injection

Electron current Electron

injection (+)I

SD

(+)I

_B

P-Sub

inversion layer

h

⁺

I

_SD

(+)

e

-I

_SUB

(+)

I.L.

HfO

₂

n

⁺

-gate P-Sub

(a)

(b)

-7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7

Fig. 2.26 Gate leakage current versus gate bias for fresh

n-channel devices at various temperatures (a)

TEOS P.L. (b) FSG P.L..

Fig. 2.27 Conduction mechanism for source/drain current fitting under inversion region (a) TEOS (b) FSG P.L..

3950 4000 4050 4100 4150 4200 -22

3950 4000 4050 4100 4150 4200

-22

Fig. 2.28 Conduction mechanism for substrate current fitting under inversion region (a) TEOS (b) FSG P.L..

3900 3950 4000 4050 4100 4150 -26

3950 4000 4050 4100 4150 4200

-30

Fig. 2.29 Band diagrams for (a) TEOS and (b) FSG P.L., illustrating the conduction mechanism of Frenkel-Poole emission.

I.L.

HfO

₂

n

⁺

-gate P-Sub

TEOS P.L. k=21

Φ=1.07 for Electron trap

Φ=1.27 for Hole trap

I.L.

HfO

₂

n

⁺

-gate P-Sub

FSG P.L. k=23

Φ=1.12 for Electron trap

Φ=1.34 for Hole trap (a)

(b)

Fig. 2.30 Schematic energy band diagram of the gate-drain overlap region.

Fig. 2.31 The band diagrams before (solid line) and after (dashed line) capturing electrons by bulk traps.

E

^c

E

E

^c

E I

^BB

S

ⁱ

O

P-Substrate Si-Gate

E

Fig. 2.32 Gate-induced leakage current characteristics of I

D

-V

GS

transfer curves for all splits of NMOSFETs.

Fig. 2.33 In FSG P.L. devices, a large amount of F atoms incorporating to passivating the bulk and

interface trap charges of HfO2/SiON gate stack n-MOSFET.

-0.5 0.0 0.5

10

^-11

10

^-10

10

^-9

10

^-8

D ra in C u rr e n t [A ]

Gate Voltage [V]

FSG A FSG B FSG C TEOS

NMOSFET

L/W=0.3/10µm

V

DS

=3V

Table 2.2 Trend of electrical properties for HfO

2

/SiON gate stack n-MOSFET for all splits of different passivation layer.

[#/cm2] Critical Electrical

Parameters

CET V

Th

S.S. µ

^eff

^I

^on

^J

^g

N

it

I-V Hys.

3.83 1.235 101.3 276 371 -- 1.58x10 150 ¹¹ 3.79 1.241 95.5 282 404 ↓ 9.52x10 120 ¹⁰ 3.94 1.187 91.9 289 444 ↓ 8.58x10 100 ¹⁰ 4.21 1.334 91.5 296 480 ↓↓ 7.65x10 50 ¹⁰

Control FSG A FSG B FSG C

[nm] [ ]V [mV dec/ ][cm²/Vs] [µA] [mV]

CHAPTER 03

Reliability Issues of FSG Passivation on HfO ² Gate Dielectrics

3.1 Briefly Reliability Review

Reliability characteristics of the Hf-based dielectric such as time dependent dielectric breakdown (TDDB), bias temperature instability (BTI), and hot carrier induced degradation (HCI) have been actively investigated in connection with expected application of these materials in the high-k gate stack [1-5]. Threshold voltage (V_Th)

instability induced by charge trapping has bee recognized as one of the critical reliability issues in Hf-based high-k gate dielectrics, especially for the n-MOSFETs under substrate electron injection conditions (positive bias stress) and V_Th degradaion of n-MOSFET

PBTI was primarily caused by charge trapping in bulk high-k rather than interfacial degradation [6]. Since the threshold voltage is directly related to the n-MOSFET’s on-off characteristics and eventually determines its output power supply voltage for its own purpose. The results from several stress conditions using various voltages and temperatures enable us to evaluate the wear-out behavior of n-MOSFETs as well as the lifetime of devices.

Although one of main issues for high-k gate stack is the charge trapping characteristics during reliability test, a threshold voltage

instability associated with electron trapping/de-trapping in high-k layer [7-12] can significantly affect the transistor parameters and complicate the evaluation of the effects of stress-induced defect generation phenomenon on the high-k gate stacks, which typically is not an issue in the case of SiO2 dielectrics because the reversible electron trapping, which is less prevalent in SiO2, can significantly affect transistor parameters [13-14]. The electron de-trapping behavior in the high-k films has been described under specific gate bias conditions identifying charge trapping and relaxation mechanism, and we can also evaluate additional electron trapping effects on top of defect generation by a de-trapping step which has been proposed for studying generation of the electron trapping process and its impact on high-k device reliability [10-11]. As a result, in the Hf-based high-k gate dielectrics, these reversible charge trapping and de-trapping behaviors are highly related to the stress history of previously trapped charge carriers, implying these high-k traps are pre-existing bulk traps [15-16]. For further understanding as mentioned above, we will investigate trapping dynamics of carrier in HfO2 high-k dielectric n-MOSFETs.

Finally, hot carrier reliability may be one of the major limitations for the implementation of the high-k gate dielectrics. We should consider the concurrent charging of the gate dielectric by the cold channel carriers injected into the dielectric when investigating hot carrier effects on high-k gate dielectrics [17-19]. The cause comes

from which both hot carriers near the drain region of the channel and cold carriers (channel electrons) can be injected and trapped in the high-k layer during HCS. In this chapter, we investigate the characteristics of threshold voltage (V_Th) shift during CVS and HCS to

find a way to differentiate the contribution of cold carrier trapping and hot carrier injection.

3.2 Effects of Various P.L. on PBTI Characterization 3.2.1 Static and Dynamic Trapping Measurements Setup

To understand the positive bias temperature instability (PBTI), the generation of interface trapp charges (∆N_it) and high-k bulk trap charges (∆N_B) was extracted by the measured stress time-dependent

∆V_Th shifts and charge pumping current change. Fig. 3.1 (a) shows

the static PBTI framework of our measurements. The gate electrode of the device was subjected to stress condition with normalized positive bias 0.5V, 1.0V, and 1.5V, respectively, varying from 25 °C to 125 °C, while the source/drain and substrate were all grounded. We measure I_D −V_GS and charging pumping during stress intervals.

D − GS

I V measurements are used to evaluate time evolution of threshold voltage, swing, transconductance, and charging pumping measurements are used to obtain interface density generation for certain interval time was investigated and compared. The dependence of bulk trap density on stress time has been indicated in section 2.2.2.

To investigate the relaxation chararcteristics, we can observe charge detrapping phenomenon from Fig. 3-1 (b). After changing the negative stress applied for a various duration in the range of 1 ~ 1000 sec, the V_Th change is continuously monitored for 1000 sec.

3.2.2 Threshold Voltage ( V ) Instability

th

Firstly, we focus on reliability characteristics of HfO2/SiON gate stack n-MOSFETs with FSG P.L. compared to TEOS P.L. under constant DC stress condition. Fig. 3.2 and Fig. 3.3 compares the threshold voltage and I_{D lin,} variations as a function of stress time for the control

TEOS sample and three splits the novel of FSG n-MOSFETs, respectively. The given normalized stress was 1.0V at room temperature. In order to exclude the difference of in the threshold voltage between samples, normalized positive stress voltage of the gate terminal was used. Very noticeable difference among samples is that the FSG C P.L. shows a reduced V_Th degradation compared to the TEOS P.L, and this I_{D lin,} degradation behavior was found to be similar to V_Th degradation. The high-k bulk traps (N_B ) are an important

factor of stress-induced degradation. To prove this degradation, the normalized gate current density during Fowler-Nordheim (FN) stress at V_GS = 4 0. V is plotted versus stress time for all splits shown in Fig.

3-4. As observed, the normalized gate leakage current density decreases with stress time for both samples, whereas TEOS P.L.

shows a higher rate of J_g decrease than three splits of FSG P.L.

devices. This result indicates that there are more high-k defect traps in the high-k bulk of TEOS P.L., causing a higher number of electrons trapped than in that of FSG P.L..

To further gain insights into the degradation mechanism during voltage stressing, the interface state generation, ∆N_it , and the increase of the bulk trap density, ∆N_B , are shown in Fig. 3-5.

Apparently, ∆N_B is significantly larger than ∆N_it, suggesting that the

degradation under PBS is dominated by the charge trapping in the bulk of HfO2 film, rather than the generation of interface states, irrespectively of whether CF4 gas is introduced or not. Q_BD Weibull

distribution of all samples stressed at 5.9V constant voltage stress is shown in Fig. 3-6. Between three samples introduced various flow rate of CF4 gas, this bulk trap generation is correlated with the amount of the fluorine from CF4 flow, which especially FSG C sample showed much reduced N_B shift. And it can clearly be seen that FSG C sample exhibits significant higher Q_BD for positive bias stress but the

difference between TEOS sample and the others is small. Therefore, we regard FSG C P.L as the optimum FSG P.L. because the good correlation between trapping and breakdown results indicates that this improvement can be attributed to reduce electron trapping rate and weak bonds replacing by strong bonds in gate stack dielectric, and further we investigate also the effects of reliability between

optimum FSG P.L and TEOS P.L..

Fig. 3-7 shows the transconductance degradation ratio as a function of stress time. Basically the trends are similar to those shown in previous figure. The transconductance degradation ratio for TEOS P.L. depicts the severest degradation among all splits, reaching 28.6%

after 1000 sec at V_GS −V_Th =1 0. V . However, the transconductance

degradation is alleviated for optimum FSG P.L. device. The results clearly indicate that the use of TEOS passivation layer may aggravate PBS, while the FSG passivation layer can be helpful to mitigate the situation. Fig. 3-8 shows the time dependences of the threshold voltage degradation under various positive bias stress voltages at room temperature for optimum FSG and TEOS devices. This result indicates that quantity of electron trap sites was increased with gate bias. It is apparent that ∆V_Thobeys a power-law dependence on stress

time, as given by Equation (3-1) :

∆V_Th ∝ tⁿ (3-1)

where the exponent value n, which dependent relative to bulk trap generation, is found to be ~0.2 and ~0.5 at V_GS −V_Th = 0 5. V for

optimum FSG and TEOS n-MOSFETS, respectively. For optimum FSG device, the threshold voltage degradation by PBS stress is obviously lower than that for TEOS device under various stress voltages. As an effect of F incorporation, this indicates that pre-existing defects were reduced and stress induced defects which were generated in the

high-k film could be alleviated. As shown Fig. 3-9, compared with TEOS sample, FSG sample indeed suppressed the generation of both

∆N_it and ∆N_B , especially ∆N_B . The improvement may be due to

fluorine atoms from CF4 gas, similar to nitrogen atoms, form complexes at the interface and dielectric, which reduce the total number of available Si-H bonds, and passivate the bulk trap, leading to less PBS degradation.

It can be seen that I_D −V_GS curves shift toward more positive

voltage at 125 °C compared to room temperature for both the FSG and TEOS P.L. devices, as shown in Fig. 3-10 (a) and (b), respectively.

Further, V_Th shift of the TEOS sample is clearly larger. Fig. 3-11 shows the V_Th shift as a function of stress time at temperatures ranging from 25 °C to 125 °C. The V_Th shift induced by charge trapping

increased exponentially with temperature. This stress induced defect generation could be observed with temperature acceleration. Since PBTI was thermally active, electron trap site generation was also accelerated by heating. Fig. 3-12 shows ∆N_it and ∆N_B as a function

of time during PBTI for both devices measured at different temperatures. It can be seen that optimum CF4-introduced device always show smaller both ∆N_it and ∆N_B than the TEOS device at all

temperatures. To compare with positive bias stress at 25 °C in Fig. 3-8, PBTI-induced threshold voltage degradation, ∆N_it and ∆N_B as a function of stress time under various positive bias stress voltages at

100 °C for optimum FSG and TEOS n-MOSFETs are show in Fig. 3-13 and Fig. 3-14. The threshold voltage and charge trapping of bulk and interface degradation for both samples are similar to PBS at 25 °C, indicating the power-law dependence and the optimum FSG P.L.

immunity to PBTI that is higher than the TEOS P.L. immunity under various stress overdrive voltages in the range from 0.5 to 1.5V. Fig.

3-15 compares the PBT-stress-time dependence of threshold voltage shift for HfO2/SiON gate stack with optimum FSG P.L. and with TEOS P.L.. A significantly smaller V_Th shift is observed for the optimum FSG sample under the BT stress, V_GS −V_Th =0.5Vat 25 °C and 125 °C. The

exponential values of both samples at 125°C are 0.4 for TEOS sample and 0.2 for FSG sample but 0.5 for TEOS sample and 0.2 for FSG sample at 25 °C. Fig. 3-16 show ∆N_it and ∆N_B as a function of stress

time during PBTI both devices measured at 25 °C and 100 °C. It is found that for both devices, V_Th degradation during PBTI stressing is

primarily caused by the charge trapping in bulk HfO2, rather than the interfacial degradation. Note that the activation energy of ∆V_Thin PBTI

degradation for FSG P.L. is larger than for TEOS P.L. as shown in Fig.

3-17. This indicates that, thermally induced defects were increased as an effect of F incorporation. In addition, the activation energy of ∆V_Th is lower than that of ∆N_it, indicating that V_Th instability is not simply contributed by interface tarp generation, but mainly comes from the more significant charge trapping in the bulk of high-k dielectric as

shown in Fig. 3-18. All results are consistent with the effectiveness of fluorine incorporation from CF4 gas in alleviating the PBT instability.

3.2.3 The Characteristics of Charge De-trapping

The threshold voltage was shifted to positive direction due to negative charges built up within the HfO² shown in Fig. 3-10. Parallel shift of I_D −V_GS curve indicates that the interface qualities are not

degraded significantly despite of significant electron charging.

Interestingly, after relaxation voltage V_g = −2V, a rapid turn around of

VTh shift was observed in Fig. 3-19. Therefore, we can conclude that the electron trapping/de-trapping occurs on the pre-existing (“as-grown”) defects due to no noticeable degradations of the interface electrical property. As shown in Fig. 3-20 shows the threshold voltage shift of the HfO2/SiON high-k gate stack n-MOSFETs for optimum FSG P.L. and TEOS P.L. samples as a function of the static stress/relaxation time with a fixed stress voltage V_GS −V_Th =1.5V and relaxation voltage V_GS = −2V . Basically, the relaxation voltage plays a

significant role to clean up the trapped charge carriers before the next stress cycle. It was also indicated that an charge de-trapping behavior can not cause an additional V_Th instability because the threshold voltage was still shifted above the initial V_Th for both samples. After relaxation, a subsequent stress-induced V_Th increase follows the initial pre-relaxation stress time dependence. It is clear that this

relaxation does not fully recover the V_Th shift caused by the positive bias stress. The residual V_Th shift appears to be determined by the

balance between the built-in potential due to trapped charges and the barrier height for de-trapping [20].

Based on the observations above, a model explaining V_Th

instability behavior during the stress and relaxation can be proposed as shown in Fig. 3-21. The signs of A and B in Fig. 3-22 are defined by de-trapping ratio and residual-trapping ratio, respectively. There are two factors to shift V_Th during the stress. One is electrons filling the

existing traps and the other is the charged damages created during the stress. Portion of the former electrons was de-trapped spontaneously to reduce the instant built-in potential after the stress was removed. However still there are some amount of trapped electrons and charged damage remaining. We can observe that a lot of trapped electron is significant to be instantly pulled out from the pre-existing traps and the created traps are also obviously decreased for the TEOS sample during de-trapping bias, resulting in a few of the residual electrons ( “B_T part in Fig. 3-20” ) and a number of reversible electrons ( “A_T part in Fig. 3-20” ), as shown in Fig. 3-21 (a). However,

a little of trapped electron is de-trapped from the pre-existing traps even if the created traps was effective to decrease for the optimum FSG sample shown in Fig. 3-21 (b), which B_F > B_T in the residual charges characteristic and A_F < A_T in charge de-trapping

characteristic. It indicates that some of deep traps filled or created due to fluorine effect resulting in trapped electrons suffering from the higher barrier height of detrapping behavior during relaxation cycle for the optimum FSG P.L.. As mentioned previous, it was associated with the good correlation of the barrier height between de-trapping behavior and F-P emission results for both samples. The other possible explanation for this phenomenon is larger CET for the optimum FSG P.L than the TEOS P.L.. This CET layer could be source for charge storage, resulting in storing significant amount of trapping in addition to the existing trap for the optimum FSG P.L. shown in Fig.

3-22. The A_T (or A_F) represents charge trapping related defect level

which causing threshold voltage shift, so we can understand defect generation of HfO2/SiON gate dielectric with the optimum FSG P.L. is much less than the TEOS P.L. in operation mode.

which causing threshold voltage shift, so we can understand defect generation of HfO2/SiON gate dielectric with the optimum FSG P.L. is much less than the TEOS P.L. in operation mode.

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