Basic Device Characteristics

The C-V curves (100 KHz) of FSG A, B, C, and control samples are show in Fig. 2-6. The capacitance of the sample with CF4 gas introduced decreases compared to that of the as-deposited sample, which no obvious difference in C-V curves in substance. When CF4 gas flow rate is lower than 20 sccm, it indicates a slight increase of CET in FSG A and FSG B. However, the introduced CF4 gas is much more than the allowable F concentration, residual damage for the CET after sintering step can be observed. The resultant CET increment faster may be an excess amount of F incorporation into high-k film stacks [12-13] or the absorption of moisture from the atmosphere in the

plasma-deposited FSG film is the principle root-cause, which many studies indicated that the phenomenon of moisture (H2O) absorption in the plasma-deposited FSG film has been observed because the Si–F bonds present are highly reactive with moisture [14-15]. Fig. 2-7 was investigated with respect to CET and flat-band voltage (V_FB , not shown) [16] for the samples. We can see the fact that the V_FB has

shifted to positive direction as the CF4 flow rate increases and EOT is also affected by the presence of F atoms. This is point out that decrease of positively charged traps or increase of negatively charged traps [17-19].

Fig. 2-8 shows the gate leakage current of n-MOSFET with HfO2/SiON gate stack under both inversion and accumulation modes.

It can obviously noted that with FSG passivation layer, the leakage current is significantly suppressed for both polarities. Specially, the reduction under normal operation condition, i.e., inversion mode, is around 40% of magnitude lower. One of the reasons for the exhibited gate leakage current reduction may be a thicker CET for two splits of fluorinated devices. Hence, it extrapolates that the CF4 gas flow rate even up to 30 sccm doesn’t deteriorate gate leakage current, and on the contrary, the reduction extent of gate leakage current is dependent on the flow rate of CF4 gas introduced into FSG passivation from measurement data of Weibull distributions shown in Fig. 2-9. Fig.

2-10 demonstrates the transconductance (Gm) as a function of gate voltage for both gate dielectrics. The Gm is normalized by CET

(Capacitance Equivalent Thickness), which is 37.9Å, 39.4Å, 42.1Å, and 38.3Å for FSG A, B, C, and control sample, respectively. The peak transconductance is 28%, 42%, and 67% for FSG passivation with respect to TEOS passivation. Fig. 2-11 shows the improved normalized linear drain–current I_D which FSG P.L. is 24% higher

above than TEOS P.L. and the inset of subthreshold slope (S.S.) reduced 9.6% for the CF4 introduced samples, indicating that fluorinated CMOS HfO2 has better interface characterization. Previous study [20] on Zr-silicate indicates that electron transport in the channel can be degraded by the coulomb scattering of negative charges in the bulk film, and Fischetti et. al [21] also points out that electron mobility in the inversion layer is affected by remote phonon scattering due to ionic polarization in high-k films. Therefore, the peak transconductance degradation in HfO2/SiON stack is probably due to charges or traps in the bulk film, as evidenced by the positive shift in C-V curve in Fig. 2-6, even if the interface-state densities are kept to be small. Besides, as shown Fig. 2-12, the V_Th distribution is less affected by the addition of F for FSG A and B wihile a increased V_Th can be observed for FSG C, which also corresponding with the V_FB

trend (not shown) due to negatively charged traps.

Fig. 2-13 presents the excellent output drive current characteristics ( I_D −V_DS ) under various normalized gate biases (V_GS −V_Th), which almost 12% enhancement in magnitude of I_{D Sat,}

for FSG P.L. with respect to TEOS P.L.. The gate voltage has been normalized with respect to threshold voltage to minimize the effect of threshold voltage. We also understand that normalized I_{D Sat,} and

transconductance max peak depends on the flow rate of CF4 gas or the amount of fluorine incorporated from Fig. 2-14. The improvements are believed to be intimately related not only to the better interface quality but also to the reduced bulk trap density. To quantify the interface state density by the CP current measurement, which the CP peak height is approximately proportional to the interface state density (N_it) along the channel, Fig. 2-15 can be seen that the trend

is quite consistent with that in subthreshold swing, as shown in inset of Fig. 2-11. Channel mobility is dependant on the nature of gate dielectric between Si substrate and high-k gate dielectric.

CF4-introduced high-k gate dielectrics suffer from CET increased whereas mobility can be enhanced shown in Fig. 2-16. The peak mobility for FSG C device is 7% higher than the control, and the high field mobility at 0.8MV/cm is 49% higher than the control, which is correlated with the higher Gm,max (see inset of Fig. 2-16) and higher output current characteristics. The electron mobility at 0.8MV/cm for the fluorinated device is 68% of SiO2 universal curve. Clearly, as the amount of introduced CF4 gas become elevated, peak mobility increasing with decreasing interface state density implying the weak and dangling bonds, associated with interface and trap states, are passivated and released strain bonds by fluorine atoms, leading to the

enhanced electrical characteristics show in Fig. 2-17.

Fig 2-18 indicates the subthreshold swing of devices with different passivation layers as a function of channel length. And we find that subthreshold swing for FSG P.L. shows the better interface states than TEOS P.L.. Thus, the FSG P.L. will improve the subthreshold swing in device. The relation between drain current and channel length for all splits of HfO2/SiON gate stack n-MOSFET is shown in Fig. 2-19 and Gm

is in Fig. 2-20. When channel length becomes shorter, the improvement is more obvious. Fig 2-21 shows the V_Th -roll-off

characteristics with different passivation layers. When channel length is less than 1µm, V_Th-roll-off phenomenon is more serious for TEOS

P.L. while the FSG devices effectively suppress this behaviour to the same extend with increasing the amount of CF4 gas flow. In short, it was found that all fundamental electrical properties, including the CET, flat-band voltage, threshold voltage, drive current, interface state density (N_it), swing, mobility, gate leakage current, and short channel

effect are almost non-degradation instead of surprise enhancement for device performance between the four splits with FSG and TEOS P.L..