Chapter 03 Reliability Issues of FSG Passivation on HfO 2
3.3 Reliability Impact of Various P.L. on HCS
3.3.2 Cold and Hot Carrier Charge Trapping Effects.…
Substrate current is an important factor to determine how much hot carriers are generated and injected during hot carrier stress. A hot carrier with sufficient energy can create more charge carriers through impact ionization. For n-MOSFET devices, holes generated by impact ionization are collected by the substrate. The substrate current (ISUB) versus gate voltage for both samples of devices at VDS of 2.5V is
illustrated in Fig. 3-23. From the figure, we can clearly see the TEOS P.L. exhibits larger substrate current than the the optimum FSG P.L. in our devices. Such phenomenon is closely related to the incorporation of fluorine atoms forming stronger Si–F bonds near the source and drain sides instead of weaker Si–H and Si–Si bonds to enhance the interface hardness between HfO2/SiON and silicon as well as the immunity against hot-carrier stress due to the inhibition of the
channel avalanche multiplication of hot carriers. Hot-carrier effects and associated performance degradation were investigated to evaluate the impacts of various passivation layer such as optimum FSG and TEOS dielectrics. Thus, we easily try two conditions
= ,
G SUB Max
V I and VGS =VDS to obtain the most serious degradation.
Threshold voltage shift and captured traps density (including interface traps and bulk traps) increase as a function of stress time for both samples are shown in Figs. 3-24 and 3.25, respectively, after receiving a hot-carrier stressing at VDS = 2.5 V and VGS at the
maximum value of substrate current. The larger degradation which happens at VGS =VDS and also get similar case in many papers [21].
Most of high-k material devices which HCS induces aggravated degradation occur in VGS =VDS. This tells us that the degradation is
caused mainly by the stress magnitude applied by gate voltage. Not to determinate by maximum substrate current. Therefore, we attain larger threshold voltage shift and huge captured traps variations with
GS = DS
V V condition.
Typical results of hot-carrier stressing for the optimum FSG P.L.
and TEOS P.L. devices are shown in Figs. 3.26 and 3.27, respectively, which are stressed at VDS = 2.5 V and VGS at maximum value of
substrate current. It is expected that the TEOS P.L. will exhibit aggravated hot carrier degradation as mentioned previous, while the improvement of the hot-carrier degradation by using the FSG P.L. is
obviously seen. Since the hot carriers tend to break the Si-H bonds during the stressing, and much severe degradation will occur with the TEOS P.L. sample. The use of the optimum FSG P.L. can effectively suppress interface damage near the drain side due to the stronger Si-F bonds formation which are less easily broken than Si–Si and Si–H bonds under hot-carrier stress, therefore, and less HCS degradation in terms of threshold voltage shift, interface states, and bulk traps generation is achieved. Consequently, the aggravation is alleviated in the devices with optimum FSG passivation layer.
Besides, Fig 3-28 and 3-29 show the comparison HCS with PBS. In hot-carrier stressing at VGS =VDS , we observe that not only larger
interface state and bulk trap density shift but also more serious threshold instability represent with PBS. However, HCS when VGS at
the maximum value of substrate current has the least interface state degradation of the others conditions, indicating the interface state degradation increases with the gate voltage. This phenomenon was observed with the formation of hot electrons resulting in much more electrons trapping in bulk traps despite ISUB Max, being indication of
less electron trap in high-k bulk.
Finally, total threshold voltage shift during a hot carrier stress is a sum of contributions from both hot carrier and cold carrier effects.
Cold carrier contribution is shown to be reversible and, therefore, it does not introduce permanent damage. The contribution from the cold carrier can be evaluated by applying a de-trapping (opposite
polarity) bias after the stress. On the other hand, since the hot carrier damage is permanent, it cannot be reverse by application of a voltage, which polarity is opposite to the one of the stress – parameter shift keeps growing with each additional stress cycle. Thus, at the same gate bias, HCS appears to induce a larger positive ∆VTh shift than PBS
shown in Fig. 3-30 and 3-31 for the TEOS and optimum FSG samples, respectively, pointing to the contribution from the hot electrons. From Fig. 3-30 and 3-31, cold carrier induced threshold voltage shift is repeatable during PBS and HCS, and a residual HCS VThshift increases
with every cycle, indicating an increase in HCS-induced degradation.
After the de-trapping cycle, amount of recovery induced by cold carrier are similar during HCS and PBS. Since total threshold voltage shift is the combination of both cold and hot carrier contribution, threshold voltage shift is greater in TEOS device than FSG device, partly due to more electron charge trapping effects, which indicates that most of the VTh shift was related to the transient charge trapping
within the bulk of high-k dielectrics [20,22]. Based on –2V de-trapping process, FSG device shows more residual threshold voltage shift than TEOS device, indicating FSG device has less cold carrier effects or a lower relaxation ratio but induces more hot carrier induced damage during HCS.
3.4 Summary
In this chapter, a novel CMOS compatible fluorine incorporation
into high-k technology and reliability characteristics has been successfully demonstrated. We observe that serious degradation such as interface state, bulk trap density and threshold voltage shift occurs in the TEOS P.L. sample. The CF4-introduced silicon oxide as a FSG passivation layer showed improved reliability characteristics under the PBTI and HCS. It is believed that the HCS and PBTI degradation are related to the electron traps in gate dielectrics. PBTI was found to be mainly caused by bulk trapped generation rather than the generation of interface trapped charge. The worst-case degradation of HCS occurs at VGS =VDS stress condition. The hot carrier contribution
induces permanent damage while cold carrier contribution is shown to be reversible. Fig.3-32 shows that the longer time-to-breakdown (TBD)
for the FSG P.L. sample is primarily attributed to its less electron trapping to the dielectric and thus contributes to a longer dielectric lifetime. Fig. 3-33 shows the dependence of lifetime (using the E-model) from PBTI on n-MOSFETs with both samples at 25 °C and 100 °C. The PBTI lifetime (degradation criterion: 30mV VTh shift)
improvement for device with the FSG P.L., as compared to the TEOS P.L.. The FSG P.L. sample leading to the formation of stronger Hf-F and Si-F bonds compared to Hf-H and Si-H bonds reduced charge trap generation rate. These stronger bonds result in less interface states generation and charge trapping under PBTI and HCS, which promotes better hot-carrier and PBTI immunity against stress, as shown in Fig.
3-34.
3.5 References
P. Tsui and G. Bersuker: Device Research Conference (2004) p. 99.[6] K. Onishi, Rino Choi, Chang Seok Kang, Hag-Ju Cho, Young Hee Kim, R. E. Nieh, Jeong Han, S. A. Krishnan, M. S. Akbar, J. C. Lee,
“Bias-temperature instabilities of polysilicon gate HfO2 MOSFETs,”
IEEE Transactions on Electron Devices, vol. 50 (6) pp.1517-1524, 2003
[7] E. P. Gusev and C. P. D’Emic: Appl. Phys. Lett. 83 (2003) 5223.
[8] S. Zafar, A. Callegari, E. Gusev and M. V. Fischetti: J. Appl. Phys.
93 (2003) 9298.
[9] R. Choi, B. H. Lee, G. Brown, P. Zeitzoff , J. H. Sim and J. C. Lee:
International Symposium on the Physical and Failure Analysis of Intergradted Circuits (2004) p. 21.
[10] R. Choi, B. H. Lee, K. Matthews, J. H. Sim, G. Bersuker, L. Larson and Jack C. Lee: Device Research Conference (2004) p. 31.
[11] F. Crupi, R. Degraeve, A. kerber, D. H. Kwak and G. Groeseneken:
Proceedings of IRPS (2004) p. 181.
[12] G. Bersuker G. Bersuker, J. Gutt, N. Chaudhary, N. Moumen, B.H.
Lee, J. Barnett, S. Gopalan, J. Peterson, H.-J. Li, P.M. Zeitzoff, G.A. Brown, Y. Kim, C. D. Young, J. H. Sim, P. Lysaght, M. Gardner, R. W. Murto and H. R. Huff: Proceedings of IRPS (2004) p. 479.
[13] D. J. DiMaria, E. Cartier, and D. A. Buchanan, “Anode hole injection and trapping in silicon dioxide,” J. Appl. Phys., vol. 80, p. 304, 1996. M. V. Fischetti, “Model for the generation of positive charge at the Si-SiO interface based on hot-hole injection from the anode,” Phys. Rev. B, vol. 31, p. 2099, 1985.
[14] Q. Lu, H. Takeuchi, R. Lin, T. J. King, C. Hu, K. Onishi, R. Choi, C.
S. Kang, and J. C. Lee, “Hot carrier reliability of n-MOSFET with ultrathin HfO gate dielectric and poly-Si gate,” in Proc. Int.
Reliability Physics Symp., 2002, p. 429.
[15] G. Ribes, S. Bruyere, D. Roy, M. Muller, M. Denais, V. Huard, T.
Skotnicki, G. Ghibaudo, Trapping and detrapping mechanism in hafnium based dielectrics characterized by pulse gate voltage techniques, IEEE-IRW, p. 125, 2004.
[16] R. Choi, S.J. Rhee, J.C. Lee, B.H. Lee, and G. Bersuker, “Charge Trapping and Detrapping Characteristics in Hafnium Silicate Gate Stack Under Static and Dynamic Stress,” IEEE Electron Device Lett., vol. 26, no. 3, p. 197-199, 2005.
[17] M. Takayanagi, T.Watanabe, R. Iijima, K. Ishimaru, and Y.
Tsunashima, “Investigation of hot carrier effects in n-MISFETs with HfSiON gate dielectric,” in Proc. Int. Reliability Physics Symp., 2004, p. 13.
[18] B. H. Lee, J. H. Sim, G. Bersuker, K. Matthew, N. Moumen, J.
Peterson, and L. Larson, “Localized transient charging and its implication on the hot carrier reliability of HfSiON MOSFETs,” in Proc. Int. Reliability Physics Symp., 2004, p. 691.
[19] Hirano, T. Yamaguchi, K. Sekine, M. Takayanagi, K. Eguchi, Y.
Sunashima, and H. Satake, “Significant role of cold carriers for dielectric breakdown in HfSiON,” in Tech. Dig. Symp. VLSI Technology, 2004, p. 142.
[20] Rino Choi, Byoung Hun Lee, K. Matthews, J. H. Sim, G. Bersuker, L. Larson and Jack C. Lee, “Relaxation of FN stress induced Vth shift at NMOSFETs with HfSiON Gate Dielectric and TiN Gate Electrode,” the 62nd DRC, submitted.
[21] Jong Pyo Kim, Yun-Seok Kim, Ha Jin Lim, Jung Hyoung Lee,Seok Joo Doh,Hyung-Suk Jung, Sung-Kee Han, Min-Joo Kim, Jong-Ho Lee, Nae-In Lee, Ho-Kyu Kang, Kwang-Pyuk Suh, Young-Su Chungt, “HCI and BTI Characteristics of ALD HfSiO(N) Gate Dielectrics as the Compositions and Post Treatment Conditions”, in IEDM, 2004
[22] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks,” J. Appl. Phys., vol. 93, no. 11, pp. 9298–9303, Jun. 2003.
[23] W.-C. Wu, C.-S. Lai, S.-C. Lee, M.-W. Ma, T.-S. Chao, J.-C. Wang, C.-W. Hsu, P.-C. Chou, J.-H. Chen, K.-H. Kao, W.-C. Lo, T.-Y. Lu, L.-L. Tay, N. Rowell, “Fluorinated HfO2 Gate Dielectrics
Engineering for CMOS by Pre- and Post-CF4 Plasma Passivation”
Fig. 3.1 Schematic of measurement setup for (a) static PBTS (b) dynamic trapping.
n+
n+ n+
P G
ID-VG
& CP
DC stress
10sec
…..
Charge pumping:
To evaluate △△△△Nit
ID-VG:
To evaluate △△△△Gm
ID-VG
& CP ID-VG
& CP ID-VG
& CP
DC stress 5sec DC stress
1sec
PBS for gate electrode
PBS(Normalized)=0.5V, 1.0V, 1.5V
Change Temp.
25°°°°C ~ 125°°°°C
(a)
(b)
Fig. 3.2 PBT-stress-time dependence of ∆V
thfor TEOS and FSG having different flow rate of CF
4gas at 25°C.
Fig. 3.3 PBT-stress-time dependence of ∆V
thfor TEOS and FSG having different flow rate of CF
4gas at 25°C.
NMOSFET
Fig. 3.4 The normalized gate current density ((J
g-J
g0)/J
g0) at a constant gate voltage of 4.0V versus stress time of all splits.
Fig. 3.5 Separation of total capatured trap density into ∆N
itand ∆N
Bcomponent for all splits after 1000s PBT stress.
0 200 400 600 800 1000 -25
-20 -15 -10 -5 0
( J g -J g 0 ) /J g 0 [ % ]
Stress Time [sec]
TEOS FSG A FSG B FSG C
TEOS FSG A FSG B FSG C 10
1010
1110
12∆ N it o r ∆ N B [ c m -2 ] N
BN
itNMOSFET T=25°C
L/W=0.4/10µm
V
GS-V
Th=1.0V, 1000sec
NMOSFET T=25°C
L/W=0.4/10µm
SILC @ V
GS=4.0V
Fig. 3.6 Weibull plot of charge-to-breakdown for all samples under a constant voltage stress of 5.9V.
Fig. 3.7 Transconductance degradation versus stress time for both samples with V
GS-V
Th=1.0V at 25°C.
Charge-to-Breakdown [ C/cm 2 ]
TEOS
Fig. 3.8 Time dependences of PBS-induced V
thdegradation at various normalized stress biases from 0.5 to 1.0 per steps of 0.5V at 25°C.
Fig. 3.9 Time dependences of PBS-induced N
itand N
Bdegradation at various normalized stress biases
from 0.5 to 1.0 per steps of 0.5V at 25°C.
Fig. 3.10 I
D-V
GScharacteristics for HfO
2/SiON n-MOSFETs
before stress and after stress 1000s at 125°C (a)
TEOS P.L. (b) FSG P.L. sample.
1 10 100 1000
Fig. 3.11 Threshold voltage shift as a function of stress time under +1.0V normalized gate bias voltage at
various temperatures.
Fig. 3.12 Interface trap density and bulk trap density shift as a function of stress time under BTS at different stress temperature, V
GS-V
Th=1.0V.
FSG TEOS
Fig. 3.13 Time dependences of PBS-induced V
thdegradation at various normalized stress biases from 0.5 to 1.0 per steps of 0.5V at 100°C.
Fig. 3.14 Time dependences of PBS-induced N
itand N
Bdegradation at various normalized stress biases
from 0.5 to 1.0 per steps of 0.5V at 100°C.
Fig. 3.15 Threshold voltage shift as a function of stress time under BTS a different stress temperature,
V
GS-V
Th=0.5V for FSG and TEOS samples.
Fig. 3.16 Interface trap density and bulk trap density shift
as a function of stress time under BTS a different
stress temperature, V
GS-V
Th=0.5V for FSG and
Fig. 3.17 Temperature dependence of threshold voltage shift. PBT stress was applied under V
GS-V
Th=0.5V.
Fig. 3.18 Temperature dependence of interface traps
shift. PBT stress was applied under V
GS-V
Th=0.5V.
Fig. 3.19 I
D-V
GScharacteristic during a constant voltage
Apply stress (Vg=3V) 1 sec
600 sec
Relax stress (Vg=-2V) 1 sec
Fig. 3.21 Schematic explanation of stress and relaxation process with different bias conditions for (a) TEOS (b) FSG P.L..
Fig. 3.22 Schematic explanation of more charge trapping stored in thicker CET during stress cycle.
: Pre-existing traps : Created traps : Electrons
(a)
(b)
Before Stress Stress Relaxation
FSG
TEOS
Stress Cycle
Fig. 3.23 Substrate current versus gate voltage for both samples of HfO
2/SiON gate stack n-MOSFETs.
Fig. 3.24 Threshold voltage shift as a function of stress time with HCS which compares FSG P.L. with TEOS P.L..
1 10 100 1000
10
010
110
2Stress Time [sec]
∆ V T h [ m V ]
FSG TEOS
0.0 0.5 1.0 1.5 2.0 2.5
0.00 0.05 0.10 0.15 0.20 0.25
S u b s tr a te C u re n t [ µ A ]
Gate Voltage [V]
FSG TEOS
n-MOSFET
I
SUB@ V
DS=2.5V L/W=0.4/10µm
ISUB,Max
VGS=VDS
HCS @ T=25°C
L/W=0.4/10µm
Fig. 3.25 Interface trap and bulk trap density shift as a function of stress time with HCS which compares FSG P.L. with TEOS P.L..
Fig. 3.26 I
D-V
GScharacteristics and transconductance of
devices with FSG P.L. before and after 1000 sec
Fig. 3.27 I
D-V
GScharacteristics and transconductance of devices with TEOS P.L. before and after 1000 sec
hot-electron stressing.
Fig. 3.28 Threshold voltage shift as a function of stress
time which compares HCS with PBS.
Fig. 3.29 Interface trap and bulk trap density shift as a function of stress time which compares HCS with
PBS.
Fig. 3.30 Threshold voltage changes during HCS and PBS
followed by a detrapping step (Vg=-2V) 600 sec
Fig. 3.31 Threshold voltage changes during HCS and PBS followed by a detrapping step (Vg=-2V) 600 sec for the FSG sample.
Fig. 3.32 Comparison of T
BDlifetime projection as a function
V
GSof FSG P.L. larger than TEOS P.L..
Fig. 3.33 Dependence of lifetime on stress V
GSfor both samples.
Fig. 3.34 Schematic of reliability improvement for the FSG passivation layer due to fluorine incorporation.
1.5 2.0 2.5 3.0 3.5
10
010
110
210
310
410
510
6FSG TEOS
L if e ti m e [ s e c ]
V GS [V]
NMOSFET
L/W=0.4/10µm
25°C 100°C
ΔV
Th=30mV
CHAPTER 04
Conclusions and Suggested Future Works
4.1 Conclusions
In this thesis, a novel fluorine passivation technique for HfO2/SiON gate stack n-MOSFET is proposed. The impact of fluorine incorporation into HfO2/SiON gate stack by introducing CF4 gas during depositing silicon oxide as a passivation layer was investigated.
Several important phenomena were observed and summarized as follows:
First of all, we have investigated its basic electrical properties. The novel high-k device with FSG film as the passivation layer to enhance the electrical characteristics due to fluorine passivation effect. We have found that improvements include many aspects, such as reduced gate leakage current, better subthreshold swing, enhanced normalized transconductance and driving current which correspond with higher mobility. This is attributed to the reduction of the interface state and bulk trap density in HfO2/SiON gate stack as confirmed by charge pumping measurements.The gate leakage current is analyzed by the carrier separation measurement, and can be explained by the band structure of the gate stack. The S/D current ISD that corresponds to the electron current dominates the leakage under inversion region, while the substrate current ISUB that indicates the hole current
dominants the leakage current under accumulation region. All leakage current can be categorized by fitting to be of Frenkel-Poole type.
In the second part of the thesis, we have studied the PBTI, HCS and charge de-trapping mechanisms of poly-si gate HfO2/SiON dielectric for various passivation layer. It is believed that the PBTI and HCS degradation are related to the electron traps in high-k dielectric, not by the interfacial degradation, resulting in threshold voltage shift.
The FSG passivation layer also promotes the PBTI and HCS immunity due to the formation of the rather stronger Si-F bonds in not only the HfO2 bulk but also the interface including near S/D sides. The results reveal that fluorine incorporation from the introduced CF4 gas is effective in suppressing ∆NB , thus improving threshold voltage instability. Stress induced VTh shift and its relaxation characteristics
under the de-trapping (negative) gate bias has been studied. The reversible electrons trapping do not generate structural damage in the dielectrics, and can be de-trapped. However, the residual electrons trapping indicate permanent damage.
Finally, we can observe that, for the FSG P.L., hot carrier induced permanent damage is significant severer than reversible cold carrier trapping. The root-cause possibly associated with the higher height barrier of de-trapping behavior and the slighter increased capacitance equivalent thickness.
4.2 Suggestions for Future Works
There are many issues that we can’t discuss completely. We list some goals for future work as follows.
1. HRTEM is used to verify real thickness and estimate value of the dielectric constant for HfO2/SiON gate stack.
2. SIMS analysis is used to prove fluorine exist in HfO2/SiON dielectric, further in order to understand fluorine depth profile.
3. XPS analysis is used to prove if fluorine can passivate oxygen vacancy so as to lower high-k bulk traps due to the formation of Hf-F bonds.
4. In actual CMOS circuit operation, AC gate bias with specific frequency and duty cycle is usually utilized. Therefore, AC stress with dynamic AC stress application is more realistic and can provide additional insights into the trapping behavior.
5. Fast transient pulsed ID-VGS measurement is also used to evaluate charge-trapping phenomena precisely.
6. The fluorinated silicate glass as a passivation layer of strained silicon device is investigated whether channel mobility and the improvement of reliability can be effectively enhanced or not.
7. How much flow rate of CF4 gas makes the FSG passivation layer unstable due to excess fluorine atoms, which in turn deteriorate the devices and result in the degraded performance and reliability.