Effects of Various P.L. on PBTI Characterization

To understand the positive bias temperature instability (PBTI), the generation of interface trapp charges (∆N_it) and high-k bulk trap charges (∆N_B) was extracted by the measured stress time-dependent

∆V_Th shifts and charge pumping current change. Fig. 3.1 (a) shows

the static PBTI framework of our measurements. The gate electrode of the device was subjected to stress condition with normalized positive bias 0.5V, 1.0V, and 1.5V, respectively, varying from 25 °C to 125 °C, while the source/drain and substrate were all grounded. We measure I_D −V_GS and charging pumping during stress intervals.

D − GS

I V measurements are used to evaluate time evolution of threshold voltage, swing, transconductance, and charging pumping measurements are used to obtain interface density generation for certain interval time was investigated and compared. The dependence of bulk trap density on stress time has been indicated in section 2.2.2.

To investigate the relaxation chararcteristics, we can observe charge detrapping phenomenon from Fig. 3-1 (b). After changing the negative stress applied for a various duration in the range of 1 ~ 1000 sec, the V_Th change is continuously monitored for 1000 sec.

3.2.2 Threshold Voltage ( V ) Instability

Firstly, we focus on reliability characteristics of HfO2/SiON gate stack n-MOSFETs with FSG P.L. compared to TEOS P.L. under constant DC stress condition. Fig. 3.2 and Fig. 3.3 compares the threshold voltage and I_{D lin,} variations as a function of stress time for the control

TEOS sample and three splits the novel of FSG n-MOSFETs, respectively. The given normalized stress was 1.0V at room temperature. In order to exclude the difference of in the threshold voltage between samples, normalized positive stress voltage of the gate terminal was used. Very noticeable difference among samples is that the FSG C P.L. shows a reduced V_Th degradation compared to the TEOS P.L, and this I_{D lin,} degradation behavior was found to be similar to V_Th degradation. The high-k bulk traps (N_B ) are an important

factor of stress-induced degradation. To prove this degradation, the normalized gate current density during Fowler-Nordheim (FN) stress at V_GS = 4 0. V is plotted versus stress time for all splits shown in Fig.

3-4. As observed, the normalized gate leakage current density decreases with stress time for both samples, whereas TEOS P.L.

shows a higher rate of J_g decrease than three splits of FSG P.L.

devices. This result indicates that there are more high-k defect traps in the high-k bulk of TEOS P.L., causing a higher number of electrons trapped than in that of FSG P.L..

To further gain insights into the degradation mechanism during voltage stressing, the interface state generation, ∆N_it , and the increase of the bulk trap density, ∆N_B , are shown in Fig. 3-5.

Apparently, ∆N_B is significantly larger than ∆N_it, suggesting that the

degradation under PBS is dominated by the charge trapping in the bulk of HfO2 film, rather than the generation of interface states, irrespectively of whether CF4 gas is introduced or not. Q_BD Weibull

distribution of all samples stressed at 5.9V constant voltage stress is shown in Fig. 3-6. Between three samples introduced various flow rate of CF4 gas, this bulk trap generation is correlated with the amount of the fluorine from CF4 flow, which especially FSG C sample showed much reduced N_B shift. And it can clearly be seen that FSG C sample exhibits significant higher Q_BD for positive bias stress but the

difference between TEOS sample and the others is small. Therefore, we regard FSG C P.L as the optimum FSG P.L. because the good correlation between trapping and breakdown results indicates that this improvement can be attributed to reduce electron trapping rate and weak bonds replacing by strong bonds in gate stack dielectric, and further we investigate also the effects of reliability between

optimum FSG P.L and TEOS P.L..

Fig. 3-7 shows the transconductance degradation ratio as a function of stress time. Basically the trends are similar to those shown in previous figure. The transconductance degradation ratio for TEOS P.L. depicts the severest degradation among all splits, reaching 28.6%

after 1000 sec at V_GS −V_Th =1 0. V . However, the transconductance

degradation is alleviated for optimum FSG P.L. device. The results clearly indicate that the use of TEOS passivation layer may aggravate PBS, while the FSG passivation layer can be helpful to mitigate the situation. Fig. 3-8 shows the time dependences of the threshold voltage degradation under various positive bias stress voltages at room temperature for optimum FSG and TEOS devices. This result indicates that quantity of electron trap sites was increased with gate bias. It is apparent that ∆V_Thobeys a power-law dependence on stress

time, as given by Equation (3-1) :

∆V_Th ∝ tⁿ (3-1)

where the exponent value n, which dependent relative to bulk trap generation, is found to be ~0.2 and ~0.5 at V_GS −V_Th = 0 5. V for

optimum FSG and TEOS n-MOSFETS, respectively. For optimum FSG device, the threshold voltage degradation by PBS stress is obviously lower than that for TEOS device under various stress voltages. As an effect of F incorporation, this indicates that pre-existing defects were reduced and stress induced defects which were generated in the

high-k film could be alleviated. As shown Fig. 3-9, compared with TEOS sample, FSG sample indeed suppressed the generation of both

∆N_it and ∆N_B , especially ∆N_B . The improvement may be due to

fluorine atoms from CF4 gas, similar to nitrogen atoms, form complexes at the interface and dielectric, which reduce the total number of available Si-H bonds, and passivate the bulk trap, leading to less PBS degradation.

It can be seen that I_D −V_GS curves shift toward more positive

voltage at 125 °C compared to room temperature for both the FSG and TEOS P.L. devices, as shown in Fig. 3-10 (a) and (b), respectively.

Further, V_Th shift of the TEOS sample is clearly larger. Fig. 3-11 shows the V_Th shift as a function of stress time at temperatures ranging from 25 °C to 125 °C. The V_Th shift induced by charge trapping

increased exponentially with temperature. This stress induced defect generation could be observed with temperature acceleration. Since PBTI was thermally active, electron trap site generation was also accelerated by heating. Fig. 3-12 shows ∆N_it and ∆N_B as a function

of time during PBTI for both devices measured at different temperatures. It can be seen that optimum CF4-introduced device always show smaller both ∆N_it and ∆N_B than the TEOS device at all

temperatures. To compare with positive bias stress at 25 °C in Fig. 3-8, PBTI-induced threshold voltage degradation, ∆N_it and ∆N_B as a function of stress time under various positive bias stress voltages at

100 °C for optimum FSG and TEOS n-MOSFETs are show in Fig. 3-13 and Fig. 3-14. The threshold voltage and charge trapping of bulk and interface degradation for both samples are similar to PBS at 25 °C, indicating the power-law dependence and the optimum FSG P.L.

immunity to PBTI that is higher than the TEOS P.L. immunity under various stress overdrive voltages in the range from 0.5 to 1.5V. Fig.

3-15 compares the PBT-stress-time dependence of threshold voltage shift for HfO2/SiON gate stack with optimum FSG P.L. and with TEOS P.L.. A significantly smaller V_Th shift is observed for the optimum FSG sample under the BT stress, V_GS −V_Th =0.5Vat 25 °C and 125 °C. The

exponential values of both samples at 125°C are 0.4 for TEOS sample and 0.2 for FSG sample but 0.5 for TEOS sample and 0.2 for FSG sample at 25 °C. Fig. 3-16 show ∆N_it and ∆N_B as a function of stress

time during PBTI both devices measured at 25 °C and 100 °C. It is found that for both devices, V_Th degradation during PBTI stressing is

primarily caused by the charge trapping in bulk HfO2, rather than the interfacial degradation. Note that the activation energy of ∆V_Thin PBTI

degradation for FSG P.L. is larger than for TEOS P.L. as shown in Fig.

3-17. This indicates that, thermally induced defects were increased as an effect of F incorporation. In addition, the activation energy of ∆V_Th is lower than that of ∆N_it, indicating that V_Th instability is not simply contributed by interface tarp generation, but mainly comes from the more significant charge trapping in the bulk of high-k dielectric as

shown in Fig. 3-18. All results are consistent with the effectiveness of fluorine incorporation from CF4 gas in alleviating the PBT instability.

3.2.3 The Characteristics of Charge De-trapping

The threshold voltage was shifted to positive direction due to negative charges built up within the HfO² shown in Fig. 3-10. Parallel shift of I_D −V_GS curve indicates that the interface qualities are not

degraded significantly despite of significant electron charging.

Interestingly, after relaxation voltage V_g = −2V, a rapid turn around of

VTh shift was observed in Fig. 3-19. Therefore, we can conclude that the electron trapping/de-trapping occurs on the pre-existing (“as-grown”) defects due to no noticeable degradations of the interface electrical property. As shown in Fig. 3-20 shows the threshold voltage shift of the HfO2/SiON high-k gate stack n-MOSFETs for optimum FSG P.L. and TEOS P.L. samples as a function of the static stress/relaxation time with a fixed stress voltage V_GS −V_Th =1.5V and relaxation voltage V_GS = −2V . Basically, the relaxation voltage plays a

significant role to clean up the trapped charge carriers before the next stress cycle. It was also indicated that an charge de-trapping behavior can not cause an additional V_Th instability because the threshold voltage was still shifted above the initial V_Th for both samples. After relaxation, a subsequent stress-induced V_Th increase follows the initial pre-relaxation stress time dependence. It is clear that this

relaxation does not fully recover the V_Th shift caused by the positive bias stress. The residual V_Th shift appears to be determined by the

balance between the built-in potential due to trapped charges and the barrier height for de-trapping [20].

Based on the observations above, a model explaining V_Th

instability behavior during the stress and relaxation can be proposed as shown in Fig. 3-21. The signs of A and B in Fig. 3-22 are defined by de-trapping ratio and residual-trapping ratio, respectively. There are two factors to shift V_Th during the stress. One is electrons filling the

existing traps and the other is the charged damages created during the stress. Portion of the former electrons was de-trapped spontaneously to reduce the instant built-in potential after the stress was removed. However still there are some amount of trapped electrons and charged damage remaining. We can observe that a lot of trapped electron is significant to be instantly pulled out from the pre-existing traps and the created traps are also obviously decreased for the TEOS sample during de-trapping bias, resulting in a few of the residual electrons ( “B_T part in Fig. 3-20” ) and a number of reversible electrons ( “A_T part in Fig. 3-20” ), as shown in Fig. 3-21 (a). However,

a little of trapped electron is de-trapped from the pre-existing traps even if the created traps was effective to decrease for the optimum FSG sample shown in Fig. 3-21 (b), which B_F > B_T in the residual charges characteristic and A_F < A_T in charge de-trapping

characteristic. It indicates that some of deep traps filled or created due to fluorine effect resulting in trapped electrons suffering from the higher barrier height of detrapping behavior during relaxation cycle for the optimum FSG P.L.. As mentioned previous, it was associated with the good correlation of the barrier height between de-trapping behavior and F-P emission results for both samples. The other possible explanation for this phenomenon is larger CET for the optimum FSG P.L than the TEOS P.L.. This CET layer could be source for charge storage, resulting in storing significant amount of trapping in addition to the existing trap for the optimum FSG P.L. shown in Fig.

3-22. The A_T (or A_F) represents charge trapping related defect level

which causing threshold voltage shift, so we can understand defect generation of HfO2/SiON gate dielectric with the optimum FSG P.L. is much less than the TEOS P.L. in operation mode.

3.3 Reliability Impact of various P.L. on HCS