Recently, the high-voltage (HV) technology is prospering due to its extremely extensive applications such as power management integrated circuits (ICs), automotive electronics, light-emitting diode (LED) and liquid-crystal-display (LCD) driver ICs. Due to the high power-supply voltage of HV ICs, latch-up issue has become one of the most critical reliability problems in HV applications, particularly on the power-rail electrostatic discharge (ESD) protection devices. When the ESD protection device is used in the power-rail ESD clamp circuit, the device is expected to be kept off under normal circuit operating condition. Under ESD-stress condition, the ESD protection device should be quickly triggered on to discharge ESD current. If the holding voltage of the ESD protection device in the power-rail ESD clamp circuit is lower than the power supply voltage (VDD), the ESD device may be triggered on by the transient noise to cause a extraordinary serious latch-up failure in HV ICs. The phenomenon often results in IC function failure or even permanent destruction by burning out in such a harsh environment.
As a result, to ensure the reliability of the HV ESD protection device, it is necessary to design an ESD protection device used as the power-rail clamp circuit without suffering the latch-up threat.
1.2 Scheme of ESD Protection Design in High-Voltage (HV) ICs
ESD is an inevitable event of ICs during fabrication, package and assembly processes. The stored ESD charges which are either positive or negative must beeffectively discharged to prevent the internal core circuits from being damaged by ESD overstress during ESD-stress condition. To judge the robustness of ESD protection device, the ESD-testing modes at input-output (I/O) pins with respect to the grounded VDD or VSS pins, pin-to-pin and the VDD-VSS ESD stresses have been specified to verify the whole-chip ESD robustness [1]. As a result, to provide effective ESD protection for whole IC, on-chip ESD protection circuits should be added around the input, output and power lines of the ICs.
Fig. 1.1 shows the whole-chip ESD protection design in high-voltage ICs. The power-rail ESD clamp circuits across the power lines had been used to further increase ESD robustness of the chip [1]. But, it should take latch-up susceptibility into consideration especially while the ESD protection device is used in the power-rail ESD clamp circuit.
Figure 1.1 The scheme of whole-chip ESD protection design in HV ICs [1].
1.3 ESD Protection Design Window of HV ESD Protection Devices
protection devices is confined between power supply voltage (VDD) and gate-oxide breakdown voltages of internal circuits (VBD,internal) [2]. The characteristics of trigger and holding voltage of ESD protection device should be precisely controlled to ensure its effectiveness and robustness during the ESD event. Thus, for an efficient ESD protection device, it is necessary to decrease the trigger voltage (Vt1) and increase the holding voltage (Vhold) to make them locate within the ESD protection design window.
The demands on lower Vt1 and higher Vhold guarantees the ESD protection devices can successfully protect internal circuits from being damaged by ESD overstress under ESD-stress condition and prevent them from mis-triggering under normal circuit operating condition with noise inputs, respectively.
The emerging reliability problem in HV ICs is the latch-up threat resulted from the transient ESD pulse. And the serious latch-up issue caused by the strong snapback of ESD protection device has become more important and challenging with the extensive applications in HV ICs industry. The ESD protection device incidentally triggered with a noise input may cause permanent damage to HV ICs due to latch-up danger, particularly for the ESD protection device used in the power-rail ESD clamp circuit. Therefore, to guarantee the ESD protection device without suffering latch-up danger, the holding voltage of ESD protection devices should be higher than the power supply voltage. It has generally approved that adopt the voltage level of 1.1VDD as the minimum snapback holding voltage to judge the latch-up susceptibility.
Finally, the ESD protection device with high turn-on efficiency and latch-up immunity can be accomplished by accurate control of trigger and holding voltage of ESD protection device within the ESD protection design window.
Figure 1.2 The ESD protection design window of HV ESD protection devices [2].
1.4 Investigation on the Impact of Kirk Effect to HV ESD Protection Devices
The Kirk effect has been analyzed for silicon-based bipolar junction transistors (BJTs) under high current regime [3]-[5]. The influence of Kirk effect becomes more obvious due to the light-doped layer concentration applied to sustain the high supply operating voltage in HV technology. Consequently, Kirk effect is the most significant phenomenon for the parasitic BJT devices used for ESD protection. The Kirk effect can alter the characteristics of ESD protection devices and further degrade the capability against an ESD event, especially while ESD protections devices are used in HV ICs.
Fig. 1.3 shows the onset of Kirk effect in BJT devices. For n-p-n bipolar junction transistors, the Kirk effect starts when the electron concentration injected from emitter exceeds the average background concentration of collector under high current
responsible for the onset of Kirk effect. After the parasitic n-p-n BJT is triggered, the base-collector depletion zone is flooded with electrons because large electrons injects into the depletion region at high collector current density. Such a high level injection, the charge density of base and collector near the reverse-biased junction will be altered. Owing to the high level injection of electrons, the subtraction of electrons and positive ions decrease the positive charge density of collector region near the depletion zone. On the contrary, the negative charge density of base region near the depletion zone is increased because of the addition of electrons and negative ions.
According to charge neutrality principle, the depletion widths are adjusted with the variations of the charge density in the depletion region. At high collector current level, Kirk effect pushes the depletion region out into the collector and leads to an effective increase of the base width. Therefore, Kirk effect in bipolar junction transistors is also well known as base push out effect due to the base widening into the collector region.
In addition, Kirk effect generates another important phenomenon. The electric field at the base-collector depletion zone is completely screened by the electrons flood and the peak field is pushed toward to the highly doped collector region. In general, the positions of the peak electric field and the avalanche breakdown region are roughly located at the same place. Besides, the high electric field can increase the impact ionization rates in the avalanche breakdown region. Similarly, as noted above, the analysis of Kirk effect is still suitable for the p-n-p transistors.
Kirk effect is an important phenomenon in bipolar junction transistors at high current condition, especially for the HV devices with light-doped concentration. To be highly efficient and robust HV ESD protection devices, it is necessarily to take the Kirk effect into consideration because most of ESD protections are operated in the parasitic BJT mode. Kirk effect leads to the base extension and the peak electric field migration which greatly affect the devices characteristics such as extremely low
snapback holding voltage. Besides, the peak electric field shifted into the highly doped collector region can results in higher impact ionization rates which promote the increase of avalanched electron-hole pairs.
(a) (b)
Figure 1.3 The onset schemes of Kirk effect in BJT devices of (a) p-n-p devices and (b) n-p-n devices [3], [4].
In smart technology, the device structures of HV MOSFETs such as laterally diffused n-channel MOS (LDNMOS) and double drain-diffused p-channel MOS
1.4. For both typical HV devices, the gate-grounded LDNMOS devices have been frequently used as on-chip ESD protection devices. However, owing to the inefficient parasitic p-n-p bipolar gain, the second breakdown current (It2) of DDDPMOS is too low to protect the HV ICs against the ESD threat. From the Fig. 1.4, the migration of the highest electric field caused by Kirk effect at high current condition has a great effect on the voltage handling capability of LDNMOS [5]. The highest electric field shifted into the n+/n- junction near the collector side generates an extraordinarily low holding voltage. Such a low holding voltage of HV ESD protection devices will lead to serious latch-up danger under normal circuit operating condition. Therefore, it is an on-going challenge to alleviate the Kirk effect and further design the HV ESD protection devices without suffering latch-up danger.
(a) (b)
Figure 1.4 The devices cross-sectional views with parasitic bipolar transistors and the variations of electric field in (a) DDDPMOS devices and (b) LDNMOS devices under the onset of Kirk effect [5].
Fig. 1.5 shows another cross-sectional view of HV MOSFETs. The n-channel drain extended MOS (nDEMOS) is fabricated in a non-silicided 0.35µm CMOS process. The high-voltage drain has been realized using a thick field oxide (TFO) and lightly doped Nwell to sustain the high supply voltage [6]. The simulated impact ionization region inside an nDEMOS device due to the Kirk effect is shown in Fig.
1.6. For the nDEMOS device at high drain-source bias, the breakdown initiated at the Nwell-Pwell junction, as illustrated by the MEDICI simulation shown in Fig. 1.6 (a).
When increasing the drain bias, a significant voltage drop occurs across the lowly doped Nwell region since it is completely depleted. When the depletion region expands with increasing drain bias, the maximum electric field migrates from the Nwell-Pwell
junction to the N+/Nwell interface. Similarly, this leads to a shift of the impact ionization region towards the N+/Nwell junction and it eventually reach the highly doped N+ drain region which can greatly increase the numbers of the electron-hole pairs. The impact ionization region locates at the heavily doped drain in the snapback state is demonstrated in Fig. 1.6 (b). As a result, the conductivity modulated Nwell region gets flooded by the generated electrons and holes due to the high impact ionization rates in the heavily doped drain.
Figure 1.5 The cross-sectional views of nDEMOS [6].
(a)
(b)
Figure 1.6 The simulated impact ionization region inside an nDEMOS in (a) breakdown state and (b) snapback state due to the Kirk effect [6].
The Fig. 1.7 shows the cross-sectional schematic of the RESURF LDMOS under investigation. The device simulation data on the junction temperature profile within the LDNMOS during the snapback breakdown condition is shown in Fig. 1.8. It shows the N+/N- junction in the drain side has the maximum lattice temperature due to the Kirk effect [7]. Such a surface heat source is partially responsible for the ESD robustness.
Figure 1.7 The cross-sectional views of RESULF LDMOS [7].
Figure 1.8 The device simulation data on the junction temperature profile within the
1.5 Investigation on the Impact of Kirk Effect to Holding Voltage [8]
The Figure 1.9 shows the typical I-V curves for different current regimes including the breakdown, BJT triggering, snapback and high current region after holding voltage in the ggLDMOS device. And the LDMOS device under investigation is shown in Fig. 1.10. After triggering of the parasitic BJT device, the strong source electron injection into the bulk results in a push-out of the depletion region across the lightly doped region of n-epi at the snapback state. The gradual progress of the avalanche impact ionization movement is depicted in Fig. 1.11. Apparently, the avalanche region eventually bumps into the highly n+ doped drain and buried layer diffusion in the high current region, which can generate much more electron-hole pairs. Hence, the impact generated hole are emitted and accumulated, which leads to a rapid increase of the hole concentration in the entire n-epi volume after turn-on of the parasitic BJT device. This effect is corroborated in Fig. 1.10, where the ratio of the avalanche hole nh to the n-epi donor doping concentration nd,epi depending on the depth depi below the FOX is presented. The e-epi resistance and thus the on-resistance is drastically reduced under the high current condition due to the large hole concentration in the n-epi volume. On the other hand, the current path widening is visible at high current region in Fig. 1.10. This effect also contributes to the low on-resistance after the ignition of the parasitic BJT.
The conductivity modulation of the n-epi due to the avalanche hole injection as well as widening of the current path within the large n-epi area lead to the transition from the high resistive breakdown regime to the low on-resistance of the high current region, as shown in Fig. 1.9.
Concluding, the extraordinarily low holding voltage after ignition of the parasitic BJT device can be attributed to three responsible mechanisms occurring in the BJT on-state [8]. One is the large avalanche multiplication factor at the holding state, and
other is reduced on-resistance and another is the large geometric extension of the avalanche region. Among the three parameters, the avalanche multiplication factor is dominant. The reduced on-resistance and the large geometric extension of the avalanche region have been analyzed as above. Now, the dependence of avalanche multiplication factor and the holding voltage is demonstrated in Fig. 1. 12. The large avalanche multiplication factor M is based upon an increase avalanche field. The field increase after triggering of the parasitic BJT is caused by the migration of the depletion region towards the highly doped drain n+ diffusion in contact with the n-epi which serves as a highly doped p+ diffusion due to the injection of the avalanche hole.
The empirical Miller formula is used to describe the voltage V dependence of M, as shown in equation (1.1). The values of ID and IB represent the drain current and impact generated hole current, respectively. Obviously, a lower holding voltage is attributed to the large avalanche multiplication factor, which can be accomplished by decreasing the n value and increasing IB.
( )
Besides, decreasing the k value can also reduce the holding voltage, as shown in Fig. 1.12. The k value represents the ratio of electrons reaching the drain to those that have undergone impact ionization, as shown in equation (1.2). It shows that almost all source emitted electrons reach the drain avalanche region and thus contribute to impact ionization.
.
. Number of Drain Elect
k = Number of Multiplied Drain Elect (1.2)
Figure 1.9 The I-V curves for different current regimes of ggLDNMOS: breakdown, BJT triggering, snapback and high current region after holding voltage [8].
Figure 1.10 Minority carriers (avalanche hole) injection into the n-epi depending on the depth perpendicular below the FOX (see inset) [8].
Figure 1.11 Impact ionization rates for different current regimes of ggLDMOS [8].
Figure 1.12 Dependence of holding voltage from the ration of the number of electrons
1.6 Brief Summary
The more and more extensive use of high-voltage (HV) technology in field applications such as automotive electronics and display driver ICs under demanding environments like high operating temperature and voltage requires very specific and appropriate protection against electrostatic discharge (ESD). As a result, ESD protection has become an important task on the reliability of HV ICs.
The LDNMOS transistor is most used in HV technology. However, using the parasitic NPN mode of the LDNMOS for HV ESD protection is not suitable due to the poor ESD robustness and low holding voltage. The poor ESD robustness is resulted from the non-uniform issue. And the low holding caused by Kirk effect leads to severe latch-up issue.
Among the ESD protection devices in HV technology, the SCR device is attractive and indispensable due to its superior voltage clamping capability, high failure current, high conductance and high area efficiency during an ESD event.
However, the characteristics of high trigger voltage and low snapback holding voltage limit the ESD protection capability of SCR devices especially in HV technology. Thus, the trigger and holding voltage of SCR devices needs to be engineered to maximize the ESD performance.
In HV technology, the characteristic of extraordinarily low holding voltage will cause SCR devices susceptible to the latch-up danger in the real system applications, especially while those devices are used in the power-rail ESD clamp circuit. The extremely low holding voltage is related to the impact ionization occurring at the highly-doped junction due to Kirk effect. Thus, the SCR device for ESD protection in HV ICs is challenging due to the requirement of high latch-up immunity to minimize the risk of ESD-induced latch-up and electrical overstress.
Chapter 2
Prior Designs of Latch-up Immunity Increase
2.1 Holding Voltage Increase by Segmented Emitter Topology [9]
Electrostatic discharge (ESD) protections for high-voltage integrated circuits is developed to minimize the risk of ESD-induced latch-up threat by increasing the holding voltage of novel SCR structure larger than the power supply voltage. The SCR is designed based on the concept that the holding voltage can be increased by reducing the emitter injection efficiency accomplished by a segmented emitter topology in the SCR.
The cross-sectional view of triple-well SCR structure is shown in Fig. 2.1 and was fabricated in the BiCMOS 0.6-µm technology. The D5 and D6 in Fig. 2.1 define the base width and collector resistance in each bipolar transistor. A novel segmented topology is proposed and shown in Fig. 2.2. In the traditional configuration, the emitter N+ blocks in the cathode and emitter P+ blocks in the anode are continuous.
In the novel segmented configuration, the emitter N+ and P+ blocks are not continuous and are separated by the well-tie blocks.
Figure 2.1 The cross-sectional view of triple-well SCR structure.
(a) (b)
Figure 2.2 The top views of SCR with (a) traditional stripe topology and (b) novel segmented topology.
Fig. 2.3 shows the TLP-measured I-V curves of two SCR devices having the same width of 186µm and segment ratio of 1:1 but different topologies. The segment ratio is defined as the number of emitter blocks versus well-tie blocks. Clearly, the holding voltage has been increased significantly from 4V to 40V when the segmented topology is used. Note that the segmented DVR possesses a slightly higher trigger voltage and current due to the decrease in the well resistance by increasing the number of well ties in the device.
The different segment ratios affect the SCR’s holding voltage and can be seen in the TLP-measured results shown in Fig. 2.4. Obviously, decreasing the segment ratio further does not increase the holding voltage. And the failure current It2
decreases with decreasing segment ratio. The poor ESD robustness can be attributed to the current crowding resulting from the smaller emitter area. Nonetheless, a reasonably high It2 of 5.3A is still obtainable for the case of 1:1 segment ratio having a holding voltage of 40V.
Figure 2.3 The TLP-measured I-V characteristics for two SCR devices with the stripe and segmented topologies.
Figure 2.4 The TLP-measured I-V characteristics of SCR devices with different segment ratios and D5= D6= 8µm.
Figure 2.5 The TLP-measured I-V characteristics of SCR devices with 1:1 segment ratio having four D5/ D6 lengths.
Changing the dimensions of D5 and D6 can also alter the ESD performance. Fig.
2.5 shows the TLP-measured I-V characteristics of SCR devices with 1:1 segment ratio having four different D5= D6 dimensions. When D5= D6 is increased from 2 to 8µm, the holding voltage is increased from 10 to 45V due to the larger base width and collector resistance.
A new SCR structure has been developed and realized for high-voltage ESD
A new SCR structure has been developed and realized for high-voltage ESD