The Kirk effect has been analyzed for silicon-based bipolar junction transistors (BJTs) under high current regime [3]-[5]. The influence of Kirk effect becomes more obvious due to the light-doped layer concentration applied to sustain the high supply operating voltage in HV technology. Consequently, Kirk effect is the most significant phenomenon for the parasitic BJT devices used for ESD protection. The Kirk effect can alter the characteristics of ESD protection devices and further degrade the capability against an ESD event, especially while ESD protections devices are used in HV ICs.
Fig. 1.3 shows the onset of Kirk effect in BJT devices. For n-p-n bipolar junction transistors, the Kirk effect starts when the electron concentration injected from emitter exceeds the average background concentration of collector under high current
responsible for the onset of Kirk effect. After the parasitic n-p-n BJT is triggered, the base-collector depletion zone is flooded with electrons because large electrons injects into the depletion region at high collector current density. Such a high level injection, the charge density of base and collector near the reverse-biased junction will be altered. Owing to the high level injection of electrons, the subtraction of electrons and positive ions decrease the positive charge density of collector region near the depletion zone. On the contrary, the negative charge density of base region near the depletion zone is increased because of the addition of electrons and negative ions.
According to charge neutrality principle, the depletion widths are adjusted with the variations of the charge density in the depletion region. At high collector current level, Kirk effect pushes the depletion region out into the collector and leads to an effective increase of the base width. Therefore, Kirk effect in bipolar junction transistors is also well known as base push out effect due to the base widening into the collector region.
In addition, Kirk effect generates another important phenomenon. The electric field at the base-collector depletion zone is completely screened by the electrons flood and the peak field is pushed toward to the highly doped collector region. In general, the positions of the peak electric field and the avalanche breakdown region are roughly located at the same place. Besides, the high electric field can increase the impact ionization rates in the avalanche breakdown region. Similarly, as noted above, the analysis of Kirk effect is still suitable for the p-n-p transistors.
Kirk effect is an important phenomenon in bipolar junction transistors at high current condition, especially for the HV devices with light-doped concentration. To be highly efficient and robust HV ESD protection devices, it is necessarily to take the Kirk effect into consideration because most of ESD protections are operated in the parasitic BJT mode. Kirk effect leads to the base extension and the peak electric field migration which greatly affect the devices characteristics such as extremely low
snapback holding voltage. Besides, the peak electric field shifted into the highly doped collector region can results in higher impact ionization rates which promote the increase of avalanched electron-hole pairs.
(a) (b)
Figure 1.3 The onset schemes of Kirk effect in BJT devices of (a) p-n-p devices and (b) n-p-n devices [3], [4].
In smart technology, the device structures of HV MOSFETs such as laterally diffused n-channel MOS (LDNMOS) and double drain-diffused p-channel MOS
1.4. For both typical HV devices, the gate-grounded LDNMOS devices have been frequently used as on-chip ESD protection devices. However, owing to the inefficient parasitic p-n-p bipolar gain, the second breakdown current (It2) of DDDPMOS is too low to protect the HV ICs against the ESD threat. From the Fig. 1.4, the migration of the highest electric field caused by Kirk effect at high current condition has a great effect on the voltage handling capability of LDNMOS [5]. The highest electric field shifted into the n+/n- junction near the collector side generates an extraordinarily low holding voltage. Such a low holding voltage of HV ESD protection devices will lead to serious latch-up danger under normal circuit operating condition. Therefore, it is an on-going challenge to alleviate the Kirk effect and further design the HV ESD protection devices without suffering latch-up danger.
(a) (b)
Figure 1.4 The devices cross-sectional views with parasitic bipolar transistors and the variations of electric field in (a) DDDPMOS devices and (b) LDNMOS devices under the onset of Kirk effect [5].
Fig. 1.5 shows another cross-sectional view of HV MOSFETs. The n-channel drain extended MOS (nDEMOS) is fabricated in a non-silicided 0.35µm CMOS process. The high-voltage drain has been realized using a thick field oxide (TFO) and lightly doped Nwell to sustain the high supply voltage [6]. The simulated impact ionization region inside an nDEMOS device due to the Kirk effect is shown in Fig.
1.6. For the nDEMOS device at high drain-source bias, the breakdown initiated at the Nwell-Pwell junction, as illustrated by the MEDICI simulation shown in Fig. 1.6 (a).
When increasing the drain bias, a significant voltage drop occurs across the lowly doped Nwell region since it is completely depleted. When the depletion region expands with increasing drain bias, the maximum electric field migrates from the Nwell-Pwell
junction to the N+/Nwell interface. Similarly, this leads to a shift of the impact ionization region towards the N+/Nwell junction and it eventually reach the highly doped N+ drain region which can greatly increase the numbers of the electron-hole pairs. The impact ionization region locates at the heavily doped drain in the snapback state is demonstrated in Fig. 1.6 (b). As a result, the conductivity modulated Nwell region gets flooded by the generated electrons and holes due to the high impact ionization rates in the heavily doped drain.
Figure 1.5 The cross-sectional views of nDEMOS [6].
(a)
(b)
Figure 1.6 The simulated impact ionization region inside an nDEMOS in (a) breakdown state and (b) snapback state due to the Kirk effect [6].
The Fig. 1.7 shows the cross-sectional schematic of the RESURF LDMOS under investigation. The device simulation data on the junction temperature profile within the LDNMOS during the snapback breakdown condition is shown in Fig. 1.8. It shows the N+/N- junction in the drain side has the maximum lattice temperature due to the Kirk effect [7]. Such a surface heat source is partially responsible for the ESD robustness.
Figure 1.7 The cross-sectional views of RESULF LDMOS [7].
Figure 1.8 The device simulation data on the junction temperature profile within the