The cross-sectional views and equivalent trigger circuits of diode-breakdown-trigger SCR (DBTSCR) are shown in Fig. 5.1. In this work, the PMOS and NMOS current mirror circuits are used as the trigger elements. And the channel widths of PMOS and NMOS are 400µm and 200µm, respectively.
Fig. 5.1 (a) shows the 2-stacked p-triggered DBTSCR composed of the diode with reversed junction of HVNW/P+, the PMOS current mirror circuits and the two single SCR devices. Similarly, the 2-stacked n-triggered DBTSCR is made up of the reversed diode, the NMOS current mirror circuits and the two single SCR devices.
Finally, PMOS and NMOS current mirror circuits are used together to form the double-triggered (d-triggered) DBTSCR, as shown in Fig. 5.1 (c).
Fig. 5.2 shows the cross-sectional views of the single SCR devices with and without PSB implantation. The widths and the lengths of anode to cathode (DAC) are 50µm and 13.8µm, respectively. The base widths of the parasitic PNP and NPN transistors are 7.4µm and 6.4µm, respectively. In the single SCR device, the P+
diffusion and the N+ diffusion are inserted to serve as the p-injected node and the n-ejected node, respectively. Therefore, the trigger current generated by the PMOS current mirror circuits can inject into the p-triggered node to decrease the trigger voltage of the stacked SCR devices. Identically, the trigger current generated by the
decrease the trigger voltage.
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Figure 5.1 The cross-sectional views and equivalent trigger circuits of (a) p-triggered DBTSCR and (b) n-triggered DBTSCR and (c) d-triggered DBTSCR.
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Figure 5.2 The cross-sectional views of single SCR devices (a) without PSB and (b) with PSB.
The TLP-measured I-V characteristics of the single SCR devices with and without PSB under the absence of the current mirror circuits are shown in Fig. 5.3.
The holding voltage is approximately to 7.84V for the single SCR device without PSB implantation. On the contrary, the ESD robustness of the single SCR with PSB is extremely low. In fact, it fails as it is triggered. This corresponds to the DC-measured results, as shown in Fig. 5.4. No snapback is observed in Fig. 5.4 (a). Actually, the single SCR device with PSB burns out after applying more DC power. Besides, the
SCR device without PSB. The TLP-measured holding voltage is much lower than that of DC-measured, which can be attributed to the joule heating effect.
Figure 5.3 The TLP-measured I-V characteristics of single SCR devices without current mirror trigger circuits.
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Figure 5.4 The DC-measured I-V characteristics of the single SCR devices (a) with PSB and (b) and (c) without PSB under the absence of the current mirror trigger
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Figure 5.5 The TLP-measured I-V characteristics of (a) p-triggered DBTSCR and (b) n-triggered DBTSCR.
Fig. 5.5 shows the TLP-measured I-V characteristics of p-triggered DBTSCR and n-triggered DBTSCR. The It2 of n-triggered DBTSCR with PSB is extremely low compared to other structures, as shown in Fig. 5.5 (b). The PSB implantations promote the conduction of PNP transistors. Therefore, the two serial PNP transistors take the current, which lead to the poor ESD robustness due to the inefficient beta gain.
From Fig. 5.5 (a), the trigger and holding voltages of p-triggered DBTSCR with PSB are higher than that of p-triggered DBTSCR without PSB. The PSB implantations reduce the base resistances of NPN transistors, and thus more free carriers are needed to forward bias the base-emitter junction. Therefore, the trigger and holding voltages of p-triggered DBTSCR with PSB increase.
Compared to the devices of the p-triggered DBTSCR without PSB and n-triggered DBTSCR without PSB, the trigger and holding voltages of n-triggered DBTSCR without PSB are higher than that of p-triggered DBTSCR without PSB.
This can be attributed to the inefficient PNP beta gain. In general, to decrease the trigger voltage, injecting the current into the base of NPN transistor is more efficient than ejecting the current out from the base of PNP transistor.
Besides, Fig. 5.5 (a) and (b) shows that the p-triggered DBTSCR have higher It2 than that of n-triggered DBTSCR. The parasitic PNP transistors are responsible for the conduction of the stacked SCR devices, when using the NMOS current mirror as trigger circuits. Therefore, the inherent low It2 of PNP transistors lead to the poor ESD robustness of n-triggered DBTSCR.
From Fig. 5.5, the TLP-measured holding voltages of p-triggered DBTSCR without and with PSB implantation are 9.06V and 16.07V, respectively. And the TLP-measured holding voltage of n-triggered DBTSCR without PSB is measured to 13.14V.
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Figure 5.6 The DC-measured I-V characteristics of p-triggered DBTSCR (a) without PSB and (b) with PSB.
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Figure 5.7 The DC-measured I-V characteristics of n-triggered DBTSCR (a) without PSB and (b) with PSB.
Fig. 5.6 and Fig. 5.7 show the DC-measured results of p-triggered DBTSCR and n-triggered DBTSCR. Fig. 5.7 (b) shows that n-triggered DBTSCR with PSB fails while applying more DC power. This corresponds to the TLP-measured measurement, as shown in Fig. 5.5 (b).
In Fig. 5.6, the DC-measured trigger and holding voltages or trigger and holding currents of p-triggered DBTSCR with PSB are higher than that of p-triggered DBTSCR without PSB. This also corresponds to the TLP-measured measurement, as shown in Fig. 5.5 (a). In other words, it is more difficult to trigger on the stacked SCR device with PSB implantation.
Additionally, the DC-measured trigger current of p-triggered DBTSCR without PSB is measured to 105mA, as shown in Fig. 5.7 (a). This can be attributed to the current path of P+/HVNW forward diode, HVNW/P+ reversed diode and NMOS transistor (MN1) before the conduction of the stacked SCR device. It is needed more trigger current ejected out from the n-triggered node to trigger on the stacked SCR while using NMOS current mirror as trigger circuits, and thus the high DC-measured trigger current can be realized. After the trigger current over 105mA, the stacked SCR turns on. Finally, it snaps back into the high current region with the holding voltage of 3.95V.
Among the four proposed structures, the p-triggered DBTSCR with PSB has the highest DC-measured holding voltage, which is measured to 6.25V. Besides, the trigger voltage can be further decreased when NMOS and PMOS transistors are used.
Figure 5.8 shows the TLP-measured and DC-measured I-V characteristics of d-triggered DBTSCR with PSB. Compared to the p-triggered DBTSCR with PSB, the TLP-measured trigger voltage of d-triggered DBTSCR with PSB is smaller. The trigger voltage can be reduced from 25.40V to 19.78V. This is beneficial to apply d-triggered DBTSCR for ESD protection.
Figure 5.8 The (a) TLP-measured and (b) DC-measured I-V characteristics of d-triggered DBTSCR with PSB.
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Figure 5.9 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the d-triggered DBTSCR with PSB under TLU test with positive charging voltage.
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Figure 5.10 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the d-triggered DBTSCR with PSB under TLU test with negative
The measured voltage waveforms of d-triggered DBTSCR with PSB under TLU test with the transient triggering of positive and negative charging voltages are shown in Fig. 5.9 and Fig. 5.10, respectively. A supply voltage of 14V was used and the trigger source was connected directly to the d-triggered DBTSCR with PSB structures.
From the observed voltage waveforms, the d-triggered DBTSCR with PSB structure is triggered on into latch state due to the transient triggering with the capacitor charging voltages of 75V or -30V. However, the clamped voltage waveforms quickly come back to the original supply voltage level of 14V under the capacitor charging voltages of 70V or -25V. In other words, a higher capacitor positive charging voltage is needed to trigger on the d-triggered DBTSCR with PSB structure during the TLU test.
The gate voltages of PMOS transistors are logic low when a transient negative charging voltage occurs. Such the relatively low gate voltages of PMOS transistors can promote the channel conduction of the PMOS transistors. Hence, the d-triggered DBTSCR with PSB structure goes into the latch-up state more easily. In other words, the latch-up danger occurs easily for the d-triggered DBTSCR with PSB structure under the TLU test with the transient negative charging voltage.
Table 5.1 The measurement results of the DBTSCR.
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Figure 5.11 The measured results of (a) holding and trigger voltages and (b) HBM level and MM level of the DBTSCR structures.