The cross-sectional views and equivalent trigger circuits of HV p-type SCR (HVPSCR) and HV n-type SCR (HVNSCR) are shown in Fig. 5.12 and Fig. 5.13. The SCR structure is embedded into the HVPMOS, named HV p-type SCR (HVPSCR).
Similarly, the SCR structure is embedded into the HVNMOS, named HV n-type SCR (HVNSCR). The HVPSCR and HVNSCR structures are complementary. In other words, the SCR structure is embedded into the HVPMOS to form the HVPSCR, and the HVNMOS is added to shunt the base resistance of parasitic NPN transistor of the SCR structure. And the SCR structure is embedded into the HVNMOS to form the HVNSCR, and the HVPMOS is added to shunt the base resistance of parasitic NPN transistor of the SCR structure.
The widths and the lengths of anode to cathode of the SCR structures are 50µm and 16µm, respectively. For the consideration of ESD robustness, the distances of drain contact to gate (DCG) and source contact to gate (SCG) are designed as 8µm and 1.3µm, respectively. Besides, the channel widths are 100µm for both HVPMOS (MP) and HVNMOS (MN) transistors.
In this work, the RC-based circuits are used as the trigger elements. The resistors of HVPSCR and HVNSCR structures are designed to 150kohm. And the capacitor of HVPSCR structure is designed to 2pF, which is made by the HVNMOS. Similarly, the capacitor of HVNSCR structure is also designed to 2pF, which is made by the HVPMOS. The values of RC time delay are designed to distinguish from the ESD stress condition and normal circuit operating condition. Besides, the crossed anodes are fabricated in both structures. And the PSB implantations are inserted to meet the requirement of high DC-measured holding voltage.
(a)
(b)
Figure 5.12 The cross-sectional views of (a) HVPSCR and (b) HVNSCR.
(a) (b)
In Fig. 5.13 (a), the RC-based circuit is used in HVPSCR structure. And the drain of the HVNMOS (MN) is directly connected to the p-ejected node. During normal circuit operating condition, the HVPMOS with embedded SCR is kept off and the HVNMOS (MN) turns on to divide the current out the base of the parasitic NPN transistor. During ESD stress condition, the HVNMOS (MN) is kept off and the HVPMOS with embedded SCR turns on to inject the trigger current into the base of the parasitic NPN transistor. In Fig. 5.13 (b), the CR-based circuit is used in HVNSCR structure. And the source of the HVPMOS (MP) is directly connected to the p-ejected node. During normal circuit operating condition, the HVNMOS with embedded SCR is kept off and the HVPMOS (MP) turns on to divide the current out the base of the parasitic NPN transistor. During ESD stress condition, the HVPMOS (MP) is kept off and the HVNMOS with embedded SCR turns on to inject the trigger current into the base of the parasitic NPN transistor.
The cross-sectional views and equivalent circuits of stacked HVPSCR and stacked HVNSCR are shown in Fig. 5.14 and Fig. 5.15, respectively. The purpose of the stacked configurations is to enhance the latch-up immunity. Fig. 5.16 shows the TLP-measured I-V characteristics of HVPSCR, HVNSCR, stacked HVPSCR and stacked HVNSCR structures. The extremely low It2 of stacked HVPSCR structure can be observed due to the serial conduction path of the parasitic PNP transistor and the PBODY/N+ forward diode. In Fig. 5.16 (a), the It2 in HVPSCR structure is higher than that in HVNSCR structure, which is attributed to the separation of the avalanche current and the high voltage potential. The base widths of HVPSCR structure and HVNSCR structure are 2.5µm and 7.9µm, respectively, as shown in Fig. 5.12. Hence, the conduction efficiency of the parasitic PNP transistor in HVPSCR structure is higher than that in HVNSCR structure. When Kirk effect occurs, the impact ionization region in the HVPSCR structure is pushed into the drain side of the HVPMOS. Then,
the most avalanche generated current occurs at the drain side due to the high avalanche multiplication factor (M). Therefore, the avalanche generated current and the high voltage potential are separated, which leads to less power generation. In this way, the It2 in HVPSCR structure is higher than that in HVNSCR structure. Besides, the trigger and holding voltages of HVNSCR structure are higher than that of HVPSCR structure due to the large base width of the parasitic PNP transistor, which can greatly decrease the beta gain of PNP transistor.
Fig. 5.17 and Fig. 5.18 show the DC-measured I-V characteristics of HVPSCR and HVPSCR structures before trigger and after trigger. For the HVPSCR structure, the conduction path is supposed to be serial path of the PNP transistor and the HVNMOS (MN) under normal circuit operating condition. However, the hard breakdown voltages of gate oxide of HVPMOS and HVNMOS transistors are approximately to 40V. From the results in Fig. 5.17, the HVPSCR is still kept off when the voltage is below 40V. After applying more DC power, the voltage gradually increases. Finally, it snaps back to the high current region with a holding voltage of 6V while the voltage is higher than 40V. But, anticipated turn-on path composed of the serial conduction path of PNP transistor and HVNMOS is missing after trigger of the parasitic SCR device. Because the gate oxides of the HVPMOS and HVNMOS transistors can not sustain in such a high voltage, the controlled capability of HVPMOS and HVNMOS transistors becomes invalid while using the RC-based circuit.
Therefore, the validity of the DC-measured holding voltage is insufficient.
The same phenomenon is observed in Fig. 518. The HVNSCR is still kept off when the voltage is below 40V. After applying more DC power, it snaps back to the high current region with a holding voltage of 7.25V. Similarly, the anticipated turn-on path composed of the serial conduction path of PNP transistor and HVPMOS is
investigate the validity of the DC-measured holding voltage, which is referred to determine the latch-up immunity.
(a)
(b)
Figure 5.14 The cross-sectional views of (a) stacked HVPSCR and (b) stacked
(a)
(b)
Figure 5.15 The equivalent circuits of (a) stacked HVPSCR and (b) stacked HVNSCR.
(a)
(b)
Figure 5.16 The TLP-measured I-V characteristics of (a) HVPSCR and HVNSCR and (b) stacked HVPSCR and stacked HVNSCR.
(a)
(b)
Figure 5.17 The DC-measured I-V characteristics of HVPSCR (a) before trigger and (b) after trigger.
(a)
(b)
Figure 5.18 The DC-measured I-V characteristics of HVNSCR (a) before trigger and (b) after trigger.
The measured voltage waveforms among HVPSCR and stacked HVPSCR and HVNSCR and stacked HVNSCR structures under TLU test with the transient triggering of positive and negative charging voltages are shown from Fig. 5.19 to Fig.
5.26, respectively. A supply voltage of 16V was used and the trigger source was connected directly to the device-under-test (DUT).
From the observed voltage waveforms, the clamped voltage waveforms quickly come back to the original supply voltage level of 16V under the capacitor charging voltages of 70V or -30V in HVPSCR, and 45V or -45V in stacked HVPSCR, and 220V or -295V in HVNSCR and 495V or -875V in stacked HVNSCR structures.
In Fig. 5.21 and Fig. 5.22, the charging voltage levels of the stacked HVPSCR structures under TLU test are extremely low. In Fig. 5.21 (b), the clamped voltage waveform quickly comes back to the original supply voltage level of 16V under the capacitor charging voltages of 50V. However, large current can be observed on the power supply machine. Hence, the stacked HVPSCR structure still fails during the TLU test with charging voltage of 50V. This can be attributed to the poor ESD robustness of stacked HVPSCR structure. The poor ESD robustness causes the stacked HVPSCR more susceptible to damage under TLU test.
Compared to the TLU test with the negative charging voltage, a higher positive charging voltage is needed to trigger on the HVPSCR structure during the TLU test, as shown in Fig. 5.19 and Fig. 5.20. When the transient negative charging voltage occurs, the gate voltage of the HVPMOS transistor becomes logic low. Hence, the HVPMOS transistor is easily ignited to provide the trigger current than the HVPSCR structure facing the transient positive charging voltage. In other words, a lower negative charging voltage stored in the capacitor is needed to trigger on HVPSCR, which can be attributed to the lower gate voltage of HVPMOS transistor with a negative transient noise input. Finally, the parasitic SCR device is triggered after the
turn-on of the HVPMOS transistor during the TLU test. As a result, to trigger on the HVPSCR by transient noise, the required level of positive charging voltage is higher than that of negative charging voltage.
On the contrary, to trigger on the HVNSCR by transient noise, the required level of negative charging voltage is higher than that of positive charging voltage, as shown in Fig. 5.23 and Fig. 5.24. In other words, a higher negative charging voltage stored in the capacitor is needed to trigger on HVNSCR, which can be attributed to the lower gate voltage of HVNMOS transistor with a negative transient noise input.
Compared to the HVPSCR and HVNSCR structures under TLU test with positive charging voltages, the higher charging voltage of HVNSCR structure is needed than that of HVPSCR structure to trigger on the parasitic SCR device.
Therefore, the latch-up immunity of HVNSCR structure to the noise transient on the power lines in high-voltage ICs is higher than that of HVNSCR structure.
In addition, the latch-up immunity to the noise transient on the power lines can be significantly increased by using the stacked configuration of the HVNSCR structure. From the measured results, the positive and negative charging voltages of stacked HVNSCR structure go into that of HVNSCR structure at least two times.
Therefore, the latch-up immunity of stacked HVNSCR structure to the noise transient can be highly increased.
By adjusting different numbers or different types of stacked ESD devices in the power-rail ESD clamp circuits, the transient-induced latch-up issue can be successfully overcome without modifying the high-voltage BCD process. In this work, the higher positive and negative charging voltages of the stacked HVNSCR structure under TLU test can be developed to the levels of 495V and -875V, respectively.
(a)
(b)
Figure 5.19 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the HVPSCR under TLU test with positive charging voltage.
(a)
(b)
Figure 5.20 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the HVPSCR under TLU test with negative charging voltage.
(a)
(b)
Figure 5.21 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the stacked HVPSCR under TLU test with positive charging voltage.
(a)
(b)
Figure 5.22 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the stacked HVPSCR under TLU test with negative charging
(a)
(b)
Figure 5.23 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the HVNSCR under TLU test with positive charging voltage.
(a)
(b)
Figure 5.24 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the HVNSCR under TLU test with negative charging voltage.
(a)
(b)
Figure 5.25 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the stacked HVNSCR under TLU test with positive charging voltage.
(a)
(b)
Figure 5.26 The measured I-V waveforms (a) before transient trigger and (b) after transient trigger on the stacked HVNSCR under TLU test with negative charging
(a)
(b)
Figure 5.27 The measured results of (a) HBM level and MM level and (b) positive and negative charging voltage level under TLU test among the four proposed structures.
Fig. 5.27 shows the measured results of HBM level and MM level and positive and negative charging voltage level under TLU test among the four proposed structures. From the measured results, the HVPSCR, HVNSCR and stacked HVNSCR structures are measured to over 2kV (HBM level) and 200V (MM level). And the higher latch-up immunity of stacked HVNSCR structure can be realized under TLU test with the positive and negative charging voltages of 495V and -875V, respectively.
Table 5.2 The measurement results of HVPSCR and HVNSCR and stacked HVPSCR and stacked HVNSCR.
The measurement results among the four proposed structures are shown in Table 5.2. The TLP-measured holding voltage of the stacked HVNSCR structure in snapback breakdown condition is higher than that of HVNSCR structure. Therefore, the holding voltage of stacked HVNSCR structure can be increased by increasing the numbers of cascaded devices. In addition, the It2 current of stacked HVNSCR structure is only slightly degraded as compared with that of HVNSCR structure.
Latch-up issue of ESD protection devices in high-voltage ICs is also investigated by TLU test. The susceptibility of stacked structures to the noise transient during normal circuit operating condition has been verified by the TLU test. Finally, the stacked HVNSCR structure with higher latch-up immunity is proposed and realized.
5.3 Brief Summary
The proposed diode-breakdown-trigger SCR (DBTSCR) structures and HV p-type SCR (HVPSCR) and HV n-type SCR (HVNSCR) structures are developed and successfully verified in the 0.5-µm BCD technology. Besides, the stacked configurations of DBTSCR structures and HVPSCR and HVNSCR structures are also designed to enhance the latch-up immunity.
To be an optimal ESD protection device, a high efficient trigger circuits are necessary to further decrease the trigger voltages of the stacked configurations. Hence, the current mirror circuits, RC-based circuits and CR-based circuits are added into the DBTSCR structures, HVPSCR structures and HVNSCR structures, respectively.
In the proposed DBTSCR structures, the DC-measured holding voltages are still low compared with the power supply voltage. However, the DC-measured trigger current of the n-triggered DBTSCR without PSB can be increased to 105mA. In addition, the TLP-measured trigger voltage can be significantly decreased by using the PMOS and NMOS current mirror trigger circuits simultaneously.
In the proposed HVPSCR structures and HVNSCR structures, the validity of the DC-measured holding voltages is insufficient due to the limitation of the gate oxide breakdown voltage. However, the latch-up immunity to the noise transient during normal circuit operating condition can be increased by the use of stacked configurations. In this work, a higher latch-up immunity of the stacked HVNSCR structure has been developed and verified during the TLU test.
Chapter 6
Conclusions and Future Works