NF [dB]
Frequency [GHz]
Figure 4.37 Measured NF of the two-stage cascaded cascode LNA of Chip S3#4 and Chip S3#9.
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Gain of LNA at different bias condition VDD1=VDD2=VDD: 0.9V ~ 1.1V, step=0.1V
Gain of LNA at different bias condition VDD1=VDD2=VDD: 0.9V ~ 1.1V, step=0.1V
Figure 4.38 Measured NF and Gain of the two-stage cascaded cascode LNA with dif-ferent bias conditions. (a) NF of Chip S3#4. (b) Gain of Chip S3#4. (c) NF of Chip S3#9. (d) Gain of Chip S3#9.
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Gain of LNA at different bias condition VDD1=VDD2=VDD: 0.9V ~ 1.1V, step=0.1V
Gain of LNA at different bias condition VDD1=VDD2=VDD: 0.9V ~ 1.1V, step=0.1V
Figure 4.38 Measured NF and Gain of the two-stage cascaded cascode LNA with dif-ferent bias conditions. (a) NF of Chip S3#4. (b) Gain of Chip S3#4. (c) NF of Chip S3#9. (d) Gain of Chip S3#9.
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and 23.2 GHz, respectively. The two signals are with the same signal level of –30.3 dBm.
It shows that the presented two-stage cascaded cascode LNA has a PIIP3of –4.2 dBm.
The comparisons of measured and simulated S-parameters of one-stage cascode LNA are shown in Fig. 4.42. The comparisons of measured and simulated S-parameters of two-stage cascaded cascode LNA are shown in Fig. 4.43. Moreover, the comparisons of measured and simulated NF performance of the designed two LNAs are shown in Fig. 4.44.
The difference between simulated and measured NF is because the preliminary version of 45-nm CMOS transistor models is used in the simulation. This transistor model is predicted from 90-nm CMOS spice model, and only the DC characteristics is verified.
Moreover, the RF parasitic effects of the transistors are not modeled well, and no process design kits are provided. Different layout results in different parasitic effects. Due to these uncertainties, the simulated and measured results have some differences.
Besides, in the proposed two-stage LNA, the load of the second-stage is not designed well. LD2 should be larger than LS2 to provide the gain. Therefore, the gain of the two-stage LNA can be improved simply by increasing the value of LD2.
The dc inputs of both one-stage and two-stage LNAs are protected with the power-clamp ESD diodes. Fig. 4.45 shows the test setup of the HBM ESD measurement. The HBM ESD tests are performed between the pad of VDD and the pad of ground with both positive and negative testing voltages. As for the testing case of positive VDD-to-VSS, the measured leakage currents are shown in Fig. 4.46(a) and Fig. 4.46(b). As the ESD level below 3 kV, the I − V curves are not changed too much. However, as the ESD level is increased to 3.5 kV, the I − V curve has dramatically changed. This means fabricated power-clamp diode has the ESD protected level of 3 kV for positive VDD-to-VSS. As for the testing case of negative VDD-to-VSS, the measured leakage currents are shown in Fig. 4.46(c) and Fig. 4.46(d). As the ESD level below 6 kV, the I − V curves are not changed too much. However, as the ESD level is increased to 6.5 kV, the I − V curve has dramatically changed. This means fabricated power-clamp diode has the ESD protected level of 6 kV for negative VDD-to-VSS. The HBM ESD robustness of the fabricated power-clamp diodes are summarized in Table 5.5.
At the 2nd-stage of the two-stage LNA, the performance of the inductor Ld2 is not
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Figure 4.39 Measured one-tone testing results of the two-stage cascaded cascode LNA.
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-35 -30 -25 -20 -15 -10 -5
vdd=1.0v, vb2=0.45v, vb1=0.45v vdd=1.0v, vb2=0.45v, vb1=0.5v vdd=1.0v, vb2=0.5v, vb1=0.45v vdd=1.0v, vb2=0.5v, vb1=0.5v vdd=1.0v, vb2=0.55v, vb1=0.45v vdd=1.0v, vb2=0.55v, vb1=0.5v vdd=1.0v, vb2=0.6v, vb1=0.45v vdd=1.0v, vb2=0.6v, vb1=0.5v
(a)
vdd=1.0v, vb2=0.45v, vb1=0.45v vdd=1.0v, vb2=0.45v, vb1=0.5v vdd=1.0v, vb2=0.5v, vb1=0.45v vdd=1.0v, vb2=0.5v, vb1=0.5v vdd=1.0v, vb2=0.55v, vb1=0.45v vdd=1.0v, vb2=0.55v, vb1=0.5v vdd=1.0v, vb2=0.6v, vb1=0.45v vdd=1.0v, vb2=0.6v, vb1=0.5v
1-dB Compression Point
fin=23.2 GHz
(b)
Figure 4.40 Measured one-tone testing results of the two-stage cascaded cascode LNA with different bias conditions.
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-100
VDD=1.0v, VG2=0.5v, VG1=0.45v
Pin=-30.3 dBm (after compensated input loss) fin1=23.15 GHz, fin2=23.2 GHz
IM3=52.2 dB
PIIP3=Pin+0.5*IM3 ~ -4.2 dBm
Figure 4.41 Measured two-tone testing results of the two-stage cascaded cascode LNA.
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Figure 4.42 Measured and simulated S-parameters of one-stage cascode LNA.
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Figure 4.43 Measured and simulated S-parameters of two-stage cascaded cascode LNA.
good. It requires to be modified to a higher value to increase the gain of 2nd-stage. At the operation frequency of K-Band, the on-chip transmission line effect is not noticeable. For the 2-stage LNA, it does not require to do the inter-stage matching to 50 Ohm. Without doing the inter-stage matching to 50 Ohm, the LNA is possible to push the gain higher.
The noise contributed from the 2nd-stage or the following stage can be suppressed by the high LNA gain. However, as the LNA is designed to operate at higher frequency, V -band or W -band, on-chip transmission line becomes remarkable. Inter-stage matching of the multi-stage LNA needs to be considered [189].
The measured results of the fabricated one-stage and two-stage 45-nm bulk-CMOS LNA are compared with those of published CMOS LNAs around 20 GHz in Table 5.6. As can be seen from Table 5.6, the fabricated one-stage LNA has good linearity performance as well as low power consumption. The LNAs in [143] and [145] have better linearity performance than these works at the cost of higher power consumption.
To characterize the performance of all bulk-CMOS LNAs around 20 GHz, the FOM
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0 2 4 6 8 10 NF of 1-stage LNA (meas.) NF of 1-stage LNA (sim.) NF of 2-stage LNA (meas.) NF of 2-stage LNA (sim.)
NF [dB]
Frequency [GHz]
Figure 4.44 Measured and simulated NF of the presented one-stage and two-stage LNAs.
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