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The Design and Analysis of CMOS K–Band
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Wen-Chieh Wang
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Chung-Yu Wu
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K
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The Design and Analysis of CMOS K–Band
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A Dissertation
Submitted to Department of Electronics Engineering &
Institute of Electronics
College of Electrical and Computer Engineering
National Chiao-Tung University
in partial Fulfillment of the Requirements
for the Degree of
Doctor of Philosophy
in
Electronics Engineering
June 2009
Hsin-Chu, Taiwan, Republic of China
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Transceiver Front-End Circuits
Student : Wen-Chieh Wang
Advisor : Chung-Yu Wu
Department of Electronics Engineering
Institute of Electronics
National Chiao-Tung University
Abstract
In this dissertation, two radio-frequency (RF) front-end circuits using current-mode design methdologies have been proposed and implemented. Moreover, two low-noise am-plifier (LNA) using 45-nm planar bulk-CMOS technology have also been implemented. The operation frequency of the two current-mode RF front-end circuits and the two 45-nm LNAs are within the frequency of K-Band. This dissertation can be mainly divided into three parts, including (1) design and analysis of the K-Band current-mode CMOS receiver front-end circuits, (2) design and analysis of the K-Band current-mode CMOS transmitter front-end circuits, and (3) The K-Band LNAs using 45-nm planar bulk-CMOS technol-ogy with high-Q above-IC inductors implemented through wafer-level package (WLP) technology.
A CMOS current-mode receiver front-end integrated circuit has been proposed. The proposed current-mode receiver front-end is composed of a current-mode LNA and a current-mode down-conversion mixer. This receiver front-end is fabricated in 0.13-µm 1P8M CMOS technology and is operated in the frequency band of 24 GHz. From the
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measurement results, the proposed integrated current-mode receiver front-end has the conversion gain of 11.3 dB, the input-referred 1-dB compression point (IP−1dB) of –13.5
dBm, and the input-referred third-order intercept point (PIIP3) of –1 dBm. The measured
noise figure (NF ) is 14.2 dB at the RF frequency of 24 GHz and LO frequency of 19 GHz. The total power dissipation of this current-mode receiver front-end dissipates 27.8 mW under the condition that the supply voltage of LNA is 0.8 V and the supply voltage of mixer is 1.2 V. The proposed current-mode receiver front-end occupies the active area of 1.45 × 0.72 mm2 where testing pads are included. From the experimental results, the
proposed CMOS current-mode down-conversion mixer can operate well in the K-band, and achieves low-power consumption under low power supply voltage. It can also be shown that the proposed receiver front-end circuit that is integrated with a current-mode down-conversion and LNA has the advantage of low-voltage operation and low-power consumption.
A CMOS current-mode transmitter front-end integrated circuit has been proposed. The proposed current-mode transmitter front-end is composed of a current-mode up-conversion mixer, a current-mode baseband amplifier/repeater, a VCO and a transformer-based VCO buffer/repeater. This transmitter front-end is fabricated in 0.13-µm 1P8M CMOS technology and is operated in the frequency band of 24 GHz. The measured re-sults have shown that the proposed integrated current-mode transmitter front-end exhibits a measured conversion power gain of –5 dB, an IP−1dB of –22 dBm, an output-referred
1-dB compression point (OP−1dB) of –28 dBm, PIIP3of –9.6 dBm, and an output-referred
third-order intercept point (POIP3) of –14.6 dBm. The single-sideband (SSB) noise figure
(NF ) is about 12.7 dB. The on-chip VCO provides the LO frequency from 20.8 GHz to 22.7 GHz with the control voltage varied from 0 V to 2 V. The phase-noise of the VCO is -108 dBc/Hz at 10-MHz offset from 22.7 GHz. Under the 1-V supply voltage, the fab-ricated current-mode double-balanced up-conversion mixer, VCO, VCO buffer/repeater and baseband current buffer/repeater circuits dissipate 3.1 mW, 2.2 mW, 3.3 mW, and 3.1 mW, respectively. The proposed transmitter front-end occupies the active area of 1.5 × 1.1 mm2where testing pads are included. From the experimental results, the proposed CMOS
current-mode up-conversion mixer can operate well in the K-band, and has a very small power consumption. Moreover, it can also be sown that the proposed transmitter
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of low-voltage operation and low-power consumption.
From the experimental results of the proposed receiver end and transmitter front-end circuits, it can be shown that the current-mode design approach is suitable for design-ing RF integrated circuits and has the advantage of low-power consumption. Moreover, the current-mode approach also has the advantage of low-voltage operation and has great potential for designing RF integrated circuits in advanced nanometer CMOS technologies. In addition to investigating current-mode approach to the RF integrated circuits, two
K-band high performance LNAs have been successfully realized by using the 45-nm pla-nar bulk-CMOS technology and high-Q above-IC inductors in WLP technology. The first LNA is made up of a single-ended one-stage cascode amplifier. The measurement results of the implemented one-stage cascode LNA show that the one-stage LNA has a NF of 4 dB, a gain of 7.1 dB, an IP−1dB of –9.5 dBm, and a PIIP3 of+2.25 dBm. The center
frequency of this LNA is about 23 GHz. The LNA consumes 3.6 mW from 1-V power supply voltage. The one-stage cascode LNA occupies the active area of 0.72 × 1.12 mm2. Moreover, the measurement results of the implemented two-stage cascaded cascode LNA show that the two-stage LNA has a NF of 4.4 dB, a gain of 11.6 dB, an IP−1dB of –16
dBm, and a PIIP3 of –4.2 dBm. The center frequency of the two-stage LNA is about
23.4 GHz. The LNA dissipates 9.3 mW from 1-V power supply voltage. The two-stage cascaded cascode LNA occupies the active area of 1.28 × 1.12 mm2.
It is at present the first two successfully verified 45-nm planar bulk-CMOS LNAs operated above 10 GHz. Moreover, as compared to prior works which are operated at the frequency around K-band, it has been shown that the proposed one-stage cascode LNA has the best performance in terms of figure-of-merit (FOM). The FOM of the proposed one-stage cascode LNA is 15.2 GHz.
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A 1896 E S Z` i English Abstract v Acknowledgements ix List of Tables xv
List of Figures xvii
1 Introduction 1
1.1 Background . . . 1
1.2 Review on RF Transceiver Architectures . . . 12
1.2.1 Receiver Architectures . . . 12
1.2.2 Transmitter Architectures . . . 16
1.3 Review on CMOS RF Building Blocks . . . 22
1.3.1 Voltage-Mode Down-Conversion Mixer . . . 22
1.3.2 Voltage-Mode Up-Conversion Mixer . . . 23
1.3.3 Low Noise Amplifier (LNA) . . . 24
1.4 Review on CMOS RF Current-Mode Circuits . . . 25
1.5 Research Motivation . . . 29
1.6 Organization of This Dissertation . . . 30
2 Low-Power Current-Mode CMOS K–Band Receiver Front-End ICs 33 2.1 Operational Principles . . . 34
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2.2 Circuit Designs . . . 36
2.2.1 Current-Mode Low-Noise Amplifier . . . 36
2.2.2 Current-Mode Down-Conversion Mixer . . . 41
2.2.3 Integrated Current-Mode Receiver Front-End . . . 50
2.3 Experimental Results . . . 56
2.4 Summary . . . 63
3 Low-Power Current-Mode K–Band Transmitter Front-End ICs 65 3.1 Design of On-Chip Transformer . . . 66
3.2 Operational Principles . . . 76
3.3 Circuit Designs . . . 77
3.3.1 Current-Mode Up-Conversion Mixer . . . 77
3.3.2 Voltage-Controlled Oscillator . . . 87
3.3.3 Transformer-Based VCO Buffer/Repeater . . . 88
3.3.4 Baseband Current Buffer/Repeater . . . 91
3.3.5 Integrated Current-Mode Transmitter Front-End . . . 91
3.4 Experimental Results . . . 97
3.5 Summary . . . 106
4 45-nm CMOS K–Band LNA With High-Q Above-IC Inductors 109 4.1 45-nm CMOS Technology and Wafer-Level Packaging (WLP) . . . 111
4.1.1 45-nm CMOS Technology [175]–[182] . . . 111
4.1.2 Wafer-Level Packaging (WLP) Technology [116]–[119] . . . 118
4.2 Circuit Designs . . . 123
4.2.1 One-stage cascode LNA . . . 125
4.2.2 Two-stage cascaded cascode LNA . . . 135
4.3 Experimental Results . . . 144
4.4 Summary . . . 172
5 Conclusion 173 5.1 Major Contributions of This Dissertation . . . 173
5.2 Future Work . . . 176
A 1896 E S Bibliography 195 Vita 219 xiii
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1.1 PROSANDCONS OFDIFFERENT TECHNOLOGIES . . . 11 2.1 DEVICEPARAMETERS OF24-GHZ CMOS CURRENT-MODE LNA . . 53 2.2 DEVICE PARAMETERS OF 24-GHZ CMOS CURRENT-MODE DOWN
-CONVERSIONMIXER ANDOUTPUTBUFFER . . . 53
2.3 THEMEASUREDPERFORMANCE ANDCOMPARISONRESULTS OFPUB -LISHED 24-GHZRECEIVER FRONT-ENDCIRCUITS . . . 64
3.1 DEVICEPARAMETERS OFTHEPROPOSEDCURRENT-MODEDOUBLE -BALANCEDUP-CONVERSIONMIXER . . . 92 3.2 DEVICE PARAMETERS OF VCO AND TRANSFORMER-BASED VCO
BUFFER/REPEATER . . . 94
3.3 DEVICEPARAMETERS OFBASEBAND CURRENT BUFFER/REPEATER . 94
3.4 PERFORMANCE COMPARISONWITHPREVIOUSLY PUBLISHED LOW
-VOLTAGECMOS UP-CONVERSIONMIXER . . . 107
3.5 PERFORMANCECOMPARISONWITHPREVIOUSLYPUBLISHEDCMOS
TRANSMITTERFRONT-ENDOPERATED AROUND20 GHZ . . . 108 4.1 CHARACTERISTICIMPEDANCE OFTHETRANSMISSIONLINEEXTRACTED
FROM HFSS . . . 123 4.2 EQUIVALENTRLGC MODEL PARAMETERS FROM HFSS . . . 124 4.3 DESIGNPARAMETERS OFONE-STAGECASCODELNA . . . 135 4.4 DESIGNPARAMETERS OFTWO-STAGE CASCADEDCASCODELNA . 138 4.5 HBM ESD ROBUSTNESS OFPOWER-CLAMPSTI DIODE . . . 170
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4.6 PERFORMANCE COMPARISON WITH BULK-CMOS LNAS AROUND
20 GHZ . . . 171
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1.1 The popular wireless standards and applications today [1]. . . 2
1.2 The application coverage of PAN, LAN, MAN and WAN. . . 3
1.3 The evolution and landscape of wireless communication. . . 3
1.4 The bit rate versus coverage of the today wireless applications. . . 4
1.5 The bandwidth demands in consumer electronics [73]. . . 4
1.6 The illustration of vehicular radar applications [89]. . . 7
1.7 The scenarios for short-range and long-range backbone wireless commu-nication networks for home-RF applications (a) [89], and (b) [96]. . . 9
1.8 The prediction of advancement of CMOS transistors in accordance with the reduction in the gate length by ITRS [89]. . . 10
1.9 fT of various kinds of technologies and frequency of personal mobile and wirelessLAN communication are plotted versus years. The supply voltage of MOSFET is also plotted. . . 10
1.10 Block diagram of the heterodyne or IF receiver. . . 13
1.11 Block diagram of the homodyne, direct-conversion, or zero-IF receiver. . 15
1.12 Two sources of DC offsets in the direct-conversion receiver. . . 16
1.13 Block diagram of the direct-conversion transmitter. . . 17
1.14 Third-order intermodulation by a non-linear PA in a direct-conversion transmitter. . . 18
1.15 LO Pulling in a direct-conversion transmitter. . . 19
1.16 Block diagram of the two-step heterodyne transmitter. . . 20
1.17 The reduction of supply voltage and threshold voltage in accordance with the scaling of channel length of CMOS technologies. . . 26
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1.18 The proposed K-band receiver front-end integrated with newly current-mode down-conversion mixer. . . 29 1.19 The proposed K-band transmitter front-end integrated with newly
current-mode up-conversion mixer. . . 30 2.1 The block diagram of the 24-GHz current-mode receiver front-end. . . 35 2.2 The circuit diagram of the proposed two-stage cascaded current-mode
LNA at the low supply voltage of 0.8 V. . . 37 2.3 The small-signal equivalent circuit of the two-stage cascaded
current-mode LNA at the operating frequency of ω0. . . 37
2.4 The circuit diagram of the proposed two-stage cascaded current-mode LNA at the normal supply voltage of 1.2 V. . . 38 2.5 The simulated (a) S-parameters, and (b) NF and NFminof the proposed
current-mode LNA. . . 42 2.6 The simulated S21 of the current-mode LNA in different process corners
(a) at the supply voltage of 0.8 V, and (b) at the supply voltage of 1.2 V. . 43 2.7 Simulated linearity performance of the current-mode LNA by (a) 1-tone
analysis, and (b) 2-tone analysis. . . 44 2.8 Conceptual block diagram of the current-mode down-conversion mixer. . 45 2.9 Circuit diagram of the current-squaring circuit and bandpass filter. . . 45 2.10 Circuit diagram of the current-summing circuit. . . 50 2.11 Circuit diagram of the current-summing circuit. . . 51 2.12 Detailed connections of the 24-GHz current-mode receiver front-end with
output buffer. . . 52 2.13 Simulated linearity performance of the 24-GHz current-mode receiver by
two-tone HB analysis. . . 54 2.14 Cross-section view of back-end process. . . 56 2.15 Chip microphotography of the fabricated 24-GHz current-mode receiver
front-end. . . 57 2.16 The environment setup of (a) S-parameter measurement, (b) linearity
measurement, and (c) noise figure measurement. . . 59
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2.17 The measured and simulated conversion gain of the receiver versus RF
input frequency. . . 62
2.18 The measured linearity performance of the receiver by two-tone testing. . 62
3.1 The winding scheme of (a) XFMR-I, and (b) XFMR-II. . . 68
3.2 Cross-section view of the back-end from the technology. . . 69
3.3 The metal structure of (a) XFMR-I, and (b) XFMR-II. . . 70
3.4 The circuit connections of the transformer to be tested. (a) XFMR-I, and (b) XFMR-II. . . 71
3.5 Simulated S11and S22of (a) XFMR-I, and (b) XFMR-II. . . 72
3.6 Simulated S21of (a) XFMR-I, and (b) XFMR-II. . . 73
3.7 Simulated self-inductance of primary and secondary windings LP,self and LS,self of (a) XFMR-I, and (b) XFMR-II. . . 74
3.8 Simulated coupling-coefficient kP S and quality factor Q of (a) XFMR-I, and (b) XFMR-II. . . 75
3.9 Block diagram of the proposed current-mode transmitter front-end. . . 78
3.10 Circuit diagram of current-squaring circuit. . . 79
3.11 Circuit diagram of current-mode double-balanced up-conversion mixer. . 81
3.12 Schematic diagram of the subtraction of current signals by (a) current mirror circuits [162], (b) LC phase-shift network [167]. . . 84
3.13 The relation among simulated CGintrinsic, the equivalent PLO,IN, and the amplitude of the differential LO current signal idif f −loin. . . 87
3.14 The relation between simulated CGintrinsic and the amplitude of the di ffer-ential IF current signal idif f −if in. . . 88
3.15 Circuit diagram of VCO. . . 89
3.16 Simulated tuning curve of VCO. . . 89
3.17 Simulated phase noise of the VCO. . . 90
3.18 Circuit diagram of transformer-based VCO buffer/repeater. . . 90
3.19 Circuit diagram of baseband current buffer/repeater. . . 92
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3.20 Detailed connections of the proposed integrated current-mode transmitter front-end circuits. . . 93 3.21 Simulated linearity performance of the proposed current-mode transmitter
front-end. . . 95 3.22 Simulated matching characteristics of (a) IF port, and (b) RF port. . . 96 3.23 Transient simulation results of the proposed current-mode transmitter
front-end. . . 97 3.24 Chip microphotograph of the proposed integrated current-mode
transmit-ter front-end. . . 98 3.25 The environment setup of (a) S-parameter measurement, (b) linearity
measurement, and (c) noise figure measurement. . . 100 3.25 The environment setup of (a) S-parameter measurement, (b) linearity
measurement, and (c) noise figure measurement (Con’t). . . 101 3.26 Measured tuning range of VCO. . . 101 3.27 Measured matching characteristics of (a) IF port, and (b) RF port. . . 102 3.28 Measured and post-simulated power conversion gain versus IF input power
from one-tone testing result. . . 103 3.29 Measured 3rd-order intermodulation from two-tone testing result. . . 104 3.30 Measured conversion power gain versus LO frequency. . . 104 3.31 Measured LO leakage versus IF input power PIF,IN at the RF output port 105 4.1 The 3-D drawing of the FinFET device and the SEM picture of FinFET
device [175]. . . 112 4.2 The SEM picture of the device. Cross-section view of planar bulk
metal-gate transistor [177]. . . 113 4.3 Cut-off frequencies fT for different gate lengths, comparing bulk CMOS
with FinFETs. (a) [175] and (b) [177]. . . 115 4.4 Results of the compact model for planar and FinFET 45-nm CMOS
de-vices (lines) compared with preliminary experimental data for similar processes (symbols). (a) The cutoff frequency fT versus current density
ID/W for different channel lengths, and (b) the gm/W versus ID/W [182].117
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M1-M5 metal levels: conventional via (through BCB-2) and high aspect ratio via (HARVi) through BCB-1 [118]. . . 120 4.6 Microphotograph of a 1.8-nH thfilm post-processed symmetrical
in-ductor, including the pad connections for wafer probing. The left induc-tor is without patterned poly-silicon ground shield, and the right inducinduc-tor is with patterned poly-silicon ground shield. The inductor has two turns (N ), an inner radius of 125 µm (Rin), 10-µm metal spacing (S), and a metal trace width (W ) of 30 µm [118]. . . 121 4.7 Measurement (solid line) and simulation result (dashed line) of the series
inductance and the Q factor of thin-film post-processed inductor with a designed inductance of 1.8 nH, both for single-ended (QSE) and di ffer-ential (QDIF F) applications. The inductor has no patterned poly-silicon ground shield: N = 24, S = 10µm, W = 30µm, and Rin = 125µm [118]. 122 4.8 The measured quality factor of single-ended QSE and differential QDIF F
applications of two-turn symmetrical thfilm post-processed 1.8-nH in-ductors with and without a patterned poly-silicon ground shield: N = 2,
S= 10µm, W = 30µm, and Rin= 125µm [118]. . . 122 4.9 The simulated relation between fT and bias voltage of cascode device
with the channel width which is varied from 5 µm to 80 µm, and the minimum channel length of 45 nm. . . 126 4.10 The simulated relation among fT, gm, and bias voltage of cascode device. 127 4.11 Circuit diagram of the one-stage cascode LNA. . . 128 4.12 Layout diagram of the one-stage cascode LNA. . . 130 4.13 Simulated S-parameters of one-stage cascode LNA. . . 131 4.14 Simulated NF and NFminof one-stage cascode LNA. . . 132 4.15 Simulated stability factor of one-stage cascode LNA. . . 132 4.16 Simulated (a) load stability circle, and (b) source stability circle of
one-stage cascode LNA. . . 133 4.17 Simulated linearity performance of one-stage cascode LNA. . . 134
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4.18 Circuit diagram of the two-stage cascaded cascode LNA. . . 136 4.19 Layout diagram of the two-stage cascaded cascode LNA. . . 139 4.20 Simulated S-parameters of the two-stage cascaded cascode LNA. . . 140 4.21 Simulated NF and NFminof two-stage cascaded cascode LNA. . . 141 4.22 Simulated stability factor of two-stage cascaded cascode LNA. . . 141 4.23 Simulated (a) load stability circle, and (b) source stability circle of
two-stage cascaded cascode LNA. . . 142 4.24 Simulated linearity performance of two-stage cascaded cascode LNA. . . 143 4.25 Environment setup of S-parameter measurements. . . 144 4.26 Environment setup of linearity measurements. . . 145 4.27 Environment setup of noise figure measurements. (a) Calibration, (b)
evaluate the losses before and after DUT, and (c) NF measurement. . . . 146 4.27 Environment setup of noise figure measurements. (a) Calibration, (b)
evaluate the losses before and after DUT, and (c) NF measurement (Con’t).147 4.28 Chip microphotography of the one-stage cascode LNA. . . 148 4.29 Measured S-parameters of the one-stage cascode LNA of (a) Chip S1#9,
and (b) Chip S3#4. . . 149 4.30 Measured NF of the one-stage cascode LNA of Chip S1#9 and Chip S3#4.150 4.31 Measured NF and Gain of the one-stage cascode LNA with different bias
conditions. (a) NF of Chip S1#9. (b) Gain of Chip S1#9. (c) NF of Chip S3#4. (d) Gain of Chip S3#4. . . 151 4.31 Measured NF and Gain of the one-stage cascode LNA with different bias
conditions. (a) NF of Chip S1#9. (b) Gain of Chip S1#9. (c) NF of Chip S3#4. (d) Gain of Chip S3#4 (Con’t). . . 152 4.32 Measured one-tone testing results of the one-stage cascode LNA. . . 153 4.33 Measured one-tone testing results of the one-stage cascode LNA with
dif-ferent bias conditions. . . 154 4.34 Measured two-tone testing results of the one-stage cascode LNA. . . 155 4.35 Chip microphotography of the two-stage cascaded cascode LNA. . . 156 4.36 Measured S-parameters of the two-stage cascaded cascode LNA of (a)
Chip S3#4, and (b) Chip S3#9. . . 157
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4.38 Measured NF and Gain of the two-stage cascaded cascode LNA with different bias conditions. (a) NF of Chip S3#4. (b) Gain of Chip S3#4. (c) NF of Chip S3#9. (d) Gain of Chip S3#9. . . 159 4.38 Measured NF and Gain of the two-stage cascaded cascode LNA with
different bias conditions. (a) NF of Chip S3#4. (b) Gain of Chip S3#4. (c) NF of Chip S3#9. (d) Gain of Chip S3#9. . . 160 4.39 Measured one-tone testing results of the two-stage cascaded cascode LNA. 162 4.40 Measured one-tone testing results of the two-stage cascaded cascode LNA
with different bias conditions. . . 163 4.41 Measured two-tone testing results of the two-stage cascaded cascode LNA. 164 4.42 Measured and simulated S-parameters of one-stage cascode LNA. . . 164 4.43 Measured and simulated S-parameters of two-stage cascaded cascode LNA.165 4.44 Measured and simulated NF of the presented one-stage and two-stage LNAs.166 4.45 Environment setup of HBM ESD measurement. . . 167 4.46 Measurement results of HBM ESD testing. (a) Positive VDD to VSS, (b)
positive VDDto VSS, (c) negative VDD to VSS, and (d) negative VDDto VSS. 168 4.46 Measurement results of HBM ESD testing. (a) Positive VDD to VSS, (b)
positive VDDto VSS, (c) negative VDDto VSS, and (d) negative VDDto VSS (Con’t). . . 169 4.47 Comparisons with published works by F OMLNA. . . 170 A.1 The current-squaring circuit in down-conversion mixer. . . 180 B.1 Current-squaring circuit of up-conversion mixer. . . 188
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Chapter 1
Introduction
1.1
Background
Over the last two decades, the frequency spectra within 1 GHz to 10 GHz have gradually become crowded because the massive requirements of data transmission from the modern wireless applications have intensively sprung up. These popular wireless standards and their application are shown in Fig. 1.1 [1]. Fig. 1.2 depicts the di ffer-ent application coverage of personal-area network (PAN), local-area network (LAN), metropolitan-area (metro) network (MAN) and wide-area network (WAN). These mod-ern wireless communication systems, such as global system for mobile (GSM), general packet radio service (GPRS), enhanced data GSM environment (EDGE), wideband code division multiple access (W-CDMA), personal handy-phone system (PHS), digital video broadcasting–handheld (DVB–H), radio-frequency identification (RFID), ZigBee, Blue-tooth, wireless local area network (WLAN), high performance radio LAN (HiperLAN) type-I and type-II, ultra-wideband (UWB), etc., have induced a great deal of interferences which will influence the quality of data transmission [2]–[49]. Due to overcrowding and interferences at low frequency spectra, the operating frequencies of these applications have been pushed toward the higher frequency bands. Sufficient free spectra for future wireless networks or wireless services are allocated at industrial-science-medical (ISM) radio bands around 17 GHz, 24 GHz, and 60 GHz [50]. Consequently, many researchers start to investigate millimeter-wave transceiver front-end circuits at the higher frequency
A 1896 E S THE NET WAN LAN LAN LAN LAN 802.11a/g HiperLAN2 802.11a/b/g 802.11b Bluetooth 802.11b 3G? 802.xx? WLAN 802.11a/b/g/n PAN Bluetooth UWB WAN GPRS/EDGE WCDMA …… Fixed Wireless Access 802.16d Mobile Wireless Access 802.16e
Figure 1.1 The popular wireless standards and applications today [1].
bands, 24 GHz (K-Band) [51]–[67] and 60 GHz (V -Band) [68]–[72] for example, where the spectra are much cleaner and can provide higher bandwidth. As shown in Fig. 1.3, the higher bandwidth of these radio bands enables significantly the higher data rata applica-tions. Moreover, the relationship between transmission bit-rate and coverage is shown in Fig. 1.4. As shown in Fig. 1.5 [73], the required data rates of the consumer electronics has been increased from 20 Mbps to 10 Gbps. To make these consumer electronics wireless, it demands very high data bandwidth and, therefore, higher operating frequency such as 24 GHz and 60 GHz. In the recent years, several standards have been set for the wireless consumer electronics with very high data rates in the frequency bands of 24 GHz and 60 GHz.
In the globally available 60-GHz frequency band, a large amount of spectrum is avail-able on an unlicensed basis in many regulatory domains. The band 57–64 GHz is al-located in North America [74], [75] and South Korea, while 59–66 GHz is alal-located in Japan [76]. Besides, European Union (EU) is in the process of creating similar
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1.1. BACKGROUND 3
Figure 1.2 The application coverage of PAN, LAN, MAN and WAN.
10 k 100 k 1 M 10 M 100 M 1 G 10 G 0.1 1 10 100 Operation Frequency [GHz] d a ta rates [b p s] paging 2G/2.5G 3G 802. 11 b /g 802. 11 a 802. 16 e (W iM AX) WiMedia/ UWB 802. 11 n B T 1. 2/ 2 24 GH z oppor tu n it y 60 GH z oppor tu n it y Voice (Cellular Phone) DSL Wireless LAN Wireless USB OC-12 pt-to-pt HDTV (HDMI 1.2/1.3) OC-48 pt-to-pt Zigbee Zigbee Dat a ra tes incr easi ng cont inuo usly 10 k 100 k 1 M 10 M 100 M 1 G 10 G
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Figure 1.4 The bit rate versus coverage of the today wireless applications.
Compressed Data Carrier Distribution Data rates ~ 20 Mbps
Uncompressed HD Data in-home Distribution
Data rates up to 10 Gbps (HDMI 1.3)
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1.1. BACKGROUND 5
tions [77]. A total of 7 GHz is allocated for use, 5 GHz of which is overlapping. With 7 GHz of bandwidth, there are many high data rate applications that one can envision. The 60-GHz radio can be useful in the design of high-speed (up to several Gbps) wireless links. Recent development in 60-GHz radio technologies are for two main applications: a) fixed wireless, and b) wireless personal area network (WPAN). In fixed wireless appli-cation, it has been used in point-to-point high speed links for telecommunications back-hauls. In WPAN applications, particularly with increased use of high-definition television (HDTV), the standard organizations, such as Institute of Electrical and Electronics En-gineering (IEEE), WirelessHD Alliance, European Computer Manufacturers Association (ECMA), and European Telecommunications Standard Institute (ETSI), as well as several industrial companies are working for the standardization of the 60-GHz radio [78]–[84]. In addition to the IEEE 802.16 standard for wireless metropolitan area network (WMAN) which covers 10 to 66 GHz [79], the IEEE is already home to a standard initiative for 60-GHz WPANs, called IEEE 802.15.3c [80]. Besides, the WLAN portion of the IEEE, 802.11, which sets the base standards for Wi-Fi, is considered to create a standard for 60 GHz. The IEEE 802.15.3c group is firmly focused on distribution of high-definition video and other content, and on high speed synchronization of devices, which does not seem to leave much space for 60-GHz Wi-Fi where the study group IEEE 802.11 is focusing on very high throughput (VHT) Wi-Fi but under IEEE rules [81].
The WirelessHD Alliance has completed the WirelessHD (WiHD) Version 1.0 high-speed radio communication standard for data rates of up to 4 Gbps via the globally un-licensed 60-GHz band of the spectrum [82]. The wide bandwidth makes it possible to attain a high data transfer rate. It was developed to provide a way of connecting high-definition content sources and screens cordlessly. Note that the core technology of WiHD promotes theoretical data rates as high as 25 Gbps. The WiHD replaces the wires in the high definition multimedia interface (HDMI) with radio links, and is designed to handle HDTV video streams between audio/video (AV) equipments. The target is defined as handling full HD video without high-efficiency coding. The ECMA TC-48 is developing a standard for short-range communications in the unlicensed 60-GHz band of the spec-trum [83], [84]. The standard will provide high-rate WPAN (including point-to-point) transport for both data transfer and multimedia streaming. The key applications are HD
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AV streaming, wireless docking station, and short-range Sync&Go.
The bands at higher frequency are attractive to RF designers despite their associated high dispersion losses. So far, numerous work have been targeted at the free spectrum of 60 GHz. However, most of the standards for 24-GHz and 60-GHz applications are still under development. In the near future, the commercial applications may prefer the fre-quency spectra at 24-GHz frefre-quency band, because several standards have been developed for this frequency band and the CMOS technology is gradually matured for the wireless applications in the 24-GHz frequency band. In addition to the ISM band within 24–24.25 GHz [50], [85], the Federal Communications Commission (FCC) has also opened the spectrum from 22 GHz to 29 GHz in 2002. The 7-GHz spectra have been allocated for ultra-wideband vehicular radar applications, short-range automotive radar systems, and autonomous cruise control (ACC) applications [86]–[88], making the 24-GHz band ap-pealing from both wireless communication and car radar perspectives, which are shown in Fig. 1.6 [89]. Some applications such as WLANs, local multi-point distribution services (LMDS) [85], point-to-point wireless communications [90], and other ISM applications have been also proposed in the frequency band of 24 GHz. Furthermore in Europe, the ETSI has specified that the HiperLink standard will be allocated in the 17-GHz ISM band to provide point-to-point short-range connections, and the HiperAccess will adopt fre-quencies higher than 20 GHz to cover long-range distances [91]. Of particular interest for the next WLAN generation is the 17 GHz band in the frequency range from 17.1 GHz to 17.3 GHz [66], [67]. Several promising studies have been published about indoor propa-gation conditions and its potential for future wireless network systems. It is intended to use 17 GHz band for a parallel network to the existing WLANs with data rates up to 54 Mb/s (HiperLAN) and for short range links with data rates up to 155 Mb/s (HiperLink). Such short range high data rate connections are ideally suited to link modern multimedia devices within the office or home. The ETSI has also specified the automotive collision warning short-range radars will be allocated in 24 GHz band which is from 24.05 GHz to 24.25 GHz [92]–[95].
According to the above-mentioned situations, Fig. 1.7(a) [89] and Fig. 1.7(b) [96] show such scenarios with clusters for short-range and long-range backbone wireless com-munication networks for home-RF applications at 17 GHz, 24 GHz, and 60 GHz in the
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near future. Although the standardizations of both applications have not been accom-plished, the possibilities of new huge wireless market lead to the interest of the commu-nication industries.
To implement new hardware for wireless communication systems, low manufacturing costs are of paramount importance to be competitive in the stringent wireless markets. This argument drives the research on highly integrated semiconductor chips, and the ulti-mate goal is a low cost solution of a wireless transceiver combined both analog RF front-end and digital baseband signal processing on the same die without any external compo-nents. Nevertheless, in the past, the millimeter-wave circuits that operated in 24-GHz, 60-GHz, or even higher frequency bands were usually realized by the SiGe(C), BiCMOS, or III-V devices because of their high unity gain frequency fT and maximum operating (or oscillation) frequency fMAX[19], [20], [97]–[104]. Although SiGe(C), BiCMOS, and III-V devices exhibit good performance in high-frequency circuits, these technologies suf-fer from high cost and great difficulties to integrate with complex digital systems which are usually realized by CMOS technologies. In the past, CMOS technologies are not well suited for high frequency analog and RF circuits. The CMOS transistors have poor char-acteristics in terms of gain, noise, and high frequency behavior in comparison to bipolar transistors. Furthermore, high substrate conductivity of silicon-based processes intro-duces additional inductive and capacitive energy loss mechanisms in passive components, such as inductors, capacitors, and transmission lines, which are intensively used in high-speed, RF, and microwave ICs. These effects together with relatively thin metallization layers degrade the quality factor of the on-chip passive devices [105]–[109].
In recent years, significant performance improvement of CMOS digital applications comes from continuous scaling of CMOS channel length. In MOSFETs, smaller di-mensions result in shorter transient times and lower parasitic capacitances. Even in a velocity-saturated MOSFET, the reduction in the channel length improves the fT by low-ering the gate-to-source capacitance. From ITRS prediction, the advancement of the CMOS transistors in accordance with the reduction in the gate length has been shown in Fig. 1.8 [89]. As shown in Fig. 1.9, the fT of CMOS devices have been beyond sev-eral tens GHz with the fast advancement of CMOS technologies into nanometer or deca-nanometer nodes and comparable to those of SiGe(C) bipolar and BiCMOS and III-V
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1.1. BACKGROUND 9
(a)
Each of these portable devices has a need to connect to other devices such as PCs or stationary consumer electronics products, such as stereos, HDTVs, video recorders, enter-tainment PCs, or the like. All these devices would benefit from the ability to connect without cables. Think, for instance, about the number of devices in your home and the tangle of wires between them. Wireless USB would eliminate these wires and enable devices to wirelessly connect to each other. Naturally, the CE environment will have high expectations for performance. Many consumer usage models will center on demanding streaming media distribution using compression algorithms. Typical video delivery with standard SDTV/DVD can consume between 3 to 7 Mbps, while HDTV can require between 19 to 24 Mbps. A point distribution technology
3
Figure 1. Home usage scenarios that could be “unwired” with Wireless USB.
Wired LAN Wireless LAN Wired USB Wireless USB Audio Cluster Family PC Cluster Gaming Cluster Home Thea ter Cluster Home Office Cluster
Long Range Netw orking/Connecti vity Wired & Wireless Broadband Video/Da ta Access Broadband Video/Da ta Access Remote Control Remote Control Phone Phone Broadband Data/V oice Access Broadband Data/V oice Access
Some Top Candidates for Wireless USB Devices in the Home
■Entertainment PC
■Digital Camcorder
■Digital Still Camera
■HDTV ■DVD-RW/CD-RW (Recorder/Player) ■External Storage Device (HDD) ■Game Console ■MP3 Player
■Set Top Box
■PDA or other handheld
mobile device ■Personal Video Player (PVP) ■Personal Video Recorder (PVR) ■Printer (b)
Figure 1.7 The scenarios for short-range and long-range backbone wireless communi-cation networks for home-RF applicommuni-cations (a) [89], and (b) [96].
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Figure 1.8 The prediction of advancement of CMOS transistors in accordance with the reduction in the gate length by ITRS [89].
77 79 81 83 85 87 89 91 93 95 97 99 01 03 05 07 09 0.1 1 10 102 103 0 2 4 6 8 Bipolar MOSFET BiCMOS/SiGe GaAs HEMT 3μm 2μm 1.5μm 1μm 0.8μm 0.6μm 0.5μm 0.35μm 0.25μm0.18μm 0.150.13μmμm 90nm 65nm45nm CMOS Bipolar GaAs HEMT BiCMOS/SiGe
Personal Mobile Commun.
Personal Mobile Communication WirelessLAN Commun. 802.15.3c, 802.11VHT, WiHD, ECMA TC-48 UWB 802.11a 802.11b 802.11g 802.11n Mobile WiMax (802.16) WirelessLAN Communication v HiperAccess, HiperLink 802.15.4 (ZigBee) Bluetooth GSM PHS C u t-off F requenc y ( fT ) [GH z] Year V o ltage [ V ]
Supply Voltage of MOSFET
Operating fre q u en cy [GH z]
Figure 1.9 fT of various kinds of technologies and frequency of personal mobile and wirelessLAN communication are plotted versus years. The supply voltage of MOSFET is also plotted.
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Table 1.1
PROSANDCONS OFDIFFERENT TECHNOLOGIES
Technology GaAs, HEMT SiGe/BiCMOS CMOS
gm High Moderate Low
fT High Moderate Low
RF performance High Moderate Low
Yield Low Moderate High
Integration capability Low Moderate High
Cost High Moderate Low
Technology improvement Slow Moderate Fast
technologies [19], [20], [110], [111]. Hence, nanometer CMOS technologies have already become attractive solutions for wireless communication system in 24-GHz, 60-GHz, or even higher frequency. Together with the capability of high-level integration, nanometer CMOS are good candidates to realize high-frequency wireless systems. It has been also demonstrated that CMOS offers great potential to achieve high performance, small chip area, low cost, low power dissipation, and long battery life-time for implementing potable devices. Table 1.1 shows the pros and cons of different technologies which are used for the implementation of wireless systems.
Furthermore, higher quality factor of passive components, like transmission lines and inductors, have been achieved by the thicker metal in the highest metallization layers in the modern RF-CMOS processes, by the micro-electro-mechanical system (MEMS) technol-ogy [112]–[115], or even by the gradually developed and matured wafer-level packaging (WLP) technologies [116]–[119].
The development of modern integration technologies is normally driven by the needs of digital CMOS circuit design. The reduction in physical dimensions of the transistors must be accompanied by a proportional reduction in the width of the depletion regions inside the transistor to maintain its basic operation. This can be achieved by an overall increase in the doping concentration of the transistors. However, the higher doping levels increase the electric field inside the transistors and reduce the breakdown voltage of the transistors. Thereby, lower voltage swings and supply voltages are necessary [120]. As
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shown in Fig. 1.9, the supply voltage of CMOS decreases rapidly as the sizes of devices shrinks [111]. The supply voltage is 1.8 V for 0.18-µm CMOS. It becomes 1.2 V for 0.13-µm and 90-nm CMOS. In the 65nm/45nm CMOS, the supply voltage becomes 1 V approximately. Although decreased supply voltages do not restrict the design of dig-ital circuits, this brings the difficulties for designing analog and RF circuits in modern sub-micron CMOS process with low supply voltage. This situation would become worse and worse as CMOS technologies continue to scale down [121]. These issues impose significant challenge in terms of circuit design for analog and RF front-ends. Conse-quently, there is a growing need to explore new low-voltage analog and RF circuit design techniques to overcome afore-mentioned limitations. The current-mode circuit design technique is proposed as one of the promising techniques [121]–[125].
1.2
Review on RF Transceiver Architectures
1.2.1
Receiver Architectures
1) Heterodyne or IF Receivers
The most straightforward receiver architecture for implementing a cellular receiver front-end is evidently the heterodyne receiver [2]–[4], [24], [25], [31], [34], [37], [41]–[43], [51], [57], [65], [69], [70], [72]. The system block diagram is illustrated in Fig. 1.10. The main feature is the use of an intermediate frequency (IF). For this reason, the heterodyne is often also called the IF receiver.
The received RF signals from the antenna are firstly filtered by a band select filter,
BP FRF1, which suppresses interferences residing outside of the application band. By
removing these out-of-band blocking signals which could saturate the following stages, the required dynamic range of the receiver can be relaxed considerably. A LNA ampli-fies the received RF signals which are then filtered by an image-reject filter, BP FRF2, to
remove the image. The image has an offset of twice the intermediate frequency by the mixer. The received RF signals after BP FRF2 are converted to IF by the
down-conversion mixer, and then passed through the channel-select filter BP FIF to remove the interferences at the adjacent channels. Finally, the channel-selected signal is demodulated
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1.2. REVIEW ON RF TRANSCEIVER ARCHITECTURES 13
90 0 LNA BPFRF1 BPFRF2 MIXERRF BPFIF LPFBB VCOIF MIXERIF VCORF I-Path Q-Path ... ... ... image RF RF image IF BB ~~ ~~ ~~ ADC ADC
Figure 1.10 Block diagram of the heterodyne or IF receiver.
into baseband I/Q signals to retrieve the desired signal information. The high-frequency noise and distortion from intermodulation and high-order harmonics are removed by the baseband low-pass filter LP FBB.
In the frequency translation, both the desired signal and image signal are mapped to the IF frequency after mixing. Although the image-reject filter BP FRF2 is used to attenuate
the image signal, suitable attenuation of the image may not be practical unless the IF frequency is selected relatively high. The trade-off is that filtering at a high IF requires more complicated filters in order to maintain selectivity. It is difficult to realize an on-chip high-Q filter at the RF frequency. The required high-Q high frequency image-reject filter is therefore placed off-chip. Consequently, the integration ability of the heterodyne or IF receiver is limited, and the cost is increased because of several off-chip filters are needed. Additional buffers to drive off-chip filters also require high power and reduce the gain of this kind of receivers.
The path mismatch is not a big issue because the image rejection does not rely on any matching between two signal paths, but is mainly achieved by the image-reject filter. Also LO feed-through and DC offset do not affect the signal quality since the desired signal frequency is never close to these frequencies. The same applies to the self-mixing of either
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RF or LO signal. Another important property is that the channel selection occurs before the ADC. Hence, the ADC only requires to handle minimum dynamic range. Due to the bandpass nature of the channel, even the sub-sampling ADC can be used. Additionally, the number of bits can be kept low since both the out-of-band and in-band blocking signals have already been removed.
Regarding the integration capability, it is clear that the heterodyne or IF receiver is not a good solution because this topology probably never get rid of the external high-Q filters. Hence, a sense of realizing a full CMOS implementation to achieve low cost is raised. Furthermore, such kinds of receiver do not effectively exploit the power of digital signal processing which is the core competence of CMOS.
2) Direct-Conversion (Homodyne, Zero-IF) Receiver
The direct-conversion (homodyne, zero-IF) receiver (DCR) has the advantage of high integration capability [7], [10]–[13], [15], [16], [21]–[23], [26], [32], [33], [35], [39], [40], [44]–[49], [52]–[56], [68], [71]. As shown in Fig. 1.11, both BP FRF2and IF components
are not required in the DCR, and this helps for the integration. The desired RF signal is directly down-converted to zero-IF in one-step frequency mixing with single LO signal. Therefore, in this type of the receiver, the LO frequency is nearly equal to the RF fre-quency. The baseband signal is then filtered with a low-pass filter to select the desired channel.
For frequency- and phase-modulated signals, the down-conversion must provide quadra-ture outputs to avoid the loss of signal information. The main advantage of DCR is that it does not possess the image problem when the incoming RF signal is directly down-converted to baseband without any IF stage. Another advantage is its simple architecture. However, the major disadvantage is DC offsets. As shown in Fig. 1.12, the severe DC offsets can be generated at the output of the mixer when the leakage from the local os-cillator V CORF is self-mixed with LO signal. The second source of DC offsets is the large nearby interferers leaking to the V CORF and then self-mixing. The generated DC offsets could saturate the following stage. The DC offsets can be removed by capacitive coupling. However, the signal power near DC could be lost. Hence, the size of capacitors should be chosen quite large. Feedback loops from the baseband or the digital part are
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90 0 LNA LPFBB VCORF MIXERRF I-Path Q-Path ... image RF BB ~~ BPFRF ADC ADC
Figure 1.11 Block diagram of the homodyne, direct-conversion, or zero-IF receiver.
also proposed to reduce the DC offsets. But these methods increase the complexity of the DCR.
Equally critical is the flicker noise of the mixer since the mixer output is the baseband signal and can be easily corrupted by large noise. It is because that the flicker noise of active devices becomes the dominant noise source as the frequency below 1 MHz. The flicker noise should be considered in designing DCR. Active devices with large dimension can be chosen to reduce flicker noise. In addition, PMOS contributes less flicker noise than NMOS.
So far, some 24-GHz CMOS receiver front-ends have been proposed in [51]–[57],[65]. Among them, [51], [57], [65] adopts the heterodyne receiver architectures. The RF sig-nal at 24 GHz is down-converted to the IF frequency of around 5 GHz in [51], [57]. In [52]–[56], the direct-conversion receiver architecture has been adopted. In [52], [53], sub-harmonic mixers are adopted to overcome the design issues of dc offsets from self-mixing in the conventional direct-conversion receiver. Moreover, this mixer topology does not consume any dc power and, hence, is ideally avoid of 1/f noise. In addition, it does not have any dc offset under ideal conditions owing to its subharmonic mixing func-tion. In [55], the direct-conversion receiver adopts the phased-array receiver architecture
A 1896 E S LNA VCORF MIXERRF LNA VCORF MIXERRF
Figure 1.12 Two sources of DC offsets in the direct-conversion receiver.
in its RF domain. After the 4 channels are combined, the RF signal is directly down-converted to the baseband. The phased-array systems have the advantage of improved spatial selectivity and spectral efficiency. These systems are good solution for broadband communications.
1.2.2
Transmitter Architectures
1) Direct-Conversion Transmitter
The direct-conversion transmitter, shown in Fig. 1.13, is attractive because of its sim-plicity of the signal path [2], [4], [13], [16], [17], [21], [22], [28], [29], [32], [33], [35], [37], [39], [41], [44]–[46], [48], [49], [62]. The IF signals are modulated and up-converted to RF in a single step by the quadrature modulator. The RF signal then amplified by the following PA. After the PA, the bandpass filter BP FRF is typically needed to meet the spectral mask requirements. A single RF frequency synthesizer provides the LO signal and performs channel selection.
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1.2. REVIEW ON RF TRANSCEIVER ARCHITECTURES 17
I-Path Q-Path 90 0 LPFBB MIXERRF DAC DAC VCORF BPFRF PA BB RF freq desired band direct-conversion no image signal
Figure 1.13 Block diagram of the direct-conversion transmitter.
The performance of a direct-conversion transmitter is typically limited by two factors. Firstly, this architecture requires quadrature LO signals like all quadrature modulators. Quadrature generator at RF frequency is less accurate than at lower frequency. Hence, the modulation accuracy of the direct-conversion transmitter is reduced by this effect. The other limitation to the performance of direct-conversion transmitter involves the inter-modulation in the PA. When the baseband signals mixed with the LO signals, harmonics of the LO are generated. These harmonics are inherent to switching mixers. The har-monics generate copies of the baseband signals which intermodulate in the PA and reduce the modulation accuracy. The phenomenon is shown in Fig. 1.14. The spectrum before the non-linear PA includes the desired signal located at the sum of the LO and baseband frequencies, and an undesired signal located at one baseband frequency below the third harmonic of the LO frequency. The third-order intermodulation of two tones f1 and f2
results in new tones located at (2f2 − f1) and (2f1 − f2). In this case, the distortion
component closed to the RF output is given by
(3fLO− fBB) − 2 (fLO+ fBB)= (fLO −3fBB) (1.1) where fLOis the frequency of LO signal and fBBis the frequency of baseband signal. This distortion component, located three baseband frequency below the LO frequency, could
A 1896 E S 90 0 LO I-Path Q-Path Non-linear PA ~~
LO+BB 3LO−BB freq LO−3BB LO+BB
third-order intermodulation (3LO − BB) − 2(LO + BB)
freq
VCORF
Figure 1.14 Third-order intermodulation by a non-linear PA in a direct-conversion trans-mitter.
lead to modulation error and spectra mask violations. As a result, the filter before the PA is often needed to attenuate the signals before intermodulation occurs in the PA. However, the need for this filter often requires a discrete component and is thus not amenable to a single chip integration solution.
Because the RF frequency is the same as LO frequency in direct-conversion transmit-ter, another potential problem for this architectures is the LO Pulling which is illustrated in Fig. 1.15. Although the simplicity of direct-conversion transmitter is attractive for inte-gration, all circuit blocks are located on the same substrate and it is a very challenge task to achieve sufficiently high isolation, especially for the on-chip PA. The large modulated signals after the output of PA could interfere with other sensitive analog circuits by cou-pling through the silicon substrate. A particular problem occurs when the PA as well as VCO runs at a frequency close to each other.
One method to reduce LO Pulling involves using two oscillators and mixing them to create the LO signal. In doing so, the frequency of the LO is moved away from the fre-quency of the PA output and thus reduce the LO Pulling. However, additional harmonics
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90 0 LO I-Path Q-Path Non-linear PA VCORF LO Pulling
Figure 1.15 LO Pulling in a direct-conversion transmitter.
are generated with this technique that either needs to be filtered or the performance may suffer. The second technique is used in which the output of the VCO is divided and then mixed to create the LO signal. Again, the frequency of LO is changed to reduce the LO Pulling. Yet another method employs multiple phases of LO at lower frequency to perform up-conversion. This method can avoid the LO frequency near the transmitted frequency. Although all of the above mentioned solutions decrease the impact of LO Pulling, they increase the complexity of the transmitter, and thus may diminish the attractive structure simplicity of the direct-conversion transmitter.
In addition to the afore-mentioned issues, other potential issues include the difficulty of power control and the LO feed-through. Because there is no IF stage, all the power control should be performed at baseband or RF. Baseband power control could suffer from very strict linearity requirements on the baseband circuits. Coupling between the LO signal to the RF output is another potential problem due to the high frequency LO used in the quadrature modulator. Although the direct-conversion transmitter has a vey simple circuit and potentially offers for the multi-standard operation, a number of limitations exist. Some of these problems can be alleviated by using heterodyne transmitter with two-step frequency conversion which will be reviewed in the next section.
A 1896 E S I-Path Q-Path 90 0 LPFBB MIXERIF DAC DAC VCOIF BPFIF MIXERRF VCORF BPFRF1 PA BPFRF2 BB IF freq desired band LO1 LO2 image signal IF
Figure 1.16 Block diagram of the two-step heterodyne transmitter.
II. Heterodyne Transmitter
The heterodyne transmitter which performs two-step up-conversion is widely used topology [24], [25], [31], [34], [37], [42], [43], [58]–[61], [66], [67], [69]. The heterodyne architecture, depicted in Fig. 1.16, uses a quadrature modulator to frequency translate the baseband signal to IF. At this point, an IF bandpass filter BP FIF is needed to suppress the harmonics created by MIXERIF. IF signal is then up-converted to RF where the RF bandpass filter BP FRF1 is needed to remove the image created by the MIXERRF. Finally, the RF signal is applied to the PA and is typically filtered again by BP FRF2 to
meet the spectral mask requirements. These filters, BP FIF, BP FRF1, and BP FRF2, are
typically discrete components that are not amenable to integration on a single CMOS substrate.
The heterodyne transmitter has a number of performance advantages over direct-conversion approach. It avoids the LO Pulling problem since the up-direct-conversion is per-formed in two steps, and therefore neither LO is operating at the transmitted frequency. The modulation accuracy in the quadrature modulator is improved since low-frequency quadrature VCO allows for more accurate quadrature generation. In addition, lower
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quency of the LO leads to less LO feed-through at the RF output. The issue of third-order intermodulation is also alleviated because the undesired distortion component near 3(fLO1+ fLO2) is attenuated by the bandpass RF filter BP FRF1. The filter requirements
can be relaxed by an optimizing frequency mapping. The demands of BP FIF can be re-laxed if the IF is chosen in a way that none of the harmonics fall directly in the transmit band. Further, a higher IF will push the image sideband far away from the RF which results in a better image rejection by BP FRF1.
Although the heterodyne transmitter shows promise for higher performance, this struc-ture does have some drawbacks with respect to single-chip integration which may be the advantage of direct-conversion transmitter. This architecture is well suited for multi-standard operation, since heterodyne transmitters are capable of both constant envelop and non-constant envelop modulation schemes. Meanwhile, the heterodyne transmitter is a versatile architecture that allows a large gain control range because the amplification can be distributed to several stages. Hence, if the limitations to integration can be overcome, heterodyne transmitter is a good choice when the target is multi-standard operation on a single CMOS substrate.
Although the direct-conversion transmitter suffers from LO Pulling, LO feed-through, and lower accurate quadrature LO signals, direct-conversion architecture still exhibits sev-eral advantages of low power consumption, high integration ability, and low cost. Re-cently, there has been increasing research interests and efforts on the design of CMOS direct-conversion transmitter.
So far, some CMOS transmitter front-ends operated around 20 GHz have been pro-posed [58]–[64], [66], [67]. Among them, the direct-conversion configuration has been adopted in [62] for the consideration of low-power consumption. The dual-conversion transmitter is the most popular configuration and has been adopted in [58]–[61],[66],[67]. For the application of general purpose, [58]–[62], [67] have proposed CMOS transmit-ters in 24-GHz ISM band, where on-chip dipole antenna has been integrated in [61] to avoids high frequency wired I/O, thus eliminating the losses associated with RF chip-to-PC-board and transmission line connections. [66] has proposed a CMOS transmitter in 17-GHz ISM band. In [63], [64], the 24-GHz CMOS transmitter has been designed for automotive short-range radar (SRR) applications.
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1.3
Review on CMOS RF Building Blocks
1.3.1
Voltage-Mode Down-Conversion Mixer
Down-conversion mixers are required for the frequency conversion in wireless com-munication systems, especially in the receiver front-ends [126]. In the past, due to the limited speed of MOSFETs and the low quality factor of the passive devices, the use of CMOS technology is restricted to relatively low operation frequencies. The down-conversion mixers operated above 20 GHz have been mostly implemented by GsAs-based HEMT, HBT, and SiGe/BiCMOS processes. Nevertheless, over the last years, the speed gap of CMOS devices to III/V and SiGe technologies has been significantly decreased by aggressive scaling of the transistors [111]. This has made it possible to design the down-conversion mixers operated above 20 GHz with the advanced nanometer CMOS devices.
So far, some down-conversion mixers have been proposed to investigate the operation feasibility at around 20 GHz [51]–[54],[56],[57],[65],[68],[70],[71],[127]–[132]. Among them, the Gilbert mixer has been adopted in [51],[54],[56],[57],[65],[68],[70],[71],[127]. The current-bleeding technique has been applied to the Gilbert mixers to achieve higher conversion gain [56], [71]. With current-bleeding method, the switching transistors can be operated at lower gate-to-source voltage with smaller size.
In addition to the Gilbert mixers, sub-harmonic mixers (SHMs) have also been in-vestigated in the operating frequency around 20 GHz [52], [53], [128]–[132]. The burden of designing a LO at high frequencies can be alleviated by the SHM topology. Because the LO frequency is a sub-harmonic of the RF frequency, this alleviates the DC-offset due to the LO–RF feedthrough. Furthermore, the Gilbert mixer requires high dc power consumption for the specific conversion gain and speed. Therefore, the passive SHM without dc power consumption becomes an attractive candidate for high frequency appli-cations. There are mainly two different techniques which are known for sub-harmonic down-conversion mixers: 1) exploiting the non-linear behavior of active devices to pro-duce higher harmonics of the LO waveform [131], [132] and 2) multiplying the received signal with a number of uniformly spaced LO phase [52], [53], [128]–[130]. While the type 1) mixers have a penalty in conversion gain and noise, the type 2) mixers have
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formance similar to the Gilbert mixers at the expense of a more complex LO generation circuits.
1.3.2
Voltage-Mode Up-Conversion Mixer
As down-conversion mixers which are described in the prior paragraph, up-conversion mixers are required for the frequency conversion in wireless communication systems, especially in the transmitter front-ends [126]. The up-conversion mixers operated above 20 GHz have been mostly implemented by GsAs-based HEMT, HBT, and SiGe/BiCMOS processes. Nevertheless, over the last decade, the significant improvement of CMOS devices into nanometer nodes has made the speed of the CMOS devices comparable to the devices in SiGe/BiCMOS and III-V technologies [111]. This has made it possible to design the up-conversion mixers operated above 20 GHz with the advanced nanometer CMOS processes.
So far, little has been done to investigate the feasibility of implementing CMOS up-conversion mixers for such a frequency range around 20 GHz [58]–[61], [66], [67], [133], [134]. Among them, the CMOS Gilbert mixer has been adopted in [58]–[60], [66], [67], [134]. In the Gilbert mixer, the LO signal at the drain of differential pairs is ideally zero, and the mixing is caused by the switching action of LO switching transistors between the cutoff and saturation region. Hence, the switching behavior of the LO switching transistors is quite important. To minimize the period of LO switching transistors into linear region, the current-bleeding technique can be used to enhance the switching speed. In [58]–[60], [67], the current-bleeding technique has been applied to the up-conversion Gilbert mixer to enhance the conversion gain and make the switching transistors operate faster with lower gate-to-source voltages and smaller sizes.
The input of the Gilbert mixer is actually a voltage-to-current stage. While the non-linearity in the switching operation is necessary for frequency translation, a distortion of the drain current caused by the transconductance stage is highly unwanted. This distor-tion deteriorates the compression and intermoduladistor-tion characteristic of the up-conversion Gilbert mixer. The transconductance stage in [66] is with resistive source degeneration to enhance its linearity performance.
