Current-Mode Up-Conversion Mixer

The core of the proposed current-mode double-balanced up-conversion mixer is com-posed of four analog current-squaring circuits, as shown in Fig. 3.10, which are originally modified from [161], [162]. The transistors M₁–M₄ are biased in the saturation region.

The bulk and source of M₂ and M₄ are separated to reduce the parasitic capacitances at the nodes N₁and N₂. Lower signal loss is achieved due to smaller parasitic capacitances appeared at nodes N₁and N₂. With the resistor R₁ (R₂), the impedance of the path from the node N₁ (N₂) to ground through the source-to-bulk parasitic capacitance of M₂ (M₄) is increased. Hence, the signal loss to ground is further reduced.

The current-squaring circuit is further improved by adding the transistor M₄ which acts as a current buffer and keeps the VDS of M₃ the same as the VDS of M₁ in order to alleviate the channel length modulation effect between M1 and M3. The current i1 is multiplied by the current-mirror circuit formed by M₁and M₃, where the aspect ratio of M₃(M₄) is N times that of M₁ (M₂). The sum of the gate-to-source voltages of M₁and M₂is kept constant and equal to VDD, where VDD = (vGS,M1 + vGS,M2). Suppose that the respective threshold voltages of M₁ and M₂ are (Vth − ∆V_{T H}) and (Vth+ ∆V^{T H}) where V_th = (Vth,M₁ + Vth,M₂)/2 and ∆VT H = (Vth,M₂ − V_th,M1)/2, and based on the square-law drain current equation for simplicity, the relationship among iin, iO, vGS,M1, and vGS,M2 is

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IF Current Buffer/RepeaterCurrent-Mode Upconversion Mixer Transformer-Based VCO Buffer/RepeaterVCO

Power Amplifier

Single-ended IF input Off-Chip Transformer Differential LO

iif+,1 iif-,1iif+,2 iif-,2

lo+ i

,1 lo-, i

1 ^{,2 lo+} i

lo-, i

2

i

if+

i

if- v lo+ v lo-

lo-i

rf This Design

i

if

Figure 3.9 Block diagram of the proposed current-mode transmitter front-end.

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3.3. CIRCUIT DESIGNS 79

V

_DD

M

₂

M

₄

N

₂

N

₁

R

₁

R

₂

i in

i 1

i 2

i O

M

₁

M

₃

+

−

v

GS M, 2

− +

, 1

v

GS M

Figure 3.10 Circuit diagram of current-squaring circuit.

A

where Vth is the threshold voltage, W /L is the channel width to channel length ratio of the MOS devices, and k_n = µnC_ox is the zero vertical-field mobility µ_n multiplied by the oxide capacitance per unit area Cox. From the first term of (3.9), the current-squaring function is realized. The second and third terms of (3.9) are unwanted components and are to be removed. With the input iin = ILOcosωLOt+ IIFcosωIFt, the output iO of the proposed square circuits can be derived as

iO = N ×

Shown in Fig. 3.11 is the proposed current-mode double-balanced up-conversion mixer which consists of four current-squaring circuits and an on-chip octagonal transformer.

Four signal inputs of this mixer are iin1= (ilo+,1+iif+,1), iin2 = (ilo−,1+iif −,1), iin3 = (ilo+,2+ i_{if −,2}), and i_in4 = (ilo−,2+ i^if+,2). iif+,1, i_{if −,1}, iif+,2, and i_{if −,2}are two-pair IF current sig-nals where iif+,1 = iif+,2 = iif+ = IIFcosωIFtand i_{if −,1} = iif −,2 = iif − = −IIFcosωIFt.

Furthermore, ilo+,1, ilo−,1, ilo+,2and ilo−,2are two-pair differential LO current signals where ilo+,1 = i^lo+,2 = i^lo+ = I^LOcosωLOtand i_lo−,1 = ilo−,2 = i^lo− = −I^LOcosωLOt. The summa-tion of IF and LO current signals is performed by directly connecting the wires of LO and IF together without additional power dissipations.

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3.3. CIRCUIT DESIGNS 81

Current-Squaring Circuit Current-Squaring Circuit Current-Squaring Circuit

V

DD

M

1

M

3

M

2

M

4

N

2

N

1

R

1

R

2

in

i

1

i

2

i

Current-Squaring Circuit

O

i ( )

1,1,1inloif

ii i

++

=+ ( )

2,1,1inloif

ii i

−−

=+ ( )

3,2,2inloif

ii i

+−

=+ ( )

4,2,2inloif

ii i

−+

=+ V

DD OM

i

OP

i

C

2

C

1

V

T1

XFMR

1

L

1

C

3

C

PAD

RF

OUT4O

i

3O

i

2O

i

1O

i

Tuned Load & Output Matching Network

Figure 3.11 Circuit diagram of current-mode double-balanced up-conversion mixer.

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As shown in (3.12)–(3.18), with the differential LO and IF signals, the LO and IF leakages which result from the second term of (3.9) can be eliminated at the output of the proposed current-mode mixer if the output currents i_O1 i_O4 of the four current-squaring circuits are summed together as iOP = (iO1+ iO2) and iOM = (iO3+ iO4). The summations of these current signals are performed using wire connections. In addition, as shown in (3.19), the even-order harmonics resulted from squaring terms of LO and IF current signals are eliminated through the subtraction of iOP and iOM.

i_in1 = (ILOcosωLOt+ IIFcosωIFt) (3.12)

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3.3. CIRCUIT DESIGNS 83

IDC = N × Some circuits that deal with current subtraction have already been reported in [162]

and [167]. As shown in Fig. 3.12(a) [162], the current-mirror circuit is adopted to deal with subtraction of current signals. The two current signals Ia and Ibthat are to be sub-tracted flows through two imbalanced paths. The two imbalanced paths will result in gain and phase differences. Additional poles from the current mirror will lead to loss of current signals in high frequency. Furthermore, higher voltage headroom and additional power are required for this subtraction circuit of current signals. As shown in Fig. 3.12(b) [167], another subtraction circuit of current signals by LC phase-shift network is adopted. This circuit can perform good subtraction, but only at the resonant frequency. No additional power consumption is required, and this circuit avoids excessive voltage drop. When deal-ing with signals with wide bandwidth, the LC phase-shift network will not be suitable.

In this design shown in Fig. 3.11, the on-chip passive transformer XF MR₁is adopted for high-frequency and wide-bandwidth subtraction of current signals. The use of XF MR₁ avoids the excessive voltage drop, and no additional power consumption is required. This also ensures that the proposed current-mode double-balanced up-conversion mixer oper-ates well at a low power supply. From (3.9) and with the four inputs of the mixer, the resultant RF output current irf = η × (iOP − i_OM) can be derived as

i_rf = ηNI_LOI_IF 4IB

[cos(ωLO+ ωIF)t+ cos(ωLO− ω_IF)t] (3.20) where η represents the losses from the on-chip transformer XF MR₁ and the output impedance matching network. From (3.20), it can be seen that the function of mixer is realized. With the exclusion of the loss η, the intrinsic current conversion gain CGintrinsic

of the proposed current-mode double-balanced up-conversion mixer is expressed as CG_intrinsic ≈ (iOP − i_OM) |ω=(ωLO+ωIF)orω=(ωLO−ω_IF)

2(iif₊− i_if−) |ω=ωIF

= NI_LO 16IB

(3.21)

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V_DD

M_S1

M_S2 M_S3

M_S4

M_S5

M_S6 M_S7

M_S8

M_S9

M_S10

M_S11

M_S12

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