Wafer-Level Packaging (WLP) Technology [116]–[119]

High-Q integrated inductors are important components for modern RFICs. Neverthe-less, on-chip RF inductors have fairly low-Q factors due to the relatively thin-metal layers and the close proximity to the lossy silicon substrate. The performance of the inductor can be improved by using low-k materials and thick Cu metallization. However, thick Cu is usually not a standard backend-of-line (BEOL) process, and the dielectric in between inductor and lossy silicon substrate is still relatively thin. Alternative reported options such as micromachining techniques to remove the lossy substrate underneath the spiral inductor in a post-processed step, or to create an air gap in between spiral inductor and substrate using suspended on-chip MEMS inductors [115] are mechanically less stable and are not preferred for subsequent packaging process.

In the past, IMEC provides a more attractive and cost-effective solution to realize the above-IC inductors using thin-film wafer-level packaging (WLP) techniques [116]–[119].

The inductors are realized above the passivation by using thin-film post-processing tech-niques. Thin-film technology offers the advantage of high precision, low temperature, and low cost. When applied above IC, thin-film WLP technology offers novel opportu-nities to the functionality of ICs, besides the redistribution of bonding pads, as the added metallization may be used for the integration of high-Q on-chip inductors and low-loss in-terconnects. Furthermore, IMEC has demonstrated that a measured Q-factor above 40 at 4.7 GHz for a 1.8 nH inductor with a resonance frequency of 28 GHz. The ultra low-loss transmission lines with insertion loss lower than 0.3 dB/mm at 100 GHz has also been proposed in the thin-film WLP technology.

The WLP technology is performed on top of IMEC’s 45-nm RF CMOS process where a p-type 20-Ω· cm Si substrate with a five levels of metal Cu/oxide BEOL is used. The BEOL Cu layer (Metal-1 to Metal-5, with Metal-5 being the top metal layer) has a thick-ness of 625 nm, and an inter-metal level dielectric of 475 nm. Thereby, a space between the passivation and the substrate is about 6.1 µm. The high-Q above-IC inductors and mi-crostrip lines by WLP technology, which consists of a 5-µm thick electroplated Cu layer of WLP-M1 on an 18-µm low-k dielectric (k = 2.65) of Benzo-Cyclo-Buthene (BCB), are realized and post-processed above the BEOL passivation. Overpasses are realized in

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4.1. 45-NM CMOS TECHNOLOGY AND WAFER-LEVEL PACKAGING (WLP) 119

WLP-M2 (2-µm Cu, 3-µm Ni/Au) and separated from WLP-M1 by 8-µm thick BCB-2.

Fig. 4.5(a) [118] illustrates the schematic cross-section view of the ”inductor above pas-sivation” concept. Fig. 4.5(b) [118] illustrates the SEM cross-section view of the stack of WLP-M1 and WLP-M2 on top of Metal-1–Metal-5, with high aspect ratio HARVi and conventional via. Processing masks for the WLP are very cheap compared to masks used for metal layers in the standard BEOL interconnect structure. The thick BCB layers lower the parasitic capacitance to the silicon substrate, hereby increasing the inductor resonance frequency. In addition, thick Cu yields low series resistance.

Fig. 4.6 [118] shows a 1.8-nH post-processed symmetrical inductor with and without patterned poly-silicon ground shield. Fig. 4.7 [118] shows the de-embedded measurement and simulation results of a 1.8-nH thin-film post-processed inductor without patterned poly-silicon ground shield, as well as the factor for single-ended (SE) and differential (DIFF) application. A 1.8-nH symmetrical inductor (without ground shield) has a dif-ferential Q-factor of 40 at 5 GHz and a single-ended Q-factor of 32 at 3 GHz. When a front-end-of-line (FEOL) is present, a patterned poly-silicon ground shield will terminate the inductor’s electric field before reaching the silicon substrate, hereby reducing the sub-strate losses, such that the Q-factor increase. As shown in Fig. 4.8 [118], Q-factors of the 1.8-nH symmetrical inductor with and without patterned poly-silicon ground shield are compared. With the shield, the differential Q-factor can reach 47 around 9 GHz with a resonance frequency of 25 GHz. Also, it is above 30 from 2.8 GHz to 18 GHz, which guarantees a good performance in a wide frequency range. The differential quality factor Q_{DIF F} and single-ended quality factor QSE are defined as [187]

Q_{DIF F} ≡ ={Z₁₁− Z₁₂− Z₂₁+ Z22}

<{Z₁₁− Z₁₂− Z₂₁+ Z22} (4.1) QSE ≡ −={Y₁₁}

<{Y₁₁} (4.2)

where Z₁₁, Z₁₂, Z₂₁ and Z₂₂ are the Z-parameters of the two-port network of inductor, and Y₁₁, Y₁₂, Y₂₁and Y₂₂are the Y-parameters of the two-port network of inductor.

The characteristic impedance of the transmission line in WLP process has been ex-tracted through HFSS simulation. The design parameters have been shown in Table 5.1.

Moreover, the parameters of the equivalent RLGC model of the designed transmission line in WLP process have been shown in Table 5.2.

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(b)

Figure 4.5 The IMEC WLP technology. (a) Schematic cross section of the ¨above IC¨layers. (b) SEM cross section of WLP-M1 and WLP-M2 on top of M1-M5 metal lev-els: conventional via (through BCB-2) and high aspect ratio via (HARVi) through BCB-1 [118].

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Figure 4.6 Microphotograph of a 1.8-nH thin-film post-processed symmetrical inductor, including the pad connections for wafer probing. The left inductor is without patterned poly-silicon ground shield, and the right inductor is with patterned poly-silicon ground shield. The inductor has two turns (N ), an inner radius of 125 µm (Rin), 10-µm metal spacing (S), and a metal trace width (W ) of 30 µm [118].

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Figure 4.7 Measurement (solid line) and simulation result (dashed line) of the series inductance and the Q factor of thin-film post-processed inductor with a designed induc-tance of 1.8 nH, both for single-ended (QSE) and differential (QDIF F) applications. The inductor has no patterned poly-silicon ground shield: N = 24, S = 10µm, W = 30µm, and Rin = 125µm [118].

Figure 4.8 The measured quality factor of single-ended QSE and differential QDIF F

applications of two-turn symmetrical thin-film post-processed 1.8-nH inductors with and without a patterned poly-silicon ground shield: N = 2, S = 10µm, W = 30µm, and R_in= 125µm [118].

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Table 4.1

CHARACTERISTICIMPEDANCE OFTHE TRANSMISSIONLINEEXTRACTED

FROM HFSS

ZC (Ω)

TL layer Shielding layer TL width (µm) 10 GHz 24 GHz 60 GHz

M1-to-M5 35 51.5 51.2 51

10 89.9 89.3 88.9

20 72.4 71.9 71.7

35 56.2 55.8 55.7

40 52.6 52.3 52.2

WLP-M1 M1-to-M2 41 52 51.8 51.6

43 50.6 50.3 50.2

45 49.2 48.9 48.8

60 41.6 41.4 41.4

80 34.5 34.4 34.3

5 50.4 48.4 47.1

M5 M1-to-M2 10 33.2 32 31.1

20 20.4 19.6 19

4.2 Circuit Designs

The CMOS technology is especially attractive for its potential of integration of RF, IF and baseband DSP functions, enabling true systems-on-chip. As CMOS technology is scaled into deca-nanometer range, the transistor ID− V_GScharacteristics in the saturation region become linear while the transconductance, minimum noise figure (NF_MIN), f_T, and fMAXimprove. Additionally, when biased the MOS transistor at the current densities between 0.15 mA/µm and 0.4 mA/µm, these figures of merits become almost insensitive to the variations of ID and VGS. The application of constant-field scaling rules to every new generation of CMOS since the 0.5-µm node has resulted in constant peak fT and f_MAX current densities of 0.3 – 0.35 mA/µm and 0.2 mA/µm, respectively [187]–[193].

This is in contrast to SiGe HBTs where the peak fT and fMAX current bias is technology dependent. The peak fT current density remains constant for different finger widths and for both the common source and cascode configurations. The minimum noise figure bias of MOSFET is JOP T = 0.15mA/µm, irrespective of frequency and technology nodes.

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Table4.2 EQUIVALENTRLGCMODELPARAMETERSFROMHFSS TLlayerShieldinglayerTLwidth<{ZC}={ZC}<{Γ}={Γ}RLGC ––[µm][Ω][Ω][Np/m][Rad/m][Ω/m](H/m)(S/m)(F/m) M1-to-M53551.1–0.6310.35774.51014.62.6×10−7 0.01710.0×10−11 1089.3–1.1911.05778.919104.6×10−7 0.0085.6×10−11 2071.9–0.839.79780.91350.23.7×10−7 0.0117.2×10−11 3555.9–0.609.21782.8985.22.9×10−7 0.0149.3×10−11 4052.3–0.549.05785.2900.52.7×10−7 0.01710.0×10−11 WLP-M1M1-to-M24151.7–0.569.25785.6918.32.7×10−7 0.01410.1×10−11 4350.3–0.539.05785.9868.12.6×10−7 0.01710.4×10−11 4548.9–0.529.10786.4854.82.6×10−7 0.01510.7×10−11 6041.3–0.428.91789.5700.72.2×10−7 0.02112.7×10−11 8034.3–0.348.82793.1571.71.8×10−7 0.02915.3×10−11 548.4–3.1366.161035.36439.23.3×10−7 –0.01814.2×10−11 M5M1-to-M21032.1–2.0264.8410414186.62.2×10−7 –0.02721.5×10−11 2019.6–1.2967.251051.326711.4×10−7 –0.08435.5×10−11

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4.2. CIRCUIT DESIGNS 125

This current density is very close to the peak fMAX current density of 0.2 mA/µm and there is practically no degradation of power gain when MOSFET is biased for optimum noise.

In this IMEC 45-nm planar bulk-CMOS technology, the transistor has been demon-strated that fT is around 300 GHz with the achievable transconductance efficiency g^m/ID

of 2.5V⁻¹. In the back-end process, this 45-nm bulk-CMOS technology offers five layers of metal in the damascene process and metal-insulator-metal (MIM) capacitor.