Receiver Architectures

1) Heterodyne or IF Receivers

The most straightforward receiver architecture for implementing a cellular receiver front-end is evidently the heterodyne receiver [2]–[4], [24], [25], [31], [34], [37], [41]–[43], [51], [57], [65], [69], [70], [72]. The system block diagram is illustrated in Fig. 1.10. The main feature is the use of an intermediate frequency (IF). For this reason, the heterodyne is often also called the IF receiver.

The received RF signals from the antenna are firstly filtered by a band select filter, BP F_RF1, which suppresses interferences residing outside of the application band. By removing these out-of-band blocking signals which could saturate the following stages, the required dynamic range of the receiver can be relaxed considerably. A LNA ampli-fies the received RF signals which are then filtered by an image-reject filter, BP FRF2, to remove the image. The image has an offset of twice the intermediate frequency by the mixer. The received RF signals after BP FRF2 are converted to IF by the down-conversion mixer, and then passed through the channel-select filter BP FIF to remove the interferences at the adjacent channels. Finally, the channel-selected signal is demodulated

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BPF_RF1 BPF_RF2 MIXER_RF BPF_IF

LPF_BB

Figure 1.10 Block diagram of the heterodyne or IF receiver.

into baseband I/Q signals to retrieve the desired signal information. The high-frequency noise and distortion from intermodulation and high-order harmonics are removed by the baseband low-pass filter LP FBB.

In the frequency translation, both the desired signal and image signal are mapped to the IF frequency after mixing. Although the image-reject filter BP F_RF2 is used to attenuate the image signal, suitable attenuation of the image may not be practical unless the IF frequency is selected relatively high. The trade-off is that filtering at a high IF requires more complicated filters in order to maintain selectivity. It is difficult to realize an on-chip high-Q filter at the RF frequency. The required high-Q high frequency image-reject filter is therefore placed off-chip. Consequently, the integration ability of the heterodyne or IF receiver is limited, and the cost is increased because of several off-chip filters are needed.

Additional buffers to drive off-chip filters also require high power and reduce the gain of this kind of receivers.

The path mismatch is not a big issue because the image rejection does not rely on any matching between two signal paths, but is mainly achieved by the image-reject filter. Also LO feed-through and DC offset do not affect the signal quality since the desired signal frequency is never close to these frequencies. The same applies to the self-mixing of either

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RF or LO signal. Another important property is that the channel selection occurs before the ADC. Hence, the ADC only requires to handle minimum dynamic range. Due to the bandpass nature of the channel, even the sub-sampling ADC can be used. Additionally, the number of bits can be kept low since both the out-of-band and in-band blocking signals have already been removed.

Regarding the integration capability, it is clear that the heterodyne or IF receiver is not a good solution because this topology probably never get rid of the external high-Q filters. Hence, a sense of realizing a full CMOS implementation to achieve low cost is raised. Furthermore, such kinds of receiver do not effectively exploit the power of digital signal processing which is the core competence of CMOS.

2) Direct-Conversion (Homodyne, Zero-IF) Receiver

The direct-conversion (homodyne, zero-IF) receiver (DCR) has the advantage of high integration capability [7], [10]–[13], [15], [16], [21]–[23], [26], [32], [33], [35], [39], [40], [44]–[49], [52]–[56], [68], [71]. As shown in Fig. 1.11, both BP FRF2and IF components are not required in the DCR, and this helps for the integration. The desired RF signal is directly down-converted to zero-IF in one-step frequency mixing with single LO signal.

Therefore, in this type of the receiver, the LO frequency is nearly equal to the RF fre-quency. The baseband signal is then filtered with a low-pass filter to select the desired channel.

For frequency- and phase-modulated signals, the down-conversion must provide quadra-ture outputs to avoid the loss of signal information. The main advantage of DCR is that it does not possess the image problem when the incoming RF signal is directly down-converted to baseband without any IF stage. Another advantage is its simple architecture.

However, the major disadvantage is DC offsets. As shown in Fig. 1.12, the severe DC offsets can be generated at the output of the mixer when the leakage from the local os-cillator V CORF is self-mixed with LO signal. The second source of DC offsets is the large nearby interferers leaking to the V CORF and then self-mixing. The generated DC offsets could saturate the following stage. The DC offsets can be removed by capacitive coupling. However, the signal power near DC could be lost. Hence, the size of capacitors should be chosen quite large. Feedback loops from the baseband or the digital part are

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Figure 1.11 Block diagram of the homodyne, direct-conversion, or zero-IF receiver.

also proposed to reduce the DC offsets. But these methods increase the complexity of the DCR.

Equally critical is the flicker noise of the mixer since the mixer output is the baseband signal and can be easily corrupted by large noise. It is because that the flicker noise of active devices becomes the dominant noise source as the frequency below 1 MHz. The flicker noise should be considered in designing DCR. Active devices with large dimension can be chosen to reduce flicker noise. In addition, PMOS contributes less flicker noise than NMOS.

So far, some 24-GHz CMOS receiver front-ends have been proposed in [51]–[57],[65].

Among them, [51], [57], [65] adopts the heterodyne receiver architectures. The RF sig-nal at 24 GHz is down-converted to the IF frequency of around 5 GHz in [51], [57].

In [52]–[56], the direct-conversion receiver architecture has been adopted. In [52], [53], sub-harmonic mixers are adopted to overcome the design issues of dc offsets from self-mixing in the conventional direct-conversion receiver. Moreover, this mixer topology does not consume any dc power and, hence, is ideally avoid of 1/f noise. In addition, it does not have any dc offset under ideal conditions owing to its subharmonic mixing func-tion. In [55], the direct-conversion receiver adopts the phased-array receiver architecture

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VCO_RF MIXER_RF

LNA

VCO_RF MIXER_RF

Figure 1.12 Two sources of DC offsets in the direct-conversion receiver.

in its RF domain. After the 4 channels are combined, the RF signal is directly down-converted to the baseband. The phased-array systems have the advantage of improved spatial selectivity and spectral efficiency. These systems are good solution for broadband communications.