Nanocrystal nonvolatile memories are one particular implementation of storing charge by dielectric surround nanodots, and were first introduced in the early 1990s by IBM researchers who proposed flash memory with a granular floating gate made from silicon nanocrystals [1.8]. The name nanocrystal referred to a crystalline structure with a nanoscale dimension. And its electric properties are more similar to an atom or molecule rather than the bulk crystal. Figure 1-4 shows the nanocrystal nonvolatile memory device structure. We can find out that the nanocrystals are separated with each other and embedded in the gate dielectric layer. In the nanocrystal nonvolatile memory device, the charges were charged in the isolated nanocrystals instead of the continuous FG polysilicon layer. Each nanodots will typically store only a handful of electrons;
collectively the charges stored in these dots control the channel conductivity of the memory transistor.
Nanocrystal NVM devices have been attracted a lot of attentions recently due to the potential to overcome the limitations of traditional FG NVM. Using the nanocrystal to store charge offers several advantages. The main one is the potential to use thinner tunnel oxide without sacrificing nonvolatility. This is quite attractive issue since reducing the tunnel oxide thickness is a main factor to lowering operating voltages and/or increasing
operating speed. This claim of improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effect of Coulomb blockade [1.22]. And the lateral charge migration phenomenon will be suppressed by the mutually isolated nanocrystals with each other. Quantum confinement effects (bandgap widening; energy quantization) can be exploited in sufficiently small nanocrystal geometries (sub-3nm dot diameter) to further enhance the memory performance. There are other important advantages for nanocrystal NVM device. First, the fabrication of the nanocrystal memories is more simplified and lower process cost as compared to the conventional FG memories. Second, due to the absence of drain to FG coupling, nanocrystal memories suffer less drain induced barrier lowering (DIBL) and therefore have intrinsically better punch-through characteristics. This advantage is gained a higher drain bias during the read operation, thus improving memory access time [1.23]. It allows using shorter channel lengths and therefore smaller cell area. Third, nanocrystal memories are characterized by excellent immunity to stress induced leakage current (SILC) and oxide defects due to the distributed nature of the charge storage in the nanocrystal layer. The other is low capacitive coupling between the external control gate and the nanocrystal charge storage layer. This does not only result in lower operating voltages, thus offsetting the benefits of the thinner tunnel oxide, it also removes an important design parameter (the coupling ratio) typically used to optimize the performance and reliability tradeoff.
The fabrication of a nonvolatile memory cell requires a perfect control of four parameters: (1) the thickness of tunnel oxide, (2) the density of nanocrystals, (3) the size of nanocrystals, and (4) the thickness of control oxide. An important issue of the nanocrystals memory is the average dot size and the nanocrystal density. Larger dot size provide faster program / erase speed due to smaller quantum confinement and coulomb blockade effects and hence better carrier tunneling injection. But it also shows undesirable disadvantages with large size nanocrystal. Stress induced leakage during retention is one of them to make the device worse reliability. And as the nanocrystal size increase, the density of nanocrystal will be decrease. Thus it is also a trade-off between operating speed and reliability in selecting size of nanocrystal. A typical target is a density at least 1012cm-2, and requires nanocrystal size be about 5 nm and below.
Moreover, good process control is needed with regards to such nanocrystal features as:
planar nanocrystal layer; inter-crystal interaction (lateral isolation); and crystal doping (type and level). Finally, it is preferred that that the fabrication process is simple and that
it uses standard semiconductor equipment.
After S. Tiwari proposed silicon nanocrystal memory devices instead of FG memory.
In order to improve the data retention by Coulomb blockade effect, double layer silicon nanocrystal memory has been invented [1.24]. It seems interesting to use Ge nanocrystals rather than Si nanocrystals because of its smaller band gap and higher dielectric constant.
Indeed King and Hu have recently demonstrated the superior memory properties of Ge based nanocrystal memories over those based on Si [1.25]. As the size and size distribution of the nanocrystals have been considered, She et al. [1.26] made a conclusion on Ge nanocrystal memory device that size around 5 nm is preferred to achieve fast programming speed and longer retention time. And size should not be scale below 5 nm due to the quantum confinement effect will be very significant.
There are several nonocrystal fabrication processes which have been demonstrated.
Numerous effort have focused on obtaining a high density of nanocrystals through a variety of techniques including aerosol technique, ion implantation, direct chemical vapor deposition (CVD), evaporation deposition such as sputter, dual E-gun, MBE and re-crystallization annealing of amorphous silicon (α-si). Kim et al. used conventional low pressure chemical vapor deposition (LPCVD) to fabricate silicon nonocrystals at 620
℃ [1.27]. Direct CVD of silicon is preferred over ion implantation and re-crystallization annealing because it is difficult to control the required amount of silicon in the stack.
Further, nucleation and growth by CVD provides simpler processing to control the size and the density of nanocrystals. Silicon nanocrystals with density between 1011 and 1012cm-2 have been deposited in various dielectrics such as SiO2 Si3N4 and Al2O3 by using CVD process. A higher density about 5×1011cm-2 was obtained on nitride surface, and the density was more than three times larger that on oxide surface[1.28]. Fernandesa et al. acquired the higher Si quantum dots density (~1012cm-2) by integrating on SiO2/Al2O3 tunneling dielectrics [1.29]. To fabricate Ge nanocrystals, the oxidation of mixed SiGe films has been proposed [1.25]. As the SiGe layer be oxidized, the Ge element will be segregated and Si will be oxidized into SiO2 [1.30-1.31]. Ostraat et al.
proposed an aerosol silicon nanocrystal nonvolatile memory device with large threshold voltage shift (＞3V), sub-microsecond program times, millisecond erase times, excellent endurance (＞105 program/erase cycles), and long term retention (＞106 sec) [1.32].As for the tunnel dielectric for nanocrystal NVM devices, high-k tunnel dielectric were investigated [1.16] [1.28] [1.33]. Results show that due to its unique band asymmetry in
programming and retention mode. Using high-k dielectric on Si channel offers lower electron barrier height and larger dielectric thickness resulted in much higher IG, Write/Erase/ IG, Retention ratio than SiO2. Therefore, we get faster program / Erase speed and longer retention.
In the future, the primary drivers behind nanocrystal memories are the potential to reduce the tunnel oxide thickness, resulting in lower operating voltages, and the simplicity of a single poly-silicon process. But there are still challenges for nanocrystal memories in the long road to commercialization. Nanocrystal memories have yet to deliver on most of their promises. In reality, part of the voltage gain is offset because of the poor control gate coupling. For fabrication processes, it is hard to control the uniformity of the nanocrystal size and their physical locations in the channel. It is not a surprise that nanocrystal memories exhibit large device-to-device variation. Moreover, it has yet to be demonstrated that both the nominal and the statistical retention behavior are sufficient to meet true non-volatility requirements. Although single-dot memories have been demonstrated [1.34-1.35], but a more fundamental understanding of the scaling limits of nanocrystal memories is necessary, concentrating especially on the aspect of controlling channel conductance when relying on only a few discrete charge centers [1.36]. Finally, in order for that to happen, their claimed benefits will need to be more unambiguously substantiated, and a more appealing bundle of memory features will have to be demonstrated.