This dissertation is divided into six chapters. The contents in each chapters are described briefly as follows:
In chapter 1, general background of nonvolatile memory, conventional flash memory, SONOS nonvolatile memory and nanocrystal memory are introduced.
In chapter 2, basics of program and erase operation are introduced.
In chapter 3, the Ge nanocrystal embedded in SiOx NVM structure, experimental process flow, results and discussions will be stated in this chapter.
In chapter 4, the Ge nanocrystal embedded in SiNx NVM structure, experimental process flow, results and discussions will be stated in this chapter.
In chapter 5, the Ge doped in Erbium silicate high-k dielectric film, which is a SONOS type NVM structure, experimental process flow, results and discussions will be stated in this chapter.
In chapter 6, the final chapter is included the conclusions and the future work.
Figure 1-1 The structure of the conventional floating-gate (FG) nonvolatile memory device. Continuous poly-silicon gate is used as the charge storage element.
Figure 1-2 The structure of the SONOS nonvolatile memory device. The nitride layer is used as the charge storage element.
Figure 1-3 The development of gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been main focus in recent years.
Figure 1-4 The structure of the nanocrystal (NC) nonvolatile memory device. The isolated nanocrystal with each other is used as the charge storage element.
Chapter 2
Nonvolatile Memory Basic Principles
2.1 Introduction
Most of operations on novel nonvolatile memories, such as SONOS and nanocrystal memories are base on the concept of Flash memory. If data was stored in selected cell of the memory, there are different procedures. The threshold voltage shift of a Flash transistor can be written as [2.1-2.2]:
FC
T C
V =− Q Δ
where Q is the charge weighted with respect to its position in the gate oxide, and the capacitances between the floating gate (FG) and control gate. The threshold voltage of the memory cell can be altered by changing the amount of charge present between the gate and the channel, corresponding to the two states of the memory cell, i.e., the binary values (“1” and “0”) of the stored bit. Figure 2-1 shows the threshold voltage shift between two states in a Flash memory. To a nonvolatile memory, it can be “written” into either state high state “1” or low state “0” by either “programming” or “erasing” methods, which are decided by the definition of memory cell itself. There are many solutions to achieve “programming” or “erasing”.
In this chapter, we will discuss program/erase mechanisms from the relation between bias and energy band bending. And different carrier injection mechanisms such as tunneling injection, channel hot electron injection and band to band tunneling. We will also discuss the reliability test briefly such as retention and endurance of NVM. Finally, some unique characteristic of nanocrystal memory will be discussed in the end of this chapter.
2.2 Basic Program/Erase Mechanisms
2.2.1 Energy band diagram during program and erase operation
The program/erase physical operation of a standard SONOS memory is illustrated in Figure 2-2. In the program operation, when a positive bias relative to the p-type substrate
applied on gate electrode, substrate induces an electron channel (inversion layer). Then the electron will tunnel through the tunnel oxide into the silicon nitride film and be trapped in deep level traps. Some electrons will not be trapped in the nitride film and will tunnel through the blocking oxide into gate electrode. The trapped electrons provide the electrostatic screening of the channel from the control gate, and result in a threshold voltage (VT) shift. In the erase operation, when a negative bias relative to the p-type substrate applied on the gate electrode. The holes will tunnel through tunnel oxide into the nitride trapping layer and partially be trapped. Further, trapped electrons may be de-trapped into the nitride conduction band and then tunnel back to the channel. Thus, for SONOS memory device operation both carrier types are involved in the transport process.
Figure 2-3 illustrates schematically the write and erase operation of an n-channel nanocrystal memory. When the different bias applied on gate electrode, it causes different results. When the bias is positive relative to substrate, the electrons in the inversion layer inject in to the nanocrystal. That phenomenon is called “write operation”. On the contrary, negative bias applied to gate causes the electrons tunneling back to channel and the holes in the accumulation layer tunneling into the nanocrystal from the channel.
2.2.2 Carrier Injection Mechanisms (a) Channel Hot Electron Injection (CHEI)
The physical mechanism of CHEI is relatively simple to understand qualitatively.
An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons). At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 105V/cm [2-3]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Figure 2-4 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields.
In the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation. For an electron to overcome this potential barrier, three conditions must hold [2.4].
(1) Its kinetic energy has to be higher than the potential barrier.
(2) It must be directed toward the barrier.
(3) The field in the oxide should be collecting it.
Nevertheless, a description of the injection conditions can be accomplished with two different approaches. The CHEI current is often explained and simulated following the
“lucky electron” model [2.5]. This model is based on the probability of an electron’s being lucky enough to travel ballistically in the field ε for a distance several times the mean free path without scattering, eventually acquiring enough energy to cross the potential barrier if a collision pushes it toward the Si/SiO2 interface. Consequently, the probability of injection is the lumped probability of the following events [2.6], which are depicted in Figure 2-5.
(1) The carrier has to be “lucky” enough to acquire enough energy from the lateral electric field to overcome the oxide barrier and to retain its energy after the collision that redirects the electron toward the interface (PΦb).
(2) The carrier follows a collision-free path from the redirection point to the interface (PED).
(3) The carrier can surmount the repulsive oxide field at the injection point, due to the Schottky barrier lowering effect, without suffering an energy-robbing collision in the oxide (POC).
(b) Tunneling Injection
There are several tunneling mechanisms are demonstrated in quantum mechanics.
Basically, tunneling injection must to have available states on the other side of the barrier for the carriers to tunnel into. The tunneling probability, depending on electron barrier height (φ(x) ), tunnel dielectric thickness (d), and effective mass (me) inside the tunnel dielectric, is express as [2.7]
(2-1) If we assume elastic tunneling, this is a reasonable assumption due to the thin oxide thickness involved. Namely, no energy loss during tunneling processes. Tunneling through the oxide can be attributed to different carrier-injection mechanisms. Which process applies depends on the oxide thickness and the applied gate field or voltage.
Direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT) are the main programming mechanisms employed in memory [2.8-2.10] as shown in Figure 2-6.
Direct Tunneling
For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [2.11]. As a result, F-N tunneling cannot serve as an efficient program/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. The direct tunneling is employed in nanocrystal memories instead. And that makes the nanocrystal memory with lower operation voltage and faster program/erase speed. Generally speaking, a thinner tunnel oxide with thickness below 5 nm is used to separate the nanocrystal from channel.
In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height, two to four orders of magnitude reduction in leakage current can still be achieved if large work function metals, such as Au or Pt [2.12]. Figure 2-6(a) shows the both sides barrier relative to thickness of the oxide that make electron direct tunneling through the oxide.
Fowler–Nordheim Tunneling
The Fowler–Nordheim (FN) tunneling mechanism occurs when applying a strong electric field (in the range of 8–10 MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very sharp. Hence, there is a high probability of electrons’ passing through the energy barrier itself. Using a free-electron gas model for the metal and the Wentzel–Kramers–Brillouin WKB approximation for the tunneling probability [2.13], one obtains the following expression for current density [2.14]:
⎥⎥ forbidden gap of the dielectric, h is the Planck’s constant, q is the electronic charge, and F is the electric field through the oxide. However, the exponential dependence of tunnel current on the oxide-electric field causes some critical problems of process control because, for example, a very small variation of oxide thickness among the cells in a memory array produces a great difference in programming or erasing currents, thus
∗
mOX
spreading the threshold voltage distribution in both logical states. Figure 2-6(b) shows the both sides barrier relative to thickness of the oxide that make electron Fowler–Nordheim tunneling through the oxide.
Modified Fowler–Nordheim Tunneling
Modified Fowler–Nordheim tunneling (MFN) is similar to the traditional FN tunneling mechanism, the carriers enter the nitride at a distance further from the tunnel oxide-nitride interface. MFN mechanism is frequently observed in SONOS memories.
The SONOS memory is designed for low-voltage operation (<10 V, depending on the Equivalent oxide thickness), a relatively weak electrical field couldn’t inject charges by DT or FN mechanism. Figure 2-6(c) shows the both sides barrier relative to thickness of the oxide that make electron Modified Fowler–Nordheim (MFN) tunneling through the dielectric.
Trap Assistant Tunneling
The charge storage elements with many traps may cause another tunneling mechanism. For instance, the charges tunnel through a thin oxide and arrive to the traps of nitride layer at very low electrical field in SONOS systems. During trap assisted injection the traps are emptied with a smaller time constant then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection.
Because of the sufficient injection current, trap assistant tunneling may influence in retention [2.15]. Figure 2-6(d) illustrates the Trap Assistant Tunneling through the dielectric.
(c) Band to Band Tunneling (BTBT)
Band to band tunneling application to nonvolatile memory was first proposed in 1989. I. C. Chen and et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [2.16]. Band to band tunneling (BTBT) process occurs in the deeply depleted doped surface region under the gate to drain or gate to source overlap region.
Band to Band Hot Electron Tunneling Injection
In n-type substrate, when band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant. The electrons are accelerated by a lateral electric field toward the
channel region and some of the electrons with sufficient energy can surmount the potential barrier of SiO2 like hot electron injection [2.16-2.18]. Figure 2-7 shows device operation during the band to band tunneling induced hot electron (BBHE) injection.
Band to Band Hot Hole Tunneling Injection
The injection is applied for p-type nonvolatile memory device. The mechanism is at the situation for both negative gate voltage and positive drain voltage. Electron-hole pairs are generated by BTBT in the drain region, as shown in Figure 2-8. The holes are accelerated by a lateral electric field toward the channel region and some of them obtain high energy. The hot holes with high energy will inject into charge trapping layer through the tunnel oxide and recombine with the stored electrons. This injection is used for a new erase operation for nonvolatile memory device [2.19].
2.3 Basic Reliability of Nonvolatile Memory
For a nonvolatile memory, the important to concern is distinguishing the state in cell.
However, in many times operation and charges storage for a long term, the state is not obvious with charges loss. Retention and endurance experiments are performed to investigate Flash-cell reliability. In general, NVMs are required to achieve up to 10-100K program/erase cycles (endurance) with 10-year memory retention at temperatures as high as 85 °C.
2.3.1 Retention
Retention means that how long does the memory keep the information without losing it. In any nonvolatile memory technology, it is essential to retain data for over ten years. This means the loss of charge stored in the storage medium must be as minimal as possible. For example, in modern Flash cells, FG capacitance is approximately 1 fF. A loss of only 1 fC can cause a 1V threshold voltage shift. If we consider the constraints on data retention in ten years, this means that a loss of less than five electrons per day can be tolerated [2.1]. There are four possible causes of charge loss: 1) by tunneling or thermionic emission mechanisms; 2) defects in the tunnel oxide; and 3) de-trapping of charge from insulating layers surrounding the storage medium; 4) mobile ion contamination. Further, the retention capability of Flash memories has to be checked by using accelerated tests that usually adopt screening electric fields and hostile environments at high temperature.
2.3.2 Endurance
Endurance referred the number of erase/write operations that the memory will complete and continue to operate as specified in the data sheet. Generally speaking, Flash products are specified for 106 erase/program cycles. Nevertheless, the endurance requirement may be relaxed with the increase of memory density for the other using.
A typical result of an endurance test on a single cell is shown in Figure 2-9. As the experiment was performed applying constant pulses, the variations of program and erase threshold voltage levels are described as “program/erase threshold voltage window closure” and give a measure of the tunnel oxide aging [2.20-2.21]. In particular, the reduction of the programmed threshold with cycling is due to trap generation in the oxide and interface state generation at the drain side of the channel. The evolution of the erase threshold voltage reflects the dynamics of net fixed charge in the tunnel oxide as a function of the injected charge. The initial lowering of the erase is due to a pile-up of positive charge which enhances tunneling efficiency, while the long-term increase of the erase is due to a generation of negative traps.
Moreover, a high field stress on thin oxide is known to increase the current density at low electric field. The excess current component, which causes a significant deviation from the current–voltage curves from the theoretical F-N characteristics at low field, is known as stress-induced leakage current (SILC). SILC is clearly attributed by stress-induced oxide defects, which leads to a trap assisted tunneling. The main parameters controlling SILC are the stress field, the amount of charge injected during the stress, and the oxide thickness. For fixed stress conditions, the leakage current increases strongly with decreasing oxide thickness [2.22-2.24].
2.4 Basic Physical Characteristics of Nanocrystal Memory
2.4.1 Quantum Confinement Effect
The quantum dot, is quasi-zero-dimensional nanoscaled material, and is composed by small amount atoms. The quantum confinement energy dependence on nanocrystal size has been studied both experimentally and theoretically with the tight-binding model [2.25]. The quantum confinement effect becomes significant when the nanocrystal size shrinks to the nanometer range, which causes the conduction band in the nanocrystal to shift to higher energy compared with bulk material [2.26]. For instance, a 3nm Ge nanocrystal can have a conduction band shift up 0.5eV as compared with bulk Ge, which
is significant enough to affect the electrical performance of the nanocrystal memory cell.
2.4.2 Coulomb Blockade Effect
With a electron is stored, the nanocrystal potential energy is raised by the electrostatic charging energy e2/2C, where C is the nanocrystal capacitance, which depends mainly on the nanocrystal size, though it also depends on tunnel oxide thickness and control oxide thickness. The capacitance is self-consistently calculated using an electrodynamics method [2.27]. Charging electrons will raise the nanocrystal potential energy and reduce the electric field across the tunnel oxide, resulting in reduction of the tunneling current density during the write process. It is more dominant at low programming voltages (< 3V). In a flash memory array, device cells often encounter disturbances with low gate voltage soft-programming. The Coulomb blockade effect can effectively inhibit the electron tunneling at low gate voltage and improve the flash memory array immunity to disturbance. However, the Coulomb blockade effect should be reduced by employing large nanocrystal if large tunneling current and fast programming speed were considered. The Coulomb blockade effect has a detrimental effect on the retention time, since the electrons in the nanocrystal have large tendency to tunnel back into the channel if the nanocrystal potential energy is high in retention mode.
Figure 2-1 ID-VGS curves of the floating-gate NVM device, with before (curve A) and after (curve B) negative charge Q is stored in the floating gate.
Figure 2-2 Energy band diagrams of the SONOS memory device under (a) program (b) erase operation. (e- : electrons, h+: holes.)
Figure 2-3 (a) The cross-section of nanocrystal memory device structure; (b) illustration of write process: inversion-layer electrons tunnel through tunnel oxide and inject into the nanocrystal; (c) illustration of erase process: accumulation layer holes tunnel through tunnel oxide and inject into the nanocrystal, electrons in nanocrystal also can tunnel back to the channel.
Figure 2-4 Schematics of channel hot electron injection (CHEI). The energy distribution function at point (X1,Y1) is also shown.
Figure 2-5 A schematic energy band diagram describing the different processes involved in electron injection.
(a) (b)
Figure 2-6 Fourth approaches to programming methods (a) Direct tunneling (DT) (b) Fowler-Nordheim (FN) tunneling (c) Modified Fowler-Nordheim (MFN) tunneling (d) Trap assistant tunneling (TAT).
Figure 2-7 The procedure of band to band hot electron injection.
Figure 2-8 The procedure of band to band hot hole injection.
Figure 2-9 A typical result of an endurance test on a single cell. Threshold voltage window closure as a function of program / erase cycles.
Chapter 3
Formation of Germanium Nanocrystals Embedded in Silicon Oxide Layer
3.1 Introduction
The nonvolatile memory (NVM) for portable electronic productions play an important role in semiconductor industrial because of its superiority in low-power consumption, low-cost, high-memory capacity and enough data retention[3.1][3.2]. The conventional NVM, however, can’t efficaciously prevent data loss in terms of reliability trials for future scaling down process, since its charge trapping layer is fabricated by floating gate (FG) structure and its tunnel oxide is ultra thin film about 2-5 nm[3.3][3.4].
Due to the discrete charge storage nodes acting as charge trapping layer to reform drawbacks of conventional FG memory, the NVMs using various semiconductor nanocrystals have been widely investigated in the past few years , such as silicon (Si) , germanium (Ge) and Zine-Oxide (ZnO) nanocrystals[3.2][3.5]. Moreover, in order to improve operation speed one can replace silicon nanocrystals (NC-Si) by germanium nanocrystals (NC-Ge) thanks to its higher dielectric constant (~16.0, i.e., stronger coupling with the conduction channel). In the other way, Ge nanocrystals device will improve data retention time due to its smaller energy band gap. Indeed King et al. [3.6]
have reported recently superior properties for NC-Ge base on memory over than NC-Si in terms of writing/erasing time.
According to the current research, the self-assembled and direct growth of Ge
According to the current research, the self-assembled and direct growth of Ge