Chapter 3 Formation of Germanium Nanocrystals Embedded
3.6 Summary I
From the above experiments result, we successfully incorporated oxygen into SiGe layer forming a new dielectric SiGeO film by sputtering a commixed target (SixGe1-x) in an Ar/O2 environment at room temperature. After some failed experiments, we find out the “pre-annealing capping oxide (PACO)” is a critical step in our process flow. The self-assembled phenomenon of Germanium nanocrystal can be explained by the chemical free energy. The Ge nanocrystals embedded in SiOx memory was fabricated easily. And the high density (~1012) of Ge nanocrytals can be achieved in this study. We observed that longer thermal treatment (RTA) can improve the isolation and nucleation of Ge nanocrystals. The memory window of RTA 900℃ 60s condition is 3.2V under ±10V sweeping operation. And the memory window is large enough to define high and low states for nonvolatile memory application. The retention and endurance characteristics are good enough to be maintained up to 10 years and 106 program/erase cycles. In addition, this novel and simple fabrication technique of germanium nanocrystals could be compatible with current manufacture process of the integrated circuit manufacture.
62.2%
Table 3-1 Surface atomic concentration ratio of the sample I (Si0.8Ge0.2O) from X-ray photoelectron spectroscopy (XPS) analysis.
51.2%
Table 3-2 Surface atomic concentration ratio of the sample I (Si0.5Ge0.5O) from X-ray photoelectron spectroscopy (XPS) analysis.
RTA 900℃ 60s 3.1V
Table 3-3 Comparison of memory window under ± 10V sweeping operation with different samples and different treatment conditions.
1.15V (25.5%)
Table 3-4 Comparison of memory window under ± 10V sweeping operation and remained charge ratio after 10 years with different thermal treatment time.
Figure 3-1 Schematics of the experimental process flow with co-sputtering silicon and germanium targets.
Figure 3-2 Cross-sectional TEM images of the MOIOS structure after a 900 60sec ℃ RTO process.
Binding Energy (eV)
Figure 3-3 Ge 2p XPS analysis of the sample after 900 60sec RTO process.℃ The peak position about 1220eV is the GeO2 signal.
Gate Voltage (V)
Figure 3-4 Capacitance-voltage (C-V) hysteresis of the fabricated MOIOS structure after a 900 60s℃ ec RTO process.
Figure 3-5 The band diagram for the charge trapping center for GeO2 layer MOIOS structure.
(a)
(b)
Figure 3-6 The process flow for different commixed target (a) Si0.8Ge0.2 (b) Si0.5Ge0.5
without pre-annealing capping oxide (PACO).
(a)
(b)
Figure 3-7 The process flow for different commixed d target (a) Si0.8Ge0.2 (b) Si0.5Ge0.5
with pre-annealing capping oxide (PACO) step.
Binding Energy (eV)
Figure 3-8 The XPS analysis by using an Al Kα (1486.6 eV) x-ray radiation is demonstrated the chemical composition of the sample I (Si0.8Ge0.2O) (a) Si 2p (b) Ge 3d (c) O 1s core-level spectra.
Binding Energy (eV)
(b) Ge 3d Experiment Data
Fitting results
Figure 3-9 The XPS analysis by using an Al Kα (1486.6 eV) x-ray radiation is demonstrated the chemical composition of the sample II (Si0.5Ge0.5O) (a) Si 2p (b) Ge 3d (c) O 1s core-level spectra.
Figure 3-10 Cross-sectional TEM images of standard Sample II (Si0.5Ge0.5O) without any thermal treatment.
(a)
(b)
Figure 3-11 Capacitance-voltage (C-V) hysteresis of (a) standard sample I (b) standard sample II.
(a)
(b)
Figure 3-12 Capacitance-voltage (C-V) hysteresis of (a) sample I Si0.8Ge0.2O (b) sample II Si0.5Ge0.5O after RTA at 900℃ for 30sec without PACO.
Figure 3-13 Cross-sectional TEM images of the Sample II (Si0.5Ge0.5O) after RTA at 900℃ for 30sec without PACO.
Sputter Time (sec)
0 100 200 300 400 500 600
Secondary Ion Counts
102 103 104 105 106
SiO2/SiGeO/SiO2/Si
→substrate
Si
O
Ge
(a)
Figure 3-14 (a) SIMS depth profile of the standard sample II (Si0.5Ge0.5O).
Sputter Time (sec)
SiO2/SiGeO/SiO2/Si
→substrate
SiO2/SiGeO/SiO2/Si
→substrate
Figure 3-14 (b) SIMS depth profile of the sample II (Si0.5Ge0.5O) after RTA at 900℃ for 30sec without PACO. (c) Comparison of the SIMS depth profile for the sample II with and without RTA treatment.
Figure 3-15 Capacitance-voltage (C-V) hysteresis of sample I Si0.8Ge0.2O after RTA at 900℃ for 30sec with PACO.
(a)
(b)
Figure 3-16 (a) and (b) TEM diagram of the sample I (Si0.8Ge0.2O) after RTA at 900℃
for 30sec with PACO.
Time (s)
0 100 200 300 400 500 600
Secondary Ion Counts
102 103 104 105 106
Si
O
SiO2/SiGeO/SiO2/Si→substrate
Ge
Time (s)
0 100 200 300 400 500 600
Secondary Ion Counts
102 103 104 105 106
Si
O
SiO2/SiGeO/SiO2/Si→substrate
Ge
Figure 3-17 SIMS depth profile of the sample II (Si0.5Ge0.5O) after RTA at 900 ℃ for 30sec with PACO.
Figure 3-18 Capacitance-voltage (C-V) hysteresis of sample II Si0.5Ge0.5O after RTA at 900℃ for 30sec with PACO.
(a)
(b)
Figure 3-19 (a) and (b) TEM diagram of the sample II (Si0.5Ge0.5O) after RTA at 900℃
for 30sec with PACO.
Figure 3-20 Comparison of the SIMS depth profile for the sample II before and after RTA at 900℃ for 30sec with PACO.
(a)
G ate V oltage (V )
Figure 3-21 different sample I and sample II after RTA 900 30sec with PACO (a) ℃ comparison of SIMS depth profile (b) C-V curve of the sample II (c) C-V curve of the sample I.
(c)
Figure 3-22 Capacitance-voltage (C-V) hysteresis of sample II Si0.5Ge0.5O after RTA at 900℃ for 60sec with PACO.
(a)
(b)
Figure 3-23 (a) and (b) TEM diagram of the sample II (Si0.5Ge0.5O) after RTA at 900 ℃ for 60sec with PACO.
Binding Energy (eV)
Figure 3-24 The X-ray photoelectron spectroscopy (XPS) analysis of the Ge 3d core-level spectrum. The Ge-O signal is at about 31eV shift to lower bonding energy 29 eV which is the Ge-Ge signal peak position before thermal treatment (RTA).
(a)
Figure 3-25 (a) Data retention characteristics of the Ge nanocrystals embedded in SiOx
memory with RTA at 900℃for 30sec.
(b)
Figure 3-25 (b) Data retention characteristics of the Ge nanocrystals embedded in SiOx
memory with RTA at 900 for 60sec.℃
Figure 3-26 (a) The band diagram of the MOIOS structure as measuring current density-voltage (J-V) characteristics.
Gate Voltage (V)
-10 -5 0 5 10
J(A/cm
2 )
10-12 10-11 10-10 10-9 10-8 10-7
STD 900 30s℃ 900 60s℃
Figure 3-26 (b) The current density-voltage (J-V) of Ge nanocrystals embedded in SiOx
memory with and without thermal treatment (RTA).
Program/Erase Cycles
Program / Erase Cycles
100 101 102 103 104 105 106 107
Program / Erase Cycles
100 101 102 103 104 105 106 107
Figure 3-27 Endurance characteristics of the Ge nanocrystal memory after RTA at (a) 900
℃ for 30sec (b) 900℃ for 60sec.
Chapter 4
Formation of Germanium Nanocrystals Embedded in Silicon Nitride Layer
4.1 Introduction
As we mentioned at the first chapter in the thesis, poly-si/oxide/nitride/oxide/silicon (SONOS) nonvolatile memory devices have been widely used in the integrated circuit market. The charge storage elements in SONOS memory are the charge traps distributed throughout the volume of the silicon nitride (Si3N4) layer. A typical trap has a density of the order 1018-1019 cm-3 according to Yang et al [4.1] and stores both electrons and holes (positive charge) injected from channel.
Base on the high trap density of silicon nitride, some study wad reported to fabricate germanium nanocrystal embedded in SiNx dielectric [4.2]. The nitride can increase trapping states to improve memory window under electrical operation.
Comparing to SONOS and Ge nanocrystals NVMs, a larger memory window can be obtained. When a memory device has a large memory window, it is easier to meet the requirement of 10 years.
In this chapter, we propose a new SiGeN film on tunnel oxide to form Ge nanocrystals embedded in SiNx dielectric memory for nonvolatile memory.
4.2 Experimental Sample Preparation
Figure 4-1 indicates a schematic of experimental procedure. This nonvolatile memory-cell structure in this study was fabricated on a 4 inches p-type silicon (100) wafer, which had been removed native oxide and particles by RCA process. After a standard RCA clean, a 5-nm-thick tunnel oxide was thermally grown by a dry oxidation process at 950℃ in an atmospheric pressure chemical vapor deposition (APCVD) furnace. Subsequently, a 8-nm-thick nitrogen incorporated Si0.5Ge0.5 (SiGeN) layer was deposited on tunnel oxide by reactive sputtering of Si0.5Ge0.5 commixed target in the Ar/N2 (24sccm/20sccm) ambiance at room temperature. This step can obtain a nitrogen incorporated SixGe1-x layer as a charge trapping layer in our memory. We choose the Si0.5Ge0.5 target for this experiment due to previously result. Si0.5Ge0.5 target can allow
enough Ge concentration in the deposited film.
In order to prevent the Ge interacting with the oxygen in the chamber result in GeO out-diffusion during RTA process. We deposited a 20-nm-thick PECVD oxide on the trapping layer before RTA. We called this step “pre-annealing-capping-oxide”
(PACO).After that, we annealed the sample by RTA at 900 for 30sec and 60sec in ℃ Nitrogen ambiance. The RTA process was performed to cause the self-assembled of Ge nanocrystal in the charge trapping layer. After RTA process, a 20-nm-thick blocking oxide was deposited by PECVD at 300 . Al gate electrodes on back and front side of the ℃ sample were finally deposited and patterned to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure. And we noted this MOIOS structure for “Sample III”.
Electrical characteristics, including the capacitance-voltage (C-V) hysteresis, current density-voltage (J-V), retention, and endurance characteristics, were also performed. The J-V and C-V characteristics were measured by Keithley 4200 and HP4284 Precision LCR Meter with high frequency 1 MHz. In addition, transmission electron microscope (TEM) and X-ray photoelectron spectroscopy (XPS) were adopted for the micro-structure analysis and chemical material analysis.
4.3 Results and discussion
The XPS analysis by using an Al Kα (1486.6 eV) x-ray radiation is demonstrated the chemical composition of the sample III (Si0.5Ge0.5N), as shown in figure 4-2. Figure 4-2 (a), (b), (c) show Si 2p, Ge 3d, N 1s core-level spectra. We can roughly define the trapping layer atomic composition of sample III by a common method using similar calculation as equation (3-2). The “I” means the peak intensity, and “S” the material sensitivity of the ESCA. And the atomic concentration with silicon, germanium and nitrogen of the charge trapping layer are 45.2%, 23.1%, and 31.7%, as table 4-1 shown.
We can observe that nitrogen was successfully incorporated during sputter process in the Ar/N2 ambiance.
Figure 4-3 shows the transmission electron microscope (TEM) diagram of the control Si0.5Ge0.5N sample (sample III). We can figure out a continuous and uniform SiGeN film was deposited on the tunnel oxide.
Figure 4-4 shows the capacitance-voltage (C-V) hysteresis of control sample III (without any thermal treatment). It is found that the control samples show no memory effect.
Figure 4-5 exhibits the typical C-V hysteresis of sample III (Si0.5Ge0.5N) after RTA
at 900 for 30sec obtained with gate voltage from inversion to accumulation and ℃ reversely. From the figure 4-5, it is obviously observed that the Flat-band voltage shift (memory window, V△ FB) is about 3.2V under ± 10V operation. The MOIOS structure with Ge nanocrystals embedded in SiNx dielectric exhibits clear counterclockwise hysteresis by a flat-band voltage shift, indicating a significant memory effect. We consider that the charges could be stored in both Ge nanocrystals and SiNx traps. And the counterclockwise hysteresis is due to injection of electrons from the deep inversion layer and discharge of electrons from the deep accumulation layer of silicon substrate.
Moreover, the memory window of Ge nanocrystals embedded in SiNx matrix is large enough to be defined logic “high” and “low” state.
Figure 4-6 shows a cross-sectional TEM image of the sample III after RTA at 900 ℃ for 30sec with PACO in nitrogen ambiance. From figure 4-6, we can figure out some Ge atom was self-assembled and separated in the SiNx dielectric. The SiNx can be used to improve charge storage ability for nonvolatile memory application [4.3]. Compare figure 4-6 with figure 4-3, the charge trapping layer was no longer a continuous film after RTA process. And the average diameter of the nanocrystals is approximately 6~8 nm and the area density of the nanocrystals is estimated to be about 1.12×1012cm-2 by TEM analysis.
In order to improve the performance of Germanium nanocrystal memory, we extended the RTA process at 900 from 30sec to 60sec. Figure 4℃ -7 shows the forward and reverse sweep C-V hysteresis of the sample III (Si0.5Ge0.5N) after RTA at 900 for ℃ 60sec in nitrogen ambiance with PACO. The sweeping condition were operated (i) from -5V to 5V, and reversely, (ii) from -10V to 10V, and reversely. The flat-band voltage shift is about 3.75V under ± 10V gate sweeping operation. From the above results, we can figure out that the charging effect of Ge nanocrystals embedded SiNx after longer RTA treatment is more significant.
Figure 4-8 show the TEM image of the sample III (Si0.5Ge0.5N) after RTA at 900 ℃ for 60sec with PACO. From the figure 4-8, Ge was segregated and nucleated obviously.
The average diameter of the nanocrystals is approximately 6-9 nm and the area density of the nanocrystals is estimated to be about 1.06×1012 cm-2 by TEM analysis. Compare figure 4-8 with figure 4-6, we can discover that the nucleation and isolation of Ge nanocrystals became better after longer thermal treatment. That is one the reasons for 900 6℃ 0sec sample has larger memory window than the other one.
Mechanism of Germanium Nanocrystal Formation by Thermal Treatment:
From the section 3.4, we used chemical reaction free energy and Gibbs free energy
to explain the phenomena for Ge self-assembled in the SiGeO ternary dielectric film.
In this section, we will discuss the mechanism of Ge nanocrystals formation by thermal treatment. Si reacts preferentially with N due to the lower Gibbs free energy of the Si compound than Ge compound in the Si-Ge-N ternary system [4.4]. And then unreacted Ge atoms accumulated and nucleated. The similar phenomena were observed in Si-Ge-O system.
The reliability characteristics, such as retention time and endurance, were also discussed in this study. Note that the reliability measured samples be discussed later are all with the “PACO” condition.
The charge retention characteristics of the MOIOS structure with Ge nanocrystals embedded in the SiNx after RTA at 900 for 30sec and 60sec are illustrated in figure 4℃ -9 (a) and (b). The retention measurements are performed at room temperature by operating a ±15V gate voltage stress for 10 sec. The flat-band voltage shift is obtained by comparing the C-V curves from a charged state to the quasi-neutral state. When the carriers are stored in the nanocrystals, the stored charges will raise the nanocrystal potential energy and increase the probability of escaping from the nanocrystal to silicon substrate or gate. Figure 4-9 (a) shows retention time of the sample after RTA at 900 ℃ for 30sec. The memory window decays during the stored charges leaked out from the nanocrystals to substrate or gate. And a 0.62 V memory window is expected to maintain after 10 years, which is approximately 16% of the stored charges retained in the nanocrystals. Figure 4-9 (b) shows retention time of the sample after RTA at 900℃ for 60sec. Similarly, the memory window decays during the stored charges leaked out from the nanocrystals to substrate or gate. And a 1.22 V memory window is expected to maintain after 10 years, which is approximately 28% of the stored charges retained in the nanocrystals. Both of them retain a memory window larger than 0.5V, which is enough to define “1” or “0” of memory state. It is easily observed the sample with longer thermal treatment (RTA) condition shows better retention time. The explanation of the different results will be discussed later.
Endurance characteristics of the MOIOS structure with Ge nanocrystals embedded in the SiNx with different RTA times are illustrated in figure 4-10 (a) and (b). Pulses (VG
= ± 5V, 1ms) were applied to evaluate endurance characteristics for the Program/Erase operation. Both of the (a) 900 for ℃ 30sec and (b) 900℃ for 60sec still show a better endurance performance after 106 program/erase cycles. Form the endurance data, we can find out the tunnel oxide and the dielectric below nanocrystal have good quality of both
sample.
Figure 4-11 illustrates the current density-voltage (J-V) characteristics of the MOISO structure with different thermal treatment time. The leakage current density in the figure 4-11 diagram decreases from 10-8 order to 10-9 with longer annealing time from 30sec to 60 sec. It means the quality of the blocking oxide and SiNx dielectric above the Ge nanocrystals is getting better after longer RTA process.
For the endurance, current density-voltage (J-V) measurements and the TEM images, we can observe that both isolation of the Ge nanocrystals and the upper leakage path through blocking oxide affect the data retention characteristics.
The comparisons of memory window under ± 10V sweeping operation and memory window after 10 years of Ge nanocrystal embedded in SiNx MOIOS structure between different thermal treatment (RTA) times were listed in Table 4-2. The 900℃
60sec sample shows larger memory window the 30sec one. That is because the longer thermal treatment induces the better isolation and nucleation of Ge. And longer thermal treatments not only make Ge isolated and nucleated better, but also reduce the SiNx
defects above the Ge NCs.
Let’s compare the two different structures for Ge nanocrystals memory. All the results were done with PACO step. Table 4-3 shows the memory windows under ±10V operation with different MOISO structure. Figure 4-12 (a) and (b) illustrate the energy band diagram of two different Ge nanocrystals structure, (a) for Ge nanocrystals embedded in SiOx and (b) for Ge nanocrystals embedded in SiNx. For the first structure, we can find out that Ge-rich samples show better electrical performance due to sufficient Ge atoms to form nanocrystal. From figure 4-12, we can observe that the charge trap centers of the second structure are not only (i) interface state between nanocrystals and the surrounding dielectric, (ii) nanocrystal confined state but also (iii) traps in side the SiNx dielectric layer. Because the SiNx supply additional accessible charge trap states, the second structure shows larger memory window than first one. We can say that the second structure is combined nanocrystal with SONOS structure.