Coulomb Blockade Effect - Basic Physical Characteristics of Nanocrystal Memory

Chapter 2 Nonvolatile Memory Basic Principles

2.4 Basic Physical Characteristics of Nanocrystal Memory

2.4.2 Coulomb Blockade Effect

With a electron is stored, the nanocrystal potential energy is raised by the electrostatic charging energy e²/2C, where C is the nanocrystal capacitance, which depends mainly on the nanocrystal size, though it also depends on tunnel oxide thickness and control oxide thickness. The capacitance is self-consistently calculated using an electrodynamics method [2.27]. Charging electrons will raise the nanocrystal potential energy and reduce the electric field across the tunnel oxide, resulting in reduction of the tunneling current density during the write process. It is more dominant at low programming voltages (< 3V). In a flash memory array, device cells often encounter disturbances with low gate voltage soft-programming. The Coulomb blockade effect can effectively inhibit the electron tunneling at low gate voltage and improve the flash memory array immunity to disturbance. However, the Coulomb blockade effect should be reduced by employing large nanocrystal if large tunneling current and fast programming speed were considered. The Coulomb blockade effect has a detrimental effect on the retention time, since the electrons in the nanocrystal have large tendency to tunnel back into the channel if the nanocrystal potential energy is high in retention mode.

Figure 2-1 ID-VGS curves of the floating-gate NVM device, with before (curve A) and after (curve B) negative charge Q is stored in the floating gate.

Figure 2-2 Energy band diagrams of the SONOS memory device under (a) program (b) erase operation. (e^-: electrons, h⁺: holes.)

Figure 2-3 (a) The cross-section of nanocrystal memory device structure; (b) illustration of write process: inversion-layer electrons tunnel through tunnel oxide and inject into the nanocrystal; (c) illustration of erase process: accumulation layer holes tunnel through tunnel oxide and inject into the nanocrystal, electrons in nanocrystal also can tunnel back to the channel.

Figure 2-4 Schematics of channel hot electron injection (CHEI). The energy distribution function at point (X1,Y1) is also shown.

Figure 2-5 A schematic energy band diagram describing the different processes involved in electron injection.

(a) (b)

Figure 2-6 Fourth approaches to programming methods (a) Direct tunneling (DT) (b) Fowler-Nordheim (FN) tunneling (c) Modified Fowler-Nordheim (MFN) tunneling (d) Trap assistant tunneling (TAT).

Figure 2-7 The procedure of band to band hot electron injection.

Figure 2-8 The procedure of band to band hot hole injection.

Figure 2-9 A typical result of an endurance test on a single cell. Threshold voltage window closure as a function of program / erase cycles.

Chapter 3 Formation of Germanium Nanocrystals Embedded in Silicon Oxide Layer

3.1 Introduction

The nonvolatile memory (NVM) for portable electronic productions play an important role in semiconductor industrial because of its superiority in low-power consumption, low-cost, high-memory capacity and enough data retention[3.1][3.2]. The conventional NVM, however, can’t efficaciously prevent data loss in terms of reliability trials for future scaling down process, since its charge trapping layer is fabricated by floating gate (FG) structure and its tunnel oxide is ultra thin film about 2-5 nm[3.3][3.4].

Due to the discrete charge storage nodes acting as charge trapping layer to reform drawbacks of conventional FG memory, the NVMs using various semiconductor nanocrystals have been widely investigated in the past few years , such as silicon (Si) , germanium (Ge) and Zine-Oxide (ZnO) nanocrystals[3.2][3.5]. Moreover, in order to improve operation speed one can replace silicon nanocrystals (NC-Si) by germanium nanocrystals (NC-Ge) thanks to its higher dielectric constant (~16.0, i.e., stronger coupling with the conduction channel). In the other way, Ge nanocrystals device will improve data retention time due to its smaller energy band gap. Indeed King et al. [3.6]

have reported recently superior properties for NC-Ge base on memory over than NC-Si in terms of writing/erasing time.

According to the current research, the self-assembled and direct growth of Ge nanocrystals embedded in SiO2 layer has successfully been implemented such as Ge implantation into SiO2 [3.7-3.8], oxidation reduction of Ge/Si islands [3.9], UV-assisted oxidation of Si1-xGex alloy [3.10], and rapid thermal oxidation (RTO) of NC-Ge [3.11-3.12] or Ge + SiO2 [3.13]. Among various formation methods, the self-assembled was reported by many previous studies because it could control better density and size of nanocrystal than direct growth. Nevertheless, the self-assembled method must need a high temperature (~900-1100℃) with long duration (~30-60 min) oxidation process to

anneal the charge trapping layer that is deposited by various ratio of SiGe layer, and the over-oxidation phenomenon of Ge is often obtained after foregoing oxidation process.

Hence, an additional step must be added to the formation flow of Ge nanocrystal by using a high pressure H2 treatment [3.14-3.15] or steam process [3.16].

In order to reduce process flow and thermal budget, we choose the sputter system and rapid thermal anneal (RTA) for our experiments.

3.2 Growth SiGe and oxidation

There were a lot of experiments forming Ge nanocrystal by oxidizing the SiGe film.

The SiGe film might be deposited by different process such as low pressure chemical vapor deposition (LPCVD), sputter system, plasma enhanced chemical vapor deposition (PECVD). At the same, we tried to deposit SiGe thin film by co-sputter and thermal treatment.

3.2.1 Experimental Sample Preparation

Figure 3-1 shows schematics of the experimental process flow. This nonvolatile memory-cell structure in this study was fabricated on a 4 inches p-type silicon (100) wafer, which had been removed native oxide and particles by RCA process. After a standard RCA clean, a 3-nm-thick tunnel oxide was thermally grown by a dry oxidation process at 950 in an atmospheric pressure chemical vapor deposition (APCVD) ℃ furnace. Subsequently, a 7-nm-thick SiGe film was deposited on tunnel oxide by co-sputtering Si and Ge targets in Argon (Ar) ambiance at room temperature, and the Ar flow rate was set to 24 sccm (Standard Cubic Centimeter per Minute). And then we deposited a 10-nm-thick pure amorphous Si by sputtering Si target in pure Ar ambiance.

And the we oxidized the sample by rapid thermal anneal (RTA) at 900℃ 60sec in Oxygen ambiance. Expected Germanium nanocrystal could be found to precipitate and embed in silicon oxide. During the rapid thermal oxidation (RTO) process, the Si layer capped on the SiGe film was formed blocking oxide at the same time. Al gate electrodes on back and front side of the sample were finally deposited and patterned to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure.

Electrical characteristics of the capacitance-voltage (C-V) hysteresis were measured by Keithley 4200 and HP4284 Precision LCR Meter with high frequency 1 MHz. In addition, transmission electron microscope (TEM) and X-ray photoelectron spectroscopy (XPS) were adopted for the micro-structure analysis and chemical material analysis.

3.2.2 Results and Discussion

Figure 3-2 shows the TEM of the sample after RTO process. We can find out the charge trapping layer became a continuous film. The XPS analysis by using an Al Kα (1486.6 eV) x-ray radiation is demonstrated the chemical composition of the charge trapping layer, as shown in figure 3-3. From the Ge 2p core-level spectrum, we can see that the GeO2 peak is at about 1220 eV by fitting results. Therefore, we think the entire trapping layer was over-oxidized and the Ge layer all became GeO2. The capacitance-voltage (C-V) hysteresis is shown in figure 3-4. It is clearly observed that 0.5V memory window was obtained under ± 5 V gate voltage operation. And the hysteresis loops follow the counterclockwise due to injection of electrons from the deep inversion layer and discharge of electrons from the deep accumulation layer of Silicon substrate. Hence, we can be enough to define “1” and “0” states for nonvolatile memory application. Figure 3-5 shows the band diagram of our sample after RTO 900 60sec. ℃ GeO2 energy band gap is about 4 eV [3.17]. Due to GeO2 providing some charge traps and the interface trap with tunnel oxide, this sample still has memory effect.

According to the previous experiment result, we can find out some results: (1) the co-sputter method is hard to control the Si/Ge ratio; (2) conventional oxidation of SiGe layer is hard to control the oxidation time; (3) as our sample, the Ge was all oxidized and became GeO2 likes the below formula.

SiGe + O2 → SiO2 + GeO2 (3-1) There are some drawbacks from the above results, in ordering to solve the over oxidation problem. We propose a SiGeO film on tunnel oxide to avoid over-oxidation phenomenon.

3.3 Formation of Ge nanocrystal using SiGeO layer

3.3.1 Experimental Sample Preparation

This nonvolatile memory-cell structure in this study was fabricated on a 4 inches p-type silicon (100) wafer, which had been removed native oxide and particles by RCA process. After a standard RCA clean, a 5-nm-thick tunnel oxide was thermally grown by a dry oxidation process at 950℃ in an atmospheric pressure chemical vapor deposition (APCVD) furnace. Subsequently, a 8-nm-thick oxygen incorporated SixGe1-x (SiGeO) layer was deposited on tunnel oxide by reactive sputtering of SixGe1-x commixed target in the Ar/O2 (24sccm/2sccm) ambiance at room temperature. This step can obtain an oxygen

incorporated SixGe1-x layer as a charge trapping layer in our memory.

We choose two different ratio of Si/Ge. One is Si0.8Ge0.2 and the other is Si0.5Ge0.5. Si0.8Ge0.2 is a common ratio for LPCVD to form Ge nanocrystals (NCs) [3.18]. However its density of NCs is about 10¹¹cm^-2. In order to achieve higher density of NCs, we choose a higher Ge concentration target (Si0.5Ge0.5) and then we noted the first process with using Si0.8Ge0.2 target “Sample I”. The other one with Si0.5Ge0.5 was noted “Sample II”.

After that, we annealed the above two sample by rapid thermal anneal (RTA) at 900 30sec in ℃ Nitrogen ambiance. The RTA process was performed to cause the self-assembled of Ge nanocrystal in the charge trapping layer. After RTA process, a 30-nm-thick blocking oxide was deposited by PECVD at 300 . Al gate electrodes on ℃ back and front side of the sample were finally deposited and patterned to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure. Figure 3-6 (a) and (b) show schematics of the experimental process flow.

In addition, after the two different ratio of SiGeO film was deposited, we deposited a 20-nm-thick PECVD oxide on it. This step was called PACO (pre-annealing-capping-oxide). And then we annealed our sample by RTA at 900℃

30sec or 60sec in N₂ ambiance. The RTA process was performed to cause the self-assembled of Ge nanocrystal in the charge trapping layer. After RTA process, a 20-nm-thick blocking oxide was deposited by PECVD at 300℃. Al gate electrodes on back and front side of the sample were finally deposited and patterned to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure. Figure 3-7 (a) (b) shows schematics of the experimental process flow.

Electrical characteristics, including the capacitance-voltage (C-V) hysteresis, current density-voltage (J-V), retention, and endurance characteristics, were also performed. The J-V and C-V characteristics were measured by Keithley 4200 and HP4284 Precision LCR Meter with high frequency 1 MHz. In addition, transmission electron microscope (TEM) and X-ray photoelectron spectroscopy (XPS) were adopted for the micro-structure analysis and chemical material analysis.

_O1s (3-2) The “I” means the peak intensity, and “S” the material sensitivity of the ESCA. The atomic concentration with silicon, germanium and oxygen of the charge trapping layer are 34.3%, 3.5%, and 62.2%, as table 3-1 shown. We can observe that oxygen was successfully incorporated in charge trapping layer during sputter process and the Ge concentration is deficient.

As the same, figure 3-9 (a), (b), (c) exhibit the Si 2p, Ge 3d, O 1s core-level spectra of the sample II (Si0.5Ge0.5O). And we use the same method to define the atomic concentration roughly. The atomic concentration with silicon, germanium and oxygen of the charge trapping layer are 32%, 16.8%, and 51.2%, as table 3-2 shown. We can also observe that oxygen was successfully incorporated during sputter process but the Ge concentration is more than sample I.

Figure 3-10 shows the transmission electron microscope (TEM) diagram of the control Si0.5Ge0.5O sample (sample II). We can figure out a continuous and uniform SiGeO film was deposited on the tunnel oxide.

Figure 3-11 (a) and (b) show the capacitance-voltage hysteresis of control sample I and control sample II (without any thermal treatment). It is obviously that both of the control samples show no memory effect. Figure 3-12 (a) and (b) show the C-V hysteresis of both sample I and II after RTA 900 30sec℃ in nitrogen ambiance. The electrical C-V measurements were performed by bidirectional voltage sweeping. The sweeping condition were split as follows, (i) from 5V to -5V, and reversely, (ii) from 10V to -10V, and reversely. However, our samples still show no memory effect after thermal treatment as figure 3-11 (a) and (b) shown. Figure 3-13 show the TEM diagram of the sample II after RTA 900 30sec℃ in nitrogen ambiance. From figure 3-13, we could find out some Ge atom was self-assembled. Compare figure 3-13 with figure 3-10, the charge trapping layer was no longer a continuous film after RTA process. And the Ge concentration seems to become less after RTA process. Therefore, we made some secondary ion mass spectrometer (SIMS) analysis for our sample. Figure 3-14 (a) and (b) exhibit the SIMS analysis for sample II (Si0.5Ge0.5O) before and after RTA process. What should we

concern is the Ge concentration of these two sample. Ge secondary ions counts is over 10⁵ before RTA, but became just between 10³ and 10⁴ after RTA. In order to compare their difference clearly, we put them on the same picture. Figure 3-14 (c) shows both Ge concentrations before and after RTA process. Obviously, Ge secondary ions counts decrease about two orders after thermal treatment. We think that is because Ge got bonded with oxygen during the RTA process, and GeO is a kind of volatile compound.

Hence, the Geo was out-gasing and left the surface [3.19]. As the Ge becomes less, there is not enough Ge to be self-assembled. Therefore, we deposited a 20-nm-thick oxide by PECVD to avoid GeO out-gasing before thermal treatment. We call this step pre-annealing capping oxide (PACO).

As the previous process flow we have mentioned, figure 3-15 show C-V hysteresis of the sample I (Si0.8Ge0.2O) after RTA 900 ℃30sec in nitrogen ambiance with PACO. It shows memory effect, when we capped PECVD oxide before RTA process. Under ±10V operation, the Flat-band voltage shift (memory window, V△ FB) is about 0.65V. And the hysteresis loops follow the counterclockwise due to injection of electrons from the deep inversion layer and discharge of electrons from the deep accumulation layer of Silicon substrate. Hence, we can be enough to define “1” and “0” states using this nonvolatile memory. Figure 3-16 (a) and (b) show the TEM diagram of the sample I (Si0.8Ge0.2O) after RTA with PACO. From the figure 3-16 (b), Ge was segregated and nucleated obviously. And the Ge dot size is about 4~6 nm. Moreover, the lattice image is shown in the figure 3-16 (a). We can easily observe that Ge was self-assembled from the TEM picture, but why the memory effect is not so obvious. Figure 3-17 exhibits the SIMS analysis of the sample I after RTA with PACO. From the SIMS analysis, we can presume that the memory effect is not obvious due to there is not sufficient Ge.

With the previous results, increasing the Ge concentration seems indeed to enlarge the memory effect. Figure 3-18 shows C-V hysteresis of the sample II (Si0.5Ge0.5O) after RTA 900 ℃ 30sec in nitrogen ambiance with PACO. The electrical C-V measurements were performed by bidirectional voltage sweeping. The sweeping condition were split as follows, (i) from -5V to 5V, and reversely, (ii) from -10V to 10V, and reversely. Under

±10V sweeping operation, the Flat-band voltage shift (memory window, △VFB) is about 2.8V. When the device is programmed, the electrons directly tunnel from the Si substrate through tunnel oxide, and are trapped in the forbidden gap of Ge nanocrystal embedded in the SiOx layer. For the erasing step, the holes may tunnel from the valance band of Si substrate and recombine with the electrons trapped in the Ge nanocrystals embedded SiO

layer. The stacked structure with Ge nanocrystals in the dielectric layer was used for the application of memory. The charge trap canters are believe to be resulted from the (i) interface states between the silicon substrate, (ii) traps inside the dielectric layer, (iii) nanocrystal confined state, (iv) interface states between nanocrystals and the surrounding dielectric[3.20].

Figure 3-19 (a) and (b) show the TEM diagram of the sample II (Si0.5Ge0.5O) after RTA 900℃ 30sec with PACO. From the figure 3-19 (b), Ge was segregated and nucleated obviously. The average diameter of the nanocrystals is approximately 5-6 nm and the area density of the nanocrystals is estimated to be about 1.73×10¹²cm^-2 by TEM analysis. Moreover, the lattice image is shown in the figure 3-19 (a). In the figure 3-19 (a), we can find out a common phenomenon about Ge diffused toward the SiOx or SiO2 in our experiment. Figure 3-20 shows SIMS analysis with sample II (Si0.5Ge0.5O) before and after RTA process. It clearly exhibits the Ge will diffuse in the silicon oxide. Because of our thermal treatment using RTA which lower thermal budget, that made Ge’s diffusion length be limited. And all the Ge atoms were confined in the region we want. Figure 3-21 (a) (b) (c) show the relationship with different ratio of Si/Ge and their electrical characteristics. We can figure out that sample I’s memory window under ±10V operation is smaller the sample II’s one with the same thermal treatment condition. Hence, we make a comment about that if we want to form Ge nanocrystal for charge storage elements; we need sufficient Ge of course.

In order to improve the performance of Germanium nanocrystal memory, we extended the annealing duration of RTA process from 900 30sec to 900 60sec. ℃ ℃ Figure 3-22 shows C-V hysteresis of the sample II (Si0.5Ge0.5O) after RTA 900 6℃ 0sec in nitrogen ambiance with PACO. The electrical C-V measurements were performed by bidirectional voltage sweeping. The sweeping condition were split as follows, (i) from -5V to 5V, and reversely, (ii) from -10V to 10V, and reversely. Under ±10V sweeping operation, the Flat-band voltage shift (memory window, △VFB) is about 3.1V. Figure 3-23 (a) and (b) show the TEM diagram of the sample II (Si0.5Ge0.5O) after RTA 900 ℃ 60sec with PACO. From the figure 3-23 (b), Ge was segregated and nucleated obviously.

The average diameter of the nanocrystals is approximately 4-8 nm and the area density of the nanocrystals is estimated to be about 1.26×10¹²cm^-2 by TEM analysis. Moreover, the lattice image is shown in the figure 3-23 (a). Compare figure 3-23 (b) with figure 3-19 (b), we can discover that the nucleation and isolation of Ge nanocrystals became better after

longer thermal treatment. That is the reason for 900 6℃ 0sec sample has larger memory window than the other.

According the above electrical characteristics, we make a table to compare the performance with each other. Table 3-3 shows the memory window under ±10 V operation with different condition. We can find out some results from this table: (i) Pre-annealing-capping oxide (PACO) which can avoid GeO out-diffusion is a critical step in our process. (ii) Germanium nanocrystals density and memory window are related to Ge concentration. (iii) Longer thermal treatment make Germanium be better isolated and nucleated. (iv) High pressure hydrogen annealing could be replaced by RTA SiGeO film to simplify the process flow and reduce fabrication cost.

3.4 Mechanism of Germanium Nanocrystal Formation by thermal treatment

In this section, we will discuss the mechanism of Ge nanocrystals formation by thermal treatment.

3.4.1 Reaction free energy

In pure O2, oxidation of silicon and germanium, forming SiO2 and GeO2, occurs following the reaction: thermodynamically more preferable than GeO2. Thermodynamically, GeO2 is not stable in the presence of silicon. Thus, during the simultaneous oxidation process reduction reaction takes place at the reaction interface, forming more SiO2 while liberating germanium from GeO2, as long as silicon is available [3.21], i.e.,

Si + GeO2 → SiO2 +Ge

On the other hand, we use Gibbs free energy to explain our result.

At 1200 K Si + O → SiO △G = -805 kJmol^-1 (3-5) Ge + O → GeO G =△ -666 kJmol^-1 (3-6) From the above equations [3.22], because of the smaller Gibbs free energy of Si–O compared with Ge–O, the oxygen atoms can interact with Si atom easier than with Ge

atom in the SiGeO ternary film during the RTA process.

3.4.2 Results and discussion

Base on the previous study, we know that Ge may get bonded with oxygen from SiO2 when the temperature below 400 . GeO is a volatile material, therefore when the ℃ temperature over 400 , it will become gas state. And the temperature getting higher, ℃

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