Chapter 1 Introduction
1.2 Organization of the Thesis
Three main topics are investigated and discussed in this dissertation. First, the
effect of hot-electron-induced electron trapping on device reliability and the low-frequency flicker noise characteristics for the deep sub-micron nMOSFETs with ultra-thin nitrided gate oxides are investigated. Second, the device degradation mechanism and the channel thickness effect on device characteristics for the deep sub-micron strained SiGe channel pMOSFETs with ultra-thin N2O-annealed SiN gate dielectric are studied. Third, the electrical characteristics of the ultra-thin HfO2 gate dielectrics prepared using various pre-deposition surface treatments are compared and discussed. This dissertation is also divided into seven chapters.
In Chapter 1, a brief overview of the background and the motivation are introduced. Three main advanced technologies for deep sub-micron MOSFETs are reviewed and we also discuss the most important issues for each technology.
In Chapter 2, the hot-electron degradation of the 0.13 µm nMOSFETs with various ultra-thin gate oxides (EOT = 1.6 nm), including thermal oxide, Si3N4/SiO2
stack, NO oxynitride, and plasma nitrided oxide, are investigated. Severe hot-electron degradations under both channel hot-electron and substrate hot-electron injections are observed for the nitrided oxide devices comparing with the thermal oxide device. We also found that the main mechanism responsible for the hot-electron degradation should be dominated by the electron trap generation rather than the interface state generation in the ultra-thin nitrided gate oxides.
In Chapter 3, we investigated the low-frequency flicker noise characteristics of the 0.15 µm nMOSFETs with ultra-thin (EOT = 1.6 nm) gate oxides of thermal oxide, Si3N4/SiO2 stack, NO oxynitride, and plasma nitrided oxide subjecting to the hot-carrier stressing and the occurrence of oxide breakdown. The nitrogen incorporation in the ultra-thin gate oxide may increase the noise level by introducing electron traps but improve the device immunity against the hot-carrier degradation in the flicker noise. Comparing with the thermal oxide device, moderate increase of the
noise level for the nitrided oxide devices is observed when oxides are suffering breakdown. We also found that the frequency index of the noise spectrum is varied with the gate bias and decreased by hot-carrier degradation and oxide breakdown.
In Chapter 4, we have fabricated the pMOSFETs with 50-nm thick strained Si0.85Ge0.15 channel and ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric and investigated the device degradations of the hot-carrier and the negative-bias temperature-instability stressing. The excellent quality of the ultra-thin N2O-annealed SiN gate dielectric is obtained. The experimental results indicate that the hot-carrier degradation is worse than the NBTI degradation and the channel hot-carrier stressing is the worst case for all kinds of reliability testing. We have also verified that the interface state generation should be the main mechanism responsible for the hot-carrier degradation while the electron trapping dominates the device degradation for the NBTI stressing.
In Chapter 5, we have fabricated the strained Si0.85Ge0.15 channel pMOSFETs with ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric and different channel thickness of 5, 15, and 30 nm. We have found that the thickness of SiGe channel has a great impact on the device characteristics. The thinner SiGe channel devices have been demonstrated to have higher interface quality, better device performance, lower leakage current, and higher mobility than the 30 nm SiGe channel device.
In Chapter 6, we have investigated the electrical characteristics of ultra-thin HfO2
gate dielectrics with various pre-deposition surface treatments, such as HF dipping, NH3 surface nitridation, and rapid thermal oxidation. The NH3 nitridation technique has been shown to be superior to other surface treatment techniques. The dependence of hysteresis on the initial inversion bias, temperature, and frequency are also investigated. The hysteresis width is found to be increased with increasing the initial inversion bias and decreased with the temperature, and it is insensitive to the
measuring frequency. The experimental results also indicate that the hysteresis width is exponentially dependent on both the initial inversion bias and the temperature and can be described by an empirical relationship in the form ( ) exp(C T ⋅ R Vv inv). The trap-assisted tunneling is also verified as the dominant conduction mechanism of the ultra-thin HfO2 gate dielectrics.
In Chapter 7, we conclude our results and summarize the main conclusions in a list, and the suggestions for further studies are also discussed.
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Chapter 2
Hot-Electron-Induced Electron Trapping in 0.13 µ m nMOSFETs with Ultra-Thin (EOT = 1.6 nm)
Nitrided Gate Oxide
2.1 Introduction
The incorporation of nitrogen into the gate oxide has become a viable approach to reduce the intolerably high standby power consumption and overcome boron penetration when the gate oxide of continues to scale down below 2 nm because it provides a physically thicker film with the same electrical equivalent oxide thickness (EOT) for reducing tunneling current and simultaneously suppressing the boron diffusion effectively [1]–[4]. In the past, a variety of techniques including thermal nitridation [5]–[17], jet vapor deposition (JVD) nitride [18]–[22], remote plasma nitridation (RPN) [23]–[28], decoupled plasma nitridation (DPN) [29], [30], and stacked nitride/oxide [31]–[40] have been studied extensively and shown to be beneficial in alleviating the above-mentioned problems. Despite these encouraging results, however, the impacts of nitrogen incorporation on the long-term reliability characteristics of the fabricated devices are still controversial. Some groups have studied that the introduction of nitrogen did cause significant reliability degradation in terms of charge trapping [41]–[45] and hot-carrier immunity[46]–[56], while the others asserted the improved robustness against hot-carrier degradation by employing various nitridation techniques [8], [57]–[69]. In this study, we demonstrate that the
gate dielectrics of 1.6nm EOT with nitrogen incorporation in deep sub-micron nMOSFETs will become less robust against hot-electron striking even though it has been shown that the ultra-thin oxides in direct tunneling regime have better hot-carrier reliability for nMOSFETs [70]–[74]. Several nitrogen incorporation techniques are employed in this work, including stacked Si3N4/SiO2 (N/O), NO annealing, and plasma nitridation. It is clearly observed that 0.13 µm nMOSFETs with ultra-thin nitrided gate oxides (EOT = 1.6 nm) depict much severe degradations under both channel hot-electron (CHE) and substrate hot-electron (SHE) injections as compared to the device with conventional ultra-thin gate oxide. Meanwhile, it is found that the main mechanism which is responsible for the hot-electron degradation should be dominated by the electron trap generation rather than the interface state generation in the ultra-thin nitrided gate dielectrics after the long-term hot-electron stressing.
2.2 Device Fabrication and Characteristics Measurement
After active region definition, wafers were split to receive various gate dielectric preparation recipes, including thermal oxidation (i.e., control), Si3N4/SiO2 (N/O) stack, NO-annealed oxide, and thermal oxide with plasma nitridation. Thermal oxide was grown by wet oxidation in catalysis oxidation chamber at 800°C; Si3N4/SiO2 stack was made of a 0.8-nm bottom thermal oxide at 800°C followed nitridation in a high-density remote helicon-based nitrogen discharge at 450°C and a 1.4-nm high-quality nitride film deposited by low-pressure chemical-vapor-deposition (LPCVD) using gas sources of SiH4 and NH3 at 800°C; NO-annealed oxide was achieved with annealing the pre-grown thermal oxide at 800°C in the NO ambient;
Plasma nitridation was implemented with exposing the thermal oxide to a decouple
plasma source at 550°C, 20 mTorr, in N2 ambient followed by rapid thermal annealing (RTA) at 1050°C for 10 seconds. All of these gate dielectrics were carefully designed to have the same equivalent oxide thickness (EOT) of approximately 1.6 nm, as identified by C–V measurements. After deposition and patterning of a 150 nm un-doped polysilicon film, arsenic dopants were implanted with the energy of 5 KeV for simultaneous gate electrode doping and shallow source/drain junction formation. For dopant activation, all wafers were annealed by
plasma source at 550°C, 20 mTorr, in N2 ambient followed by rapid thermal annealing (RTA) at 1050°C for 10 seconds. All of these gate dielectrics were carefully designed to have the same equivalent oxide thickness (EOT) of approximately 1.6 nm, as identified by C–V measurements. After deposition and patterning of a 150 nm un-doped polysilicon film, arsenic dopants were implanted with the energy of 5 KeV for simultaneous gate electrode doping and shallow source/drain junction formation. For dopant activation, all wafers were annealed by