Conduction Mechanism

The mechanisms previously reported for the leakage currents in MIS capacitors that have high-k gate dielectrics are Fowler–Nordheim tunneling (FN) [27], trap-assisted tunneling (TAT) [28], and Poole–Frenkle emission (PF) [7], [29], [30].

So far, the dominating mechanism is still an issue under debate because the conduction mechanism for the high-k films might be process dependent; this phenomenon explains why different conclusions have been drawn by different groups.

Nevertheless, we have investigated (shown in Fig. 6.10) our experimental data of leakage currents, which are temperature dependent (20–125 °C). In an attempt to clarify the dominant current conduction mechanism in our films, in Fig. 6.11 we have plotted the leakage currents as a function of reciprocal temperature for two different applied voltages. Clearly, the leakage currents are more strongly dependent on temperature at low voltage, with a weaker dependence observed at higher voltage.

This trend is quite consistent with the results described from previous studies [28].

Therefore, we believe that the conduction mechanism in our samples is also be dominated by trap-assisted tunneling (TAT) at low gate biases (Vg < 2 V).

According to the trap-assisted tunneling model in the low-voltage range [28], the gate current density should be defined by the expression

1 2

exp[( ) / ] exp( / )

g IL t a

J ∼ qV − + +φ φ φ kT ∼ −E kT (6.6) where VIL is the voltage across the interfacial layer, φ1 is the barrier height between the Si substrate and the interfacial layer, φ2 is the barrier between the interfacial layer and HfO2, φt is the effective energy of the electron traps with respect to the conduction band edge of the HfO2 layer, and Ea is the activation energy. Consequently, the effective electron trap energy, φt, can be extracted from the activation energy, which is obtained from the slope of the Arrhenius plot of the leakage current if the values of VIL, φ1, and φ2 are given.

For a stacked gate dielectric, it is well-known that

1/C_T =1/C_hk+1/C_IL (6.7) where CT is the total accumulation capacitance, Chk is the capacitance of the HfO2

film, and CIL is the capacitance of the interfacial layer. Hence, we can derive the equation layer, respectively, and thk and tIL are the thicknesses of the HfO2 and interfacial layers, respectively. The values of thk and εhk can be obtained by considering the TEM analysis, C−V measurements, and quantum mechanical effects (in our case, thk ~ 6.5 nm and εhk ~ 18). Because the stacked gate voltage, Vstack, is almost equal to the applied gate voltage, Vg, under positive bias (Vstack = Vg − Vfb − ψs ~ Vg), we can derive the voltages across the HfO2 and interfacial layers further, as follows:

1

1 where Vhk is the voltage across the HfO2 layer. As we mentioned above, the interfacial layers of the HF-dipped, NH3-annealed, and RTO-treated samples are Hf-silicate-like, SiNx, and SiO2, respectively. Therefore, the values of φ1 can be assumed to be 1.5 eV [31], 2.4 eV [32], and 3.2 eV, respectively, for these three kinds of interfacial layers.

Additionally, because the conduction band barrier height of HfO2 on an Si substrate is 1.5 eV [31], the value of φ2 can be determined by the expression φ1−1.5 eV. From Eqs.

(6.5), (6.7) and (6.9), therefore, we obtain effective electron trap energies of 0.541, 0.546 and 0.437 eV for the HF-dipped, NH3-annealed and RTO-treated samples, respectively. Table 6.2 summarizes the extracted data for all of the samples.

6.4 Summary

We have studied the influence that different pre-deposition surface treatments have on the electrical characteristics of HfO2 gate dielectrics. We have found that NH3-annealed surface treatment not only can result in a decrease in the equivalent oxide thickness but it also significantly reduces the leakage current. In contrast, the RTO-treated process is also able to reduce the leakage current, but it increases the EOT because of its greater physical thickness. We have also investigated the dependence of hysteresis on the initial inversion bias (Vinv), temperature, and frequency. Our results indicate that the hysteresis width depends exponentially on both the temperature and the initial inversion bias, but it is rather insensitive to the measuring frequency. The relationship between the reciprocal voltage constant, Rv, and the activation energy, Eh, obviously is linear, and the hysteresis of our gate

dielectrics is described well by an empirical relationship of the form ( ) exp( _{v inv})

C T ⋅ R V . In addition, we have found that the electron traps in the gate dielectrics fall in the category of slow traps and that they should play a key role in the hysteresis behavior: a large number of electron traps present in a gate dielectric results in a larger hysteresis width. Moreover, the NH3-annealed surface treatment increases the hysteresis width only slightly when compared to that of the Hf-dipped sample, while the RTO-treated sample exhibits a considerably larger hysteresis width. We believe that more electron traps exist at the inner-interface between the HfO2 and SiO2

layers. Finally, we have observed that the leakage currents exhibit a stronger temperature dependence at low voltage than they do at higher voltage. Therefore, we believe that the conduction mechanism for each sample at a low gate bias is dominated by trap-assisted tunneling. We have also extracted the corresponding parameters for the TAT model and have presented the data for all splits. In conclusion, we believe that surface nitridation is the most promising method of pre-deposition surface treatment of HfO2 gate dielectrics for improving the electrical characteristics in terms of EOT, leakage current, and hysteresis.

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Table 6.1. Values of A, B, ln(A/B), Rv, and Eh under the conditions of Vinv = +3 V at T

= 300 K. The terms A and B are proportionality constants, Rv is the reciprocal voltage constant, and Eh is the activation energy.

Eh = 0.026ln(A/B) + 0.078Rv

Surface

Treatments A B ln(A/B) Rv (1/V) Eh (eV)

HF-dipped 0.150 8.74 × 10^–3 2.843 0.274 0.095

NH3-annealed 0.151 1.40 × 10^–2 2.378 0.336 0.088

RTO-treated 0.200 2.15 × 10^–2 2.230 0.435 0.092

Table 6.2. Values of Ea, qVIL, φ1, φ2, and φt for all samples at Vg = +1 V. The term Ea is the activation energy, VIL is the voltage across the interfacial layer, φ1 is the barrier height between the Si substrate and the interfacial layer, φ2 is the barrier between the interfacial layer and HfO2, and φt is the effective energy of the electron traps with respect to the conduction band edge of the HfO2 layer.

Ea = −(qVIL−φ1 + φ2 + φt) (eV) Surface

Treatments Ea qVIL φ1 φ2 φt

HF-dipped 0.384 0.575 1.5 0.0 0.541

NH3-annealed 0.405 0.549 2.4 0.9 0.546

RTO-treated 0.433 0.630 3.2 1.7 0.437

Fig. 6.1. TEM pictures of the cross sections for the HfO2 films with different surface treatments. (a) HF-dipped. (b) NH3-annealed. (c) RTO-treated.

5 nm

HfO2

IL

(a) HF-dipped

5 nm

HfO2

IL

(b) NH3-annealed

5 nm

HfO2

IL

(c) RTO-treated

Fig. 6.2. The XPS spectra of the HfO2 films with different surface treatments.

Binding Energy (eV)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Count (a.u.)

HF-dipped NH

₃

-annealed RTO-treated

Hf 4f

Fig. 6.3. The capacitance−voltage (C−V) characteristics of NMIS capacitors prepared by applying the three different surface treatment processes. The equivalent oxide thickness (EOT) was determined by measuring the maximum accumulation capacitance.

Gate Voltage, V

_g

(V)

-3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0

Capacitance (pF)

0 1 2 3 4

5 HF-dipped, EOT=3.4nm

NH

₃

-annealed, EOT=3.2nm RTO-treated, EOT=3.9nm

Area=4x10

^-6

cm

²

ideal V

_fb

Fig. 6.4. The plot of the leakage current as a function of gate voltage for each sample.

Gate Voltage, V

_g

(V)

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

Current Density, J

g

(A /cm

2

)

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

HF-dipped

NH

₃

-annealed

RTO-treated

Fig. 6.5. The cumulative distribution of leakage currents at Vg = −2.5 V for capacitors formed by using the three different surface treatment processes.

J

_g

@V

_g

=-2.5V (A/cm

²

)

10

^-6

10

^-5

10

^-4

10

^-3

Cumulative Probability (%)

1 10 30 50 70 90 99 99.9

HF-dipped

NH

₃

-annealed

RTO-treated

Fig. 6.6(a). Normalized C−V curves with different sweeping voltages for the HF-dipped sample. The initial inversion biases (Vinv) are +1, +2, and +3 V, and the accumulation bias (Vacc) is −3 V.

Gate Voltage, V

_g

(V)

-3 -2 -1 0 1 2 3

Normalized Capacitance, C/C

max

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

V

_inv

=1V, V

_acc

=-3V V

_inv

=2V, V

_acc

=-3V V

_inv

=3V, V

_acc

=-3V HF-dipped

∆V

_fb

<0.35V

Fig. 6.6(b). Normalized C−V curves with different sweeping voltages for the NH3-annealed sample. The initial inversion biases (Vinv) are +1, +2, and +3 V, and the accumulation bias (Vacc) is −3 V.

Gate Voltage, V

_g

(V)

-3 -2 -1 0 1 2 3

Normalized Capacitance, C/C

max

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

V

_inv

=1V, V

_acc

=-3V V

_inv

=2V, V

_acc

=-3V V

_inv

=3V, V

_acc

=-3V NH

₃

-annealed

∆V

_fb

<0.4V

Fig. 6.6(c). Normalized C−V curves with different sweeping voltages for the RTO-treated sample. The initial inversion biases (Vinv) are +1, +2, and +3 V, and the accumulation bias (Vacc) is −3 V.

Gate Voltage, V

_g

(V)

-3 -2 -1 0 1 2 3

Normalized Capacitance, C/C

max

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

V

_inv

=1V, V

_acc

=-3V V

_inv

=2V, V

_acc

=-3V V

_inv

=3V, V

_acc

=-3V RTO-treated

∆V

_fb

<0.8V

Fig. 6.7. The dependence of hysteresis width on the inversion bias (Vinv) during C−V measurement. The reciprocal voltage constant (Rv) is obtained from the slope of the fitted line.

Initial Inversion Bias, V

_inv

(V)

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

Hysteresis (V)

0.1 1 10

Hysteresis=Ae

^RvVinv

R

_v

=0.274 R

_v

=0.336 R

_v

=0.435 HF-dipped

NH

₃

-annealed

RTO-treated

Fig. 6.8. The plot of hysteresis as a function of the reciprocal of temperature. The activation energy (Eh) for each sample is ca. 0.092 eV.

1/kT (eV)

^-1

26 28 30 32 34 36 38 40 42 44 46 48

Hysteresis (V)

0.01 0.1 1 10

Hysteresis=Be

^Eh/kT

HF-dipped

NH

₃

-annealed

RTO-treated

E

_h

~0.092eV

Fig. 6.9. The plot of hysteresis as a function of the C−V measuring frequency.

Frequency (Hz)

10

³

10

⁴

10

⁵

10

⁶

10

⁷

Hysteresis (V)

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

HF-dipped

NH

₃

-annealed

RTO-treated

Fig. 6.10(a). The plot of leakage current as a function of gate voltage for the HF-dipped sample as the temperature was varied from 20 to 125 °C.

Gate Voltage, V

_g

(V)

0.0 0.5 1.0 1.5 2.0 2.5

Current Density, J

g

(A /cm

2

)

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

HF-dipped

T=20

^o

C

T=125

^o

C

Fig. 6.10(b). The plot of leakage current as a function of gate voltage for the NH3-annealed sample as the temperature was varied from 20 to 125 °C.

Gate Voltage, V

_g

(V)

0.0 0.5 1.0 1.5 2.0 2.5

Current Density, J

g

(A /cm

2

)

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

NH

₃

-annealed

T=20

^o

C

T=125

^o

C

Fig. 6.10(c). The plot of leakage current as a function of gate voltage for the RTO-treated sample as the temperature was varied from 20 to 125 °C.

Gate Voltage, V

_g

(V)

0.0 0.5 1.0 1.5 2.0 2.5

Current Density, J

g

(A /cm

2

)

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

RTO-treated

T=20

^o

C

T=125

^o

C

Fig. 6.11. The Arrhenius plot of leakage currents at Vg = 1.0 V and Vg = 2.5 V. The activation energy (Ea) increases as the temperature decreases.

1000/T (1/K)

2.0 2.5 3.0 3.5 4.0

Current Density, J

g

(A/cm

2

)

10

^-8

10

^-7

10

^-6

10

^-5

10

^-4

10

^-3

10

^-2

J

_g

@2.5 V E

_a

~0.318 eV

E

_a

~0.343 eV E

_a

~0.331 eV

J

_g

@1.0 V E

_a

~0.384 eV

E

_a

~0.433 eV E

_a

~0.405 eV HF-dipped

NH

₃

-annealed

RTO-treated

Chapter 7

Conclusions and Suggestions for Further Study

7.1 Conclusions

We have investigated the hot-carrier degradation, reliability, and flicker noise characteristics of the deep sub-micron nMOSFETs with various ultra-thin (EOT = 1.6 nm) gate oxides, including thermal oxide, Si3N4/SiO2 stack, NO oxynitride, and plasma nitrided oxide. Next, the reliability and the channel thickness effect of the deep sub-micron pMOSFETs with ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric and strained Si0.85Ge0.15 channel have been studied. Finally, we have also investigated the electrical characteristics of the ultra-thin HfO2 gate dielectrics with different pre-deposition surface treatments of HF dipping, NH3 nitridation and RTO annealing. In conclusion, we summarize the results and discussions in the following list.

For the deep sub-micron nMOSFETs with various ultra-thin (EOT = 1.6 nm) gate oxides:

1. Nitrogen incorporation into ultra-thin gate oxide could reduce gate leakage current effectively, but it also introduces the positive oxide charges to cause threshold voltage shift and transconductance degradation and induces the electron traps to enhance the flicker noise.

2. The nitrided oxides result in enhanced hot-electron-induced device degradations, such as significant threshold voltage shift, transconductance

degradation, and drain current reduction comparing with the thermal oxide.

The electron trap generation rather than the interface state generation should be the main mechanism of the hot-electron degradation for the deep sub-micron nMOSFET with ultra-thin (EOT = 1.6 nm) nitrided gate oxide because of the observations of the positive shift of threshold voltage, the insignificant variation of subthreshold swing, the reduction of gate leakage current, no significant slope changes of the Ib-Vcb curves for DCIV measurement, and a small exponent value (n ~ 0.3) of the ∆Vt versus stress time plot after the hot-carrier stressing. Therefore, the hot-electron-induced electron trapping in the ultra-thin nitrided gate oxide could eventually become a severe long-term reliability concern (CHE and SHE) for the sub-100nm technologies.

3. The low-frequency flicker noise is mainly generated by electron trapping/detrapping with the interface states and the electron traps. Because of the electron traps induced by incorporating nitrogen into oxide, the nitrided oxides demonstrate a higher flicker noise than the thermal oxide. However, nitrogen incorporation can improve the device immunity against the hot-carrier degradation in the flicker noise since the hot-electron-induced electron trapping may suppress the generation of flicker noise. On the other hand, a considerable amount of electron traps are created to enhance the flicker noise when oxide breakdown is occurred, and moderate increase of noise level is observed for the nitrided oxide as compared with the thermal oxide.

4. The frequency index of noise spectrum is varied with the gate bias and it is strong related to the oxide traps. Moreover, the frequency index will be lowered by hot-carrier degradation and even worse by oxide breakdown for

both thermal oxide and nitrided oxide devices.

5. For considering the hot-carrier reliability and the characteristics of flicker noise, the plasma nitridation should be the most promising technique for the ultra-thin nitrided gate oxide applications, and the plasma nitrided oxide should be the promising candidate of the ultra-thin nitrided oxide for sub-100 nm MOSFET devices in analog and RF applications.

For the deep sub-micron pMOSFETs with ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric and strained Si0.85Ge0.15 channel:

1. A good quality of gate dielectric can be obtained by the N2O-annealed SiN film because no significant as-deposited oxide traps are observed in the N2O-annealed SiN gate dielectric. The conduction mechanism responsible for the gate leakage current should be dominated by the FN tunneling with an effective barrier height of 1.8 eV. Moreover, the strained SiGe channel device with ultra-thin N2O-annealed SiN gate dielectric shows well-performed on/off and output characteristics.

2. Insignificant degradation has been found when the capacitors with ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric are stressed under the constant voltage (or current) stressing. The polarity dependence of SILC reveals that the oxide traps generated during the stressing process should be more close to the gate electrode.

3. The device reliability of hot-carrier degradation and NBTI stressing has been investigated. The hot-carrier degradation is more severe than the NBTI stressing and the channel-hot-carrier stressing is regarded as the worst case of device degradation. According to the power law relationship of ∆Vt versus stress time as well as the results of charge pumping measurement, the interface

state generation should be the predominant factor for the HC degradation while the electron trapping may dominate the degradation of device characteristics for the NBTI stressing. On the other hand, although the electron trapping occurs at the initial stage of the high voltage CHC stressing, the hole trapping eventually dominates the degradation when the device is stressed for a longer time.

4. To investigate the channel thickness effect of the strained Si0.85Ge0.15

pMOSFETs with ultra-thin N2O-annealed SiN gate dielectric, the devices with various SiGe channel thickness of 5, 15, and 30 nm have been fabricated. A thin gate dielectric with EOT of 3.1 nm and an excellent subthreshold swing of 68 mV/dec are obtained for the devices with 5 and 15 nm SiGe channel, and the density of interface state and dislocation are also even lower than that of the 30 nm SiGe channel device because of their lower GIDL and junction leakage currents.

5. Comparing with the thinner SiGe channel devices, the 30 nm SiGe channel device degrades the transconductance at low gate voltages because of its higher density of interface state and dislocation and improves, however, the transconductance at high gate bias because of the screening effect on the surface scattering. On the other hand, all SiGe channel pMOSFETs, comparing with the Si channel device, show the enhancement in the effective hole mobility which is due to the compressive strain and the quantum confinement effect of the strained SiGe channel.

6. The pMOSFETs with thin (<30 nm) SiGe channel and ultra-thin N2O-annealed SiN gate dielectric are well-performed and show their potential for the advanced sub-100 nm device technology and applications.

在文檔中 具有超薄高介電常數閘極介電層與應變矽鍺通道之先進深次微米金氧半場效電晶體研究 (頁 165-0)