HC and NBTI Stressing for pMOSFETs

Figure 4.10 displays the degradation of drain currents (∆Id) versus stress time when devices are stressed with the hot-carrier (stressed at Vg=Vd, the channel-hot-carrier (CHC), and Vg=2Vd/3, the drain-avalanche-hot-carrier (DAHC)) and the negative-bias-temperature- instability (stressed at room temperature (RT) and 100 ºC) stressing. Obviously, the degradation of HC stressing is much severe than that of NBTI stressing, and the CHC stressing has been shown to be the worst case.

Similar results, as shown in Fig. 4.11, are also observed for the degradation of transconductance (∆Gm). Because the trends of ∆Id and ∆Gm are almost identical, the same mechanism should be responsible for the hot-carrier degradations of drain current and transconductance. However, the variations both for Id and Gm are moderate when the devices are stressed with the NBTI stressing at 100 ºC as compared with the counterparts at room temperature. This can be explained by the self-recovery effect of the high temperature NBTI degradation [29]. Moreover, the shift of threshold voltages (∆Vt) with the stress time is plotted in Fig. 4.12.

Interestingly, all values of ∆Vt are positive for all stressing conditions and follow a power law with the stress time in the form of ∆Vt =Atⁿ, indicating that electron trapping in the gate dielectric and/or at the interface is occurred during the stressing

process. According to the previous report [30], for a small value of n (n < 0.2) means that the degradation of Vt should be dominated by the electron trapping in the gate oxide while ∆Vt should be caused by the interface state generation for a large value of n (n > 0.3 in our case). Therefore, we believe that the interface state generation is responsible for the hot-carrier degradation and the electron trapping in the gate dielectric dominates the NBTI reliability degradation for the pMOSFET with Si0.85Ge0.15 channel and N2O-annealed SiN gate dielectric.

The interface state density variation accompanying with stressing using the charge pumping (CP) technique are shown in Fig. 4.13. The charge pumping currents (ICP) are increased after the devices are stressed, and this confirms the generation of excess interface states. In addition, Fig. 4.14, the enlargement of Fig. 4.13, also depicts slightly positive shifts of the ICP curves. Again, the occurrence of electron trapping which has been observed after stressing is obviously consistent with the results of ∆Vt. Comparing the interface state generation (∆Nit) for all stressing conditions in Fig. 4.15, the hot-carrier stressing, especially the CHC stressing, shows higher ∆Nit than the NBTI stressing. It demonstrates that the generated interface states play the most important role in the hot-carrier degradation for the device reliability. Nevertheless, it is worth to notice that the result of charge pumping measurement for the NBTI stressing at 100 ºC is not shown here because of its insignificant degradation due to the self-recovery effect.

The degradations for the different bias conditions of Vg = Vd = –4.5, –5, and –5.3 V were further investigated even though the CHC stressing has been shown to be the worst case for the hot-carrier degradation. The results of ∆Id, ∆Gm, and ∆Vt are shown in Fig. 4.16, Fig. 4.17, and Fig. 4.18, respectively. Although the drain currents are degraded with increasing the stressing time and applying voltages, the ∆Gm tends to saturate when the device was stressed under higher voltages for a longer time. It is

quite different from the case of stressing at Vg = Vd = –4.5 V which the degradations of Id and Gm are increased monotonically with the stress time. From the shifts of threshold voltage induced by the hot-carrier stressing as well as the results shown in Fig. 4.16, positive shifts of Vt are only occurred at the beginning for the stressing voltages of –5 and –5.3 V and then the ∆Vt tends to be negative. It means that the electron trapping dominates the device degradation at the initial stage of the channel-hot-carrier stressing and then the hole trapping is enhanced to mainly degrade the device characteristics for a longer time stressing [31], [32].

4.4

Summary

We have successfully fabricated pMOSFETs with selectively 50 nm epitaxial Si0.85Ge0.15 channel and ultra-thin (EOT = 3.1 nm) N2O-annealed SiN gate dielectric.

No significant as-deposited oxide traps have been observed in the N2O-annealed SiN gate dielectric and the FN tunneling has been demonstrated as the conduction mechanism responsible for the gate leakage current with an effective barrier height of 1.8 eV. Besides, the device also shows well-performed on/off and output characteristics. For the reliability concern, insignificant degradation has been found when the capacitors were stressed under the constant voltage (or current) stressing.

This means that a good quality of gate dielectric can be obtained by the N2O-annealed SiN film. On the other hand, the polarity dependence of SILC reveals that the oxide traps generated during the stressing process should be more close to the gate electrode.

Moreover, we have studied the effect of hot-carrier and negative-bias-temperature instability stressing on the SiGe channel pMOSFETs with ultra-thin N2O-annealed SiN gate dielectric. It is found that the hot-carrier degradation is more severe than the NBTI degradation and the channel-hot-carrier stressing is regarded as the worst case

of device degradation. According to the power law relationship of ∆Vt versus stress time as well as the results of charge pumping measurement, we have demonstrated that the interface state generation is the predominant factor for the HC degradation while the electron trapping dominates the degradation of device characteristics for the NBTI stressing. Although the electron trapping has been found to occur at the initial stage of the high voltage CHC stressing, the hole trapping will eventually dominate the degradation when the device is stressed for a longer time.

References

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Vainonen-Ahlgren, W.-M. Li, E. Tois, and M. Tuominen,“A novel strained Si0.7Ge0.3 surface-channel pMOSFET with an ALD TiN/Al2O3/HfAlOx/Al2O3

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T. Onai, J. Yugami, and S. Kimura, “Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics,” Proc. Int. Reliability Physics Symp., p. 183, 2003.

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Electron Devices, vol. 42, p. 109, 1995.

Fig. 4.1. The schematic device cross-section and process flow of device fabrication.

LOCOS Isolation

UHVCVD Selective In-Situ Doped Epitaxy Si

_0.85

Ge

_0.15

Channel

LPCVD SiN Deposition RTA N

₂

O-Annealing

LPCVD Undoped Poly-Si Deposition Source/Drain Formation

RTA Dopant Activation

Contact and Metallization

Forming Gas Annealing

Fig. 4.2. The capacitance–voltage (C–V) characteristics of the pMOSFET with 50 nm Si0.85Ge0.15 channel and N2O-annealed SiN (EOT=3.1 nm) gate dielectric. The equivalent oxide thickness (EOT) of 3.1 nm is extracted from the accumulation capacitance.

Gate Voltage, V

_g

(V)

-3 -2 -1 0 1 2 3

Capacitance (pF)

3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6

inv-to-acc acc-to-inv W/L=20/20 µm

100 kHz

EOT=3.1 nm

pMOSFET

Fig. 4.3. The current–voltage (I–V) characteristics of the pMOSFET with 50 nm Si0.85Ge0.15 channel and N2O-annealed SiN (EOT=3.1 nm) gate dielectric. The inset shows the fitting of Fowler-Nordheim (FN) tunneling with an effective barrier height of 1.8 eV.

Gate Voltage, V

_g

(V)

-4 -3 -2 -1 0 1 2 3 4

Current Density, J

g

(A /cm

2

)

10

^-9

10

^-8

10

^-7

10

^-6

10

^-5

pMOSFET

1/Ε_ox (MV/cm)^-1

0.080 0.085 0.090 0.095 0.100

ln(J g/Ε ox2 )

e^-22 e^-21 e^-20 e^-19 e^-18

φ

_B

=1.8 eV F-N tunneling

W/L=20/20 µm

Fig. 4.4. The Id–Vg and Gm characteristics of SiGe pMOSFET (W/L=10/0.5 µm) with N2O-annealed SiN gate dielectric.

Gate Voltage, V

_g

(V)

Fig. 4.5. The Id–Vd characteristics of SiGe pMOSFET (W/L=10/0.5 µm) with N2O-annealed SiN gate dielectric with various gate overdrives (Vg–Vt) from 0 to –2 V.

Drain Voltage, V

_d

(V)

-4 -3 -2 -1 0

Drain Current, I

d

( µA)

0 100 200 300 400 500

V

_g

-V

_t

=-2 V

W/L=10/0.5 µm pMOSFET

V

_g

-V

_t

=-1.5 V

V

_g

-V

_t

=-1 V

V

_g

-V

_t

=-0.5 V

V

_g

-V

_t

=0 V

Fig. 4.6. The C–V characteristics of SiGe pMOSCAP with N2O-annealed SiN gate dielectric for various CVS conditions.

Gate Voltage, V

_g

(V)

-4 -3 -2 -1 0 1 2 3 4

Normalized Capacitance

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

Fresh

V

_g

=5V, 3000 s inv-to-acc

V

_g

=5 V, 3000 s acc-to-inv

V

_g

=5.3 V, 3000 s V

_g

=-5 V, 3000 s

100x100 µm

²

100 kHz

pMOSCAP

Fig. 4.7. The leakage current versus the stress time of SiGe pMOSCAP with N2O-annealed SiN gate dielectric under the constant voltage stress (CVS).

Gate Voltage, V

_g

(V)

-4 -3 -2 -1 0 1 2 3 4

Current Density, J

g

(A/cm

2

)

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

Fresh

V

_g

=5 V, 10 s V

_g

=5 V, 100 s V

_g

=5 V, 1000 s V

_g

=5 V, 3000 s V

_g

=5.3 V, 3000 s

100x100 µm

²

pMOSCAP

Fig. 4.8. The C–V characteristics of SiGe pMOSCAP with N2O-annealed SiN gate dielectric for various CCS conditions.

Gate Voltage, V

_g

(V)

-4 -3 -2 -1 0 1 2 3 4

Normalized Capacitance

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

1.2 Fresh

J

_g

=0.01 mA/cm

²

, 3000 s, inv-to-acc J

_g

=0.01 mA/cm

^2,

3000 s, acc-to-inv J

_g

=0.02 mA/cm

²

, 3000 s

J

_g

=-0.01 mA/cm

²

, 3000 s

pMOSCAP

100x100 µm

²

100 kHz

Fig. 4.9. The leakage current versus the stress time of SiGe pMOSCAP with N2O-annealed SiN gate dielectric under the constant current stress (CCS).

Gate Voltage, V

_g

(V)

-4 -3 -2 -1 0 1 2 3 4

Current Density, J

g

(A/cm

2

)

10

^-10

10

^-9

10

^-8

10

^-7

10

^-6

Fresh

Jg=0.01 mA/cm

²

, 10 s Jg=0.01 mA/cm

²

, 100 s Jg=0.01 mA/cm

²

, 1000 s Jg=0.01 mA/cm

^2,

3000 s Jg=0.02 mA/cm

²

, 3000 s

100x100 µm

²

pMOSCAP

Fig. 4.10. The Id degradation versus the stress time of HC and NBTI stressing for the SiGe pMOSCAP with N2O-annealed SiN gate dielectric.

Stress Time (s)

10

¹

10

²

10

³

10

⁴

Drain Current Degradation, ∆ I

d

/|I

d

| (%)

-3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5

pMOSFET

V

_d

=-4.5 V

W/L=10/0.5 µm

CHC

DAHC

NBTI-RT

NBTI-100

^o

C

Fig. 4.11. The Gm degradation versus the stress time of HC and NBTI stressing for the SiGe pMOSCAP with N2O-annealed SiN gate dielectric.

Stress Time (s)

10

¹

10

²

10

³

10

⁴

Transconductance Degradation, ∆ G

m

/|G

m

| (%)

-50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0

5 pMOSFET

V

_d

=-4.5 V

W/L=10/0.5 µm

CHC

DAHC

NBTI-RT

NBTI-100

^o

C

Fig. 4.12. The threshold voltage shift (∆Vt) versus the stress time for the SiGe pMOSCAP with N2O-annealed SiN gate dielectric.

Stress Time (s)

10

¹

10

²

10

³

10

⁴

Threshold Voltage Shift, ∆ V

t

(V )

0.001 0.01 0.1 1

pMOSFET V

_d

=-4.5 V

∆V

_t

=At

ⁿ

W/L=10/0.5 µm CHC (n=0.32)

DAHC (n=0.34)

NBTI-RT (n=0.13)

NBTI-100

^o

C (n=0.08)

Fig. 4.13. The charge pumping currents of the devices before and after being stressed at HC and NBTI (RT) stressing.

V

_g,peak

(V)

-4 -3 -2 -1 0

Charge Pumping Current, I

CP

(nA)

-9

Fig. 4.14. The enlargement of the charge pumping currents shown in Fig. 4.13.

V

_g,peak

(V)

-1.5 -1.4 -1.3 -1.2 -1.1 -1.0

Charge Pumping Current, I

CP

(nA)

-9

Fig. 4.15. Comparison of the interface state generation (∆Nit) which are extracted from the increase of charge pumping currents for the HC and NBTI (RT) stressing.

Stress Conditions

CHC DAHC NBTI-RT

Interface S tates Incresment, ∆ N

it

(10

9

cm

-2

)

-5 0 5 10 15 20 25 30 35

W/L=10/2 µm pMOSFET

V

_d

=-4.5 V, 3000 s

Fig. 4.16. The Id degradation versus the stress time for the channel-hot-carrier stressing under various bias conditions of Vg = Vd = –4.5, –5, and –5.3 V.

Stress Time (s)

10

¹

10

²

10

³

10

⁴

Drain Current Degradation, ∆ I

d

/|I

d

| (%)

-10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1

W/L=10/0.5 µm pMOSFET

V

_g

=V

_d

=-4.5 V V

_g

=V

_d

=-5 V V

_g

=V

_d

=-5.3 V

CHC

Fig. 4.17. The Gm degradation versus the stress time for the channel-hot-carrier stressing under various bias conditions of Vg = Vd = –4.5, –5, and –5.3 V.

Stress Time (s)

10

¹

10

²

10

³

10

⁴

Transconductance Degradation, ∆ G

m

/|G

m

| (%)

-80 -70 -60 -50 -40 -30 -20 -10 0 10

W/L=10/0.5 µm pMOSFET

V

_g

=V

_d

=-4.5 V

V

_g

=V

_d

=-5 V

V

_g

=V

_d

=-5.3 V

CHC

Fig. 4.18. The threshold voltage shift (∆Vt) versus the stress time for the channel-hot-carrier stressing under various bias conditions of Vg = Vd = –4.5, –5, and –5.3 V.

Stress Time (s)

10

¹

10

²

10

³

10

⁴

Threshold Voltage Shift, ∆ V

t

(V)

-0.15 -0.10 -0.05 0.00 0.05 0.10

0.15 pMOSFET W/L=10/0.5 µm

V

_g

=V

_d

=-4.5 V V

_g

=V

_d

=-5 V V

_g

=V

_d

=-5.3 V

CHC

Chapter 5

Channel Thickness Effect on Strained SiGe Channel pMOSFETs with Ultra-Thin (EOT = 3.1

nm) N

₂

O-Annealed SiN Gate Dielectric

5.1 Introduction

To enhance the performance of pMOSFETs, the silicon germanium (SiGe) layer has been introduced into the channel of pMOSFETs because (a) it has higher bulk carrier mobility than that of bulk Si, (b) the offset of valence band between SiGe and Si substrate leads to the quantum confinement effect of holes which also contributes the increase of hole mobility [1], and (c) the hole mobility is further enhanced when the SiGe layer is deposited on top of Si substrate due to the induced compressive strained in the SiGe channel [2], [3]. Although the SiGe channel devices have abovementioned advantages, however, the gate oxide formed by the conventional thermal oxidation process will cause Ge precipitates at the interface between SiGe and oxide, which will deteriorate the quality of gate oxide [4]. Therefore, one appreciable approach to prepare the gate dielectric for SiGe channel devices is using the deposition technique at lower temperature which can also prevent the relaxation of the strained SiGe layer. Recently, the ultra-thin silicon nitride (SiN) has been reported as the possible alternative of gate dielectrics for the SiGe channel pMOSFETs [4], [5]

owing to the advantages of suppressing the boron penetration, a larger dielectric constant, and better hot-carrier hardness [6]. Unfortunately, SiN films usually contain

a large amount of fixed oxide charges, which can cause the threshold voltage shift, and increase the interface state density to degrade the device performance [7]. Hence, N2O-annealing has been reported to improve the qualities of the SiN layer and the SiN/Si interface by forming an oxygen-enriched interface (OI-SiN) [8]. In this paper, we employed the low temperature (800 ºC) N2O-annealed SiN gate dielectric for fabricating the SiGe channel pMOSFETs. According to the results of electrical characteristics, we found an excellent interface quality, a considerably low subthresthold swing, and significant hole mobility improvement can be achieved for the SiGe channel pMOSFETs with the ultra-thin N2O-annealed SiN gate dielectric.

5.2 Device Fabrication and Characteristics Measurement

The devices were fabricated on 6-inch (100) orientated Si wafers. After the standard LOCOS isolation being fabricated, the Si0.85Ge0.15 epitaxial layers with various thicknesses of 5, 15 and 30 nm were selectively deposited on top of the Si substrates by ultra-high vacuum chemical vapor deposition (UHVCVD) at 550 ºC.

The SiGe layers were in-situ doped with phosphorus and the doping concentrations were 9×10¹⁷, 1×10¹⁸, and 4×10¹⁸ cm^-3 for the thickness of 5, 15, and 3 nm, respectively according to the results of SIMS analysis shown in Fig. 5.1. After being cleaned by RCA process, the ultra-thin SiN gate dielectrics were deposited by low pressure CVD (LPCVD) furnace with dichlorosilane (DCS) and NH3 at 780 ºC, and the rapid thermal annealing (RTA) at 800 ºC for 30 seconds in N2O ambience immediately followed. The undoped 150 nm poly-Si deposition were performed by LPCVD furnace with silane (SiH4) at 620 ºC and patterned by using lithography and etching process as the gate electrode. Then, the self-aligned source/drain extension

was implanted with BF2 by a dosage of 1×10¹⁴ cm^-2 at 10 keV. An oxide spacer was formed by etching isotropically the low temperature TEOS oxide (LTO), and the self-aligned gate and source/drain implantation were performed by implanting BF2

with a dosage of 5×10¹⁵ cm^-2 at 20 keV. After the substrate contact being defined and implanted to improve the body contact, the dopant activation by RTA at 900 ºC in N2

ambience for 30 seconds was carried out. Then, the devices were passivated with 500 nm LTO oxide followed by a standard back-end-of-line (BEOL) contact and metallization processes. Finally the devices were annealed in a furnace with the forming gas at 400 ºC for 30 minutes before the electrical characteristics measurements.

The capacitance−voltage (C−V) characteristic of each capacitor was measured using an HP4284 LCR meter. The equivalent oxide thickness (EOT) of the gate dielectrics was obtained from the strong accumulation capacitance (EOT=εSiO₂/Cacc).

The current−voltage (I−V) characteristics were measured by using a Keithley 4200 semiconductor characterization system.

5.3 Results and Discussion

Figure 5.2 shows the C–V characteristics of pMOSFETs with different strained SiGe channel thickness. The smaller value EOT of approximately 3.1 nm was obtained for the devices with thinner SiGe channels of 5 and 15 nm. The 30 nm SiGe channel device, however, depicts higher EOT value (3.5 nm). It is speculated that the faster deposition rate of SiN layer may be induced by the poor quality and/or the high strain energy of a thicker SiGe channel. In addition, the distortion of C–V curve for

the 30 nm SiGe channel device indicates more interface states did exist at the SiN/SiGe channel interface, and the shift of flat-band voltage (Vfb) is probably not only due to the higher oxide charges and interface states but also due to a slightly heavier doping concentration in the thicker SiGe channel which was evidenced by the SIMS profiles.

The Id–Vg and Id–Vd characteristics are shown in Fig. 5.3 and Fig. 5.4. The threshold voltages of the devices with thinner strained SiGe channel (5 and 15 nm) are almost identical and they are smaller than that of the 30 nm SiGe channel device because of their smaller Vfb and lighter channel doping concentration. In addition, the subthreshold swing of as low as 68 mV/dec can also be realized in the devices with 5 and 15 nm stained SiGe channel. As strained SiGe channel increases up to 30 nm, the subthreshold swing increases drastically. On the other hand, the thin SiGe channel devices demonstrate higher driving currents than the 30-nm SiGe channel device for various overdrive gate biases (Vg–Vt) as well as Fig. 5.4 shows. Figure 5.5 depicts the results of charge pumping measurement for extracting the interface state density (the extracted interface state density is shown in Fig. 5.6). Obviously, the charge pumping current (Icp) of the 30-nm SiGe channel device is much higher than that of the counterparts, and it means that the 30-nm SiGe channel device has a poor interface because the charge pumping current is proportional to the amount of interface states.

The negative shift of the Icp for the 30-nm SiGe channel device also indicates that positive charges are induced in the gate dielectric. These results are consistent with the information obtained from the C–V and Id–Vg curves for the 30-nm SiGe channel device. Figure 5.6 illustrates the comparison of the interface state density (Nit) extracted by charge pumping technique and the subthreshold swing (S) for all samples.

From the Icp data previously shown in Fig. 5.5, it is expected that the device with 30 nm SiGe channel may show nearly one order of magnitude higher Nit than the other

devices. Besides, Nit and S show almost identical trends, and this is in a good agreement with the well-known results, i.e. the lower the interface state density, the lower the subthreshold swing. We believe that the significant increases in subthreshold swing and the interface state density should come from the increase of the dislocation density in the devices with 30 nm SiGe channel thickness [9].

Therefore, we can conclude that with the combination of the sufficiently thin (<30 nm)

Therefore, we can conclude that with the combination of the sufficiently thin (<30 nm)

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