CHE and SHE Stressing

For the deep sub-micron devices with conventional ultra-thin gate oxide, it has been shown that the worst hot-carrier stress condition switches from Vg = Vd/2 (maximum Isub) to Vg = Vd [103]–[107], and the device degradation is also enhanced by the valence-band electron tunneling when the oxide thickness shrinks down to the direct tunneling regime [105]. For the 0.13 µm nMOSFETs with ultra-thin nitrided gate oxides, as shown in Fig. 2.4, similar flat curves of substrate current versus gate voltage (Ib–Vg) are also obtained, so the worst condition of Vg = Vd was used to monitor the degradations of our devices for hot-carrier stressing. Although the interface state generation has been demonstrated to be the main cause of the hot-carrier degradation for ultra-thin gate oxide devices [72], [104], [105], [108], the situation is, however, quite different for the devices with ultra-thin nitrided gate dielectrics. Figure 2.5 indicates that almost no degradation was observed for the thermal oxide device with an EOT value of 1.6 nm, and this result is consistent with the previous works [70]–[74]. On the other hand, a slightly larger increase of threshold voltage (∆Vt = 6 mV) is presented even though almost unchanged subthreshold swing was also observed for the plasma nitrided oxide device after being stressed under Vg = Vd = 1.8 V (CHE) for 10⁴ seconds. According to the results that nitrided oxide is very resistive to the interface state generation [47], [49], [52]–[54], [57]–[59], [62], [63], [67], we, then, speculate that the electron trapping should be the dominating mechanism of the hot-electron degradation for the ultra-thin nitrided oxide device. Moreover, Fig. 2.6 displays that the gate leakage current of the plasma nitrided oxide is slightly decreased after the CHE stressing. This trend is opposite to the results shown in other works, in which the increase of gate current has been

demonstrated if the gate oxide and the interface are damaged [74], [106], [108]–[115].

Therefore, the reduction of gate leakage current is believed to be due to the local electric field lowering induced by the electrons trapped in the gate dielectric [109], [116].

Figure 2.7 depicts the ∆Vt and ∆Gm/Gm versus gate voltage as a function of substrate bias (Vsub) under SHE stressing for the 0.13 mm nMOSFET with plasma nitrided gate oxide. We can clearly see that only negligible degradation has been found even when the gate voltage is up to 2.6 V when Vsub was fixed at 0 V (i.e.

constant voltage stress, CVS). For the case of SHE stressing under Vsub = −2 V, however, the ∆Vt as well as ∆Gm/Gm are significantly enhanced with the increase of gate voltage. Note that the channel of device is strongly inverted for all applied gate voltages (Vg > Vt = 0.38 V). Thus, the electron injection into the gate dielectric which degrades threshold voltage (positive shift) and transconductance should be dominated by the substrate bias rather than the gate voltage. These results imply that the degradation must be strongly related to the energy of electrons flowing through the gate dielectric because electrons will gain energy from the substrate bias injection.

Interestingly, Vt and Gm degradations are shown in a similar trend which indicates that Vt shift and Gm reduction may be enhanced by the same degradation mechanism, i.e.

the electron trapping in the gate dielectric. In addition, the shifts of threshold voltage as a function of substrate bias under SHE stressing for various gate dielectrics are shown in Fig. 2.8. It can be seen that nitrogen-incorporated gate dielectrics depict poorer immunity against SHE stressing. When the substrate bias becomes more negatively than −1 V, all but the control device with thermal oxide show a drastic increase in threshold voltages. These sudden increases in the threshold voltages imply that electron trapping should be the dominant mechanism which is responsible for the aggravated device degradation for all nitrided gate oxide devices. Based on the

discussion abovementioned, we illustrate a schematic band diagram and electron conduction path for the devices stressed at different bias conditions, i.e., constant voltage stress (CVS), channel hot electron (CHE) injection, and substrate hot electron (SHE) in Fig. 2.9. For conventional CVS, i.e. Vsub = 0 V, the channel electrons, i.e., cold carriers, have a higher probability to directly tunnel into the gate without entering the conduction band of the oxide when the thickness of gate dielectric lies in the direct tunneling regime (EOT = 1.6 nm in our cases). Therefore, only negligible stress-induced degradation has been observed when the gate voltage is lower than 2.6 V as shown in Fig. 2.7. When a larger gate voltage is applied, a small fraction of electrons in the high-energy tail may tunnel into the conduction band of the gate dielectric and cause the dielectrics damaged via interaction with the dielectric network.

Since the kinetic energy of the electrons in the tail of the energy distribution will increase with increasing the substrate bias, the degradation becomes accordingly more apparent.

It has ever been reported that electron trapping will dominate the dielectric degradation instead of the interface state generation for the gate oxide with heavily nitridation [41], [52], [57]–[59], [62], [117], [118]. The link of the electron trap creation to the nitrogen incorporation has also been investigated [119]–[121]. It was shown that the bonds of paramagnetic electron trap precursors introduced by the nitrogen incorporation can be easily broken by the impact of the high energy electrons to create the electron traps. Therefore, the presence of trapped electrons in the gate dielectric may not only reduces the gate leakage current by locally electric field lowering [109], [116], but also leads to threshold voltage shift. Meanwhile, transconductance will also be degraded due to the loss of channel electrons and the consequent Coulomb scattering with capturing electrons within the gate dielectric [35], [47], [92]–[96].

2.3.3 DCIV Measurement

In despite of the fact that charging pumping method is a very useful technique to characterize the interface quality, high gate leakage in the direct tunneling regime will cause the charge pumping measurement become unreliable, and more complicate analyzing approaches have to be developed [122]–[126]. Another technique for evaluating the interface quality as the Direct-Current Current-Voltage (DCIV) method has also been proposed [127]–[134]. Because gate bias of the DCIV measurement is biased at near the flat-band condition, the gate leakage component can be suppressed.

Figure 2.10 is the cross-sectional view of the four-terminal DCIV measurement.

Regarding the source, substrate, and drain of the nMOSFET as the emitter, base, and collector of the parasitic BJT structure, respectively, the base current, Ib, is mostly attributed to the recombination current with the recombination process through the defects in the base region and the interface traps. Therefore, if excess interface states are generated during device stressing, Ib will be significantly increased with varying the slope as displayed in the curve-#2, 3, and 4 for different distribution situations.

The base currents as a function of collector-base voltage (Vcb) measured by the four-terminal DCIV method of the 0.13 µm nMOSFETs with an EOT of 1.6 nm plasma nitrided gate oxide before and after CHE and SHE stressing for 10⁴ seconds are shown in Fig. 2.11. Note that the slopes of Ib–Vcb curves are almost unchanged for both CHE and SHE stressing except slightly increase of the base currents. The parallel increase of Ib should be due to raising the effective gate bias by electron trapping in the gate dielectric after the hot-electron stressing. Again, we confirm that the mechanism responsible for the degradation is the electron trap generation rather than the interface state generation. As discussed previously, we speculate that all of these