Organization of the Thesis

1.5 Organization of the Thesis

In Chapter 1, we introduce the evolution of lithography and device technology.

In Chapter 2, we present the fabrication of PMOSFETs with channel length down to 80 nm and describe the process flow utilizing the DP technique. TCAD simulation and measurement setups are also presented in this chapter.

In Chapter 3, electrical characteristics of the fabricated devices with various annealing temperature are presented. Both transfer curves and capacitance-voltage (C-V) characteristics are analyzed to indentify boron penetration and gate depletion.

For the sake of reliability issues, NBTI and CHC stress are undergone and charge pumping measurements are taken place for understanding the degradation of MOS

transistors.

Eventually, in Chapter 4, we summarize the major conclusions based on the analysis of our experimental results.

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Chapter 2

Device Fabrication and Measurement Setup

2.1 Double Patterning Technique

In this section, we present a double patterning (DP) technique which combines twice lithographic and subsequent etching steps using an I-line stepper to fabricate and demonstrate 80nm p-channel MOSFETs. The intended design patterns are defined by virtue of two distinct masks which are denoted as G1 and G2 and shown in Fig. 2.1.

The masks are used in the litho-etch-litho-etch (LELE) process [30] to form the final device’s gate structure. In the first place, we utilize the G1 mask to shelter poly-Si on the right side of active region from the first etching step, whereas the uncovered Si region is established as the source region. Next, the task of G2 mask is to prevent the left side of active region from succeeding etching process for the sake of drain side definition, including a fraction of poly-Si region remained after the first etching. The overlapped region between the G1 and G2 masks defines the gate length, which is the most critical metric of the pattern size. No doubt LELE process is obliged to add an additional mask, raising process complexity. However, LELE process breaks the resolution limit of conventional I-line lithography and enables the feasibility of asymmetric MOSFETs [31].

The above DP process was carried in the National Nano Device Laboratories (NDL) which offers public technical service for academic field and industry, including the I-line lithographic process. To make sure that the critical dimensions (CDs) of the fabricated devices meet the requirements relies on the inspection effort spent before the irreversible etching step. We’ve split many exposure dose conditions on a test wafer and inspected the resultant gate length by an in-line scanning electron

microscope (SEM). The most appropriate exposure dose condition capable of achieving the target CD values was determined form the test wafer and used in the following fabrication of devices. In this thesis, we define the intended design gate length on the mask as L_mask and veritable gate length measured by in-line SEM as L_gate. Fig. 2.2 shows the in-line SEM images and measured gate lengths for poly-Si patterns with nominal gate length of 100nm. Thanks to the appropriate exposure dose we chose, good CD control can be achieved. The results for the patterns with L_mask of 80nm are shown in Fig. 2.3 with the test structures taken from dies the same as those shown in Fig. 2.2. In this case, the control of CD is still satisfactory as well.

Nevertheless, principal fluctuations in the CD of the exquisite patterns are due to the overlay capability of the lithographic tool. Based on the handbook furnished by NDL, the overlay accuracy is approximately 45nm. Moreover, the abnormal results with Lmask of 60nm are indicated in Fig. 2.4, in which practical lengths much smaller than L_mask are obtained. Obviously for this case it is out of control due to the limitation of overlay accuracy. On the whole, most of patterns with Lmask of 80 nm show no serious difference from die to die, as shown in Fig. 2.5.

2.2 TCAD Simulation and Device Fabrication

2.2.1 TCAD Simulation for Asymmetric S/D Extensions

Technology computer-aided design (TCAD) provides an available way to develop and optimize semiconductor processes and devices by using computer simulations. Semiconductor foundries pay the expensive license fee to suppliers of TCAD tools to reduce high-priced and time-consuming test wafer runs while developing and characterizing a novel structure or next-generation device [32]. In general, TCAD simulation tools solve fundamental physical differential equations,

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such as diffusion and transport equations for applications of process simulation, device simulation, and electrical characteristics [33].

The process simulation considers the basic p-channel MOSFET procedures with an N-well and substrate doping conditions summarized in Table 2.1. After growing a 2.5 nm thermal oxide in N2O ambient and a 120 nm undoped poly-Si layer, the poly-Si layer is implanted with BF2+

at 15 keV with dose of 5×10¹⁵ cm^-2. As mentioned in the motivation, we undertake ion sources of B⁺ and BF2+

to form S/D extension, however, different effective mass of the ion sources incurs various doping profiles. For the purpose of comparable depth and lateral profile, we add a screen oxide before ion implantation for boron.

Hence, the process simulation focuses on doping profiles of S/D extensions and halo implantation. Implantation conditions and activation temperatures are also listed in Table 2.1. It is noticed that process simulation including DP technique to accomplish gate formation and asymmetric S/D extension. Besides, the capping screen oxide is formed only for source extension implantation of B⁺, while drain extension is implanted by BF₂⁺ without the screen oxide. With such a procedure we successfully obtain resembling doping distributions between junctions formation by B⁺ and BF₂⁺, as shown in Fig. 2.6. Figure 2.7 shows the activated carrier concentration of the As-doped regions, indicating that halo implantation takes part in the S/D junction construction. On account of the lateral profile which is the most influential factor in affecting the device characteristics, we enlarge the doping profiles along the channel further in Fig. 2.8. In the figure it is seen that there is no considerable difference between the asymmetric S/D extensions. Through TCAD simulation, we look forward to acquiring appropriate procedures and conditions to fabricate our practicable devices.

2.2.2 Device Fabrication and Process Flow

The devices were fabricated on 6-inch n-type (100) Si wafers with resistivity of 15~25 Ω -cm. To begin with, the N-well was formed by P⁺ implantation at 120 keV with dose of 7.5×10¹² cm^-2 and the well drive-in was carried out at 1100 ℃ for 12 hours. Then, standard local oxidation of silicon (LOCOS) process was performed with channel stop implantation by As⁺ at 120 keV with dose of 3×10¹² cm^-2 for device isolation. Threshold voltage adjustment implantation was done by As⁺ at 80keV with dose of 1×10¹³ cm^-2 and anti-punch through implantation was done by P⁺ at 120keV with dose of 4×10¹² cm^-2, respectively.

Figure 2.9 illustrates the fabrication flow of PMOSFETs with major process steps in gate dielectric and electrode deposition. Briefly, after standard LOCOS process, Radio Corporation of America (RCA) clean was used for removing contaminants from the wafer surface. Subsequently, a 2.5 nm thermal gate oxide grown in N₂O ambient and a 120 nm undoped poly-Si layer deposited by low-pressure chemical vapor deposition (LPCVD) were formed in a clustered vertical furnace system sequentially. Undoped poly-Si layers were implanted with either BF2+

or B⁺ at 15 keV with dose of 3×10¹² cm^-2. Then all wafers were annealed at 900℃ for 10 seconds for dopant activation of the gate. Afterwards, a 50 nm LPCVD TEOS oxide was deposited as a hard mask layer.

Figure 2.10 shows the fabrication of asymmetric and symmetric devices. All devices were defined by G1 mask, whereas only symmetric devices received gate definition with the G2 mask before the halo implantation. The details about the halo and S/D extension implantation conditions are shown in Table 2.2. In the case of source extension implantation with B⁺, a 10nm TEOS oxide was capped as screen

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oxide as mentioned previously. Source side extension of asymmetric devices and the split A of symmetric devices having extensions formed with B⁺ were implanted, as shown in Fig 2.11. For asymmetric devices, we defined drain-side region by G2 mask and halo implantation sequentially, as shown in Fig. 2.12. Drain side extension of asymmetric devices and the split B of symmetric devices are formed by BF2+

implantation. Afterwards, all wafers went through sidewall spacer formation, followed by a deep S/D implant with BF₂⁺ at 15 keV at dose of 5×10¹⁵ cm^-2, as shown in Fig.

2.13. Spike rapid thermal anneal (SRTA) was then carried out in N₂ ambient at 1000

C to activate the dopants in the preceding implantation processes. After a typical

process to deposit a 500nm TEOS passivation for humidity prevention, the metal contact pads were formed. Finally, all wafers received a forming gas annealing at 400

C for 30 minutes.

2.3 Measurement Setup

2.3.1 Electrical Measurement Setup

In our study, electrical measurements of our devices were evaluated by an HP4156A precision semiconductor parameter analyzer and an HP4284 LCR meter.

The HP4156A systems were applied to gauge the current-voltage (I-V) and the HP4284 LCR systems were used for capacitance-voltage (C-V) measurements. In order to stabilize the measurement environment, black box and temperature-regulated hot chucks were employed.

2.3.2 NBTI and CHC Reliability Measurement Setup

To investigate the matching parameters of PMOSFETs before and after negative bias temperature instability (NBTI) and channel hot carrier (CHC) stresses, we have

performed the NBTI-mode and CHC-mode tests to study the performance degradation, as shown in Fig. 2.14. The stress voltages were applied by an overdrive voltage. In the NBTI-mode the stress bias was only applied to the gate whereas the other terminals were grounded. On the other hand, the CHC-mode has the applied stress biases applied to the gate and drain, while the other terminals were grounded. Temperature effect was also explored in cooperation with both NBTI and CHC modes. In the course of heating, temperature was monitored. Note that the measurement system was heated up to the objective temperature and hold for additional 30 minutes before the measurements for stabilizing the system.

2.3.3 Charge Pumping Measurements

The charge pumping (CP) measurement has been widely used to characterize the interface state density in MOSFET devices [34-35]. Both fixed amplitude sweep and fixed base sweep schemes are employed in this work to determine the density and lateral distribution of the interface traps generated during the CHC stress and NBTI stress. Figure 2.15 shows the schematic of fixed amplitude sweep CP measurement.

The substrate current was measured and recorded by applying a series of voltage with fixed amplitude to the gate while both source and drain were biased with a small reverse bias and substrate was connected to ground. On the other hand, the fixed peak sweep CP measurement is used to analyze the lateral distribution of interface traps, as shown in Fig. 2.16. In this work, the CP measurement was pulsed with square-waveforms at frequency of 1 MHz, duty cycle of 50, leading and trailing of 80 nanoseconds. In the fixed amplitude sweep, the base voltage was modulated by step of 50 mV and constant pulse amplitude at 1.5 V to operate the device from accumulation to inversion. Nevertheless, the peak voltage was constant and

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modulated pulse amplitude by step of 100 mV in the fixed peak sweep. Figure 2.17 illustrates three types of different voltage pulse applied to the gate, but we merely use the foregoing sweep to examine and analyze our devices.

Table 2.1 Process conditions for TCAD simulation

Poly Gate 120nm

N₂O thermal oxide 2.5nm Source side screen oxide 10nm Implantation conditions

N-well P⁺/120keV /7.5×10¹² cm^-2

Anti-punch through P⁺/120keV /4×10¹² cm^-2 Threshold voltage adjustment As⁺/80keV/1×10¹³ cm^-2 Poly gate BF₂⁺/15keV/5×10¹⁵ cm^-2

Rapid Thermal Annealing In N2 ambient at 1000 C for 1 second

Table 2.2 Split conditions for extension structure with the DP technique.

Halo implantation As⁺/50keV/1×10¹³ cm^-2/Tilt 45˚/Twist 27˚/Rotation 4 times Symmetric

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Chapter 3

Results and Discussion

3.1 Electrical Characteristics of Symmetric-Extension Devices

3.1.1 Boron Penetration with Poly-Si Gate

In this work, we investigate the effects of gate stack formation and fluorine incorporation on boron penetration with S/D activation temperature at 1000℃ and gate oxide down to 2.5 nm. Figure 3.1 shows the transfer characteristics of B-implanted gate with length of 10 μm. It can be seen that the Vth dramatically shifts rightward to 0.62 V and the SS is also increased to 260 mV/dec. To verify whether DP is the culprit or not, we have also fabricated control devices with single-patterning (SP) technique as well. By single patterning we are referring to conventional self-aligned process with S/D extension formed directly after the standard gate definition. Comparisons between DP and SP splits show negligible difference, so we could exclude DP technique from being the culprit for the above abnormal V_th shift and SS degradation. From a survey of literature, the positive shift of Vth and SS degradation are typical behaviors of boron penetration [37]. That is, diffusion of boron from heavily-doped p⁺ ploy-Si gate through the thin oxide and into the underlying channel region, resulting in SS degradation and Vth shift. Furthermore, the presence of fluorine enhances boron diffusion through thin oxide [38]. Figure 3.2 confirms this trend, i.e., for a device with BF2+

-doped gate, larger Vth shift (0.72V) and much larger gate leakage current as compared with those shown in Fig. 3.1 are observed. Such F-enhanced boron-penetration phenomenon further worsens the short-channel effects. This can be understood from the comparison of the results

shown in Figs. 3.3 and 3.4. In the two figures it is seen that the on-state current does not increase with decreasing channel length. Moreover, Fig 3.4 shows the F-doped devices exhibit strong punch-through characteristics owing to F-enhanced boron diffusion and penetration. As a matter of fact, boron penetration through thin oxide and into the channel is detrimental to the success of surface channel PMOSFETs.

3.1.2 Accomplishment of 80nm Devices without Boron Penetration

It has been reported that nitrided oxide prepared by oxidizing Si in an N2O ambient shows good barrier property and blocks boron diffusion due to the pile-up of nitrogen at the Si/oxide interface (Fig. 3.5) [38]. In this work, we used RTA at 900℃

for 10 seconds to activate gate doping. Additional post-thermal process for the gate was the S/D activation step. For the reason of suppressing boron penetration, the temperature for S/D activation was reduced to 900℃. Figure 3.6 shows the transfer characteristics of devices with B- and BF₂-doped gates. The channel length is 10μm.

The Vth is -0.06V and -0.78V for B- and BF2–doped gates, respectively. It is noticed that gate leakage currents are much smaller than the results shown in Figs. 3.1 and 3.2, implying that the B-penetration has been effectively suppressed, especially for the BF2–doped split. Figure 3.7 illustrates transfer characteristics of devices with B-doped gate and various channel length of 1 μm and 0.08 μm. The results indicate that a much better control over the short-channel effects is obtained as compared with that shown in Fig. 3.3. However, the source and drain depletion regions are so close to each other that the short-channel device still exhibits obvious short-channel behaviors such as DIBL. Another important parameter is SS which is expressed with the following equation:

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where Cdm is depletion layer capacitance and Cox is oxide capacitance. To get a steep SS for better gate controllability, we need to use ultra-thin oxide to reduce Cox for lower SS degradation in the short-channel device. A similar comparison of BF₂-doped devices is shown in Fig. 3.8. In addition, the output characteristics are shown in Fig.

3.9 and Fig. 3.10, which look quite normal. The B-doped split exhibits much higher on-current than the BF2-doped one. This might be due to the lower substrate doping with the BF2-doped one which is implied by its lower Vth, as well as the poly deletion effect (see discussion later). The lower substrate doping could reduce the Coulomb scattering rate and improve the carrier mobility.

We also extract the V_th form the transfer characteristics at V_DS = -0.05V with several gate lengths and the results are plotted in Fig. 3.11. The Vth is defined by constant current method, that is, the gate voltage at drain current of 10nA×(W/L), where W is the gate width, and L is the gate length. It is observed that two kinds of devices depict reverse short channel effect (RSCE) because of tilt-halo implantation which increases the doping concentration near the edge of the channel, especially in the short-channel devices [39]. Devices with B-doped gate possess more severe RSCE than the BF₂-doped devices, but reveal less fluctuation in the short-channel devices.

Figure 3.12 shows the DIBL effect. It apparently exhibits worse DIBL while gate length is shrunk. SS is a key factor for switching the transistor current off, and the results are shown in Fig. 3.13 as a function of channel length. As can be seen in the

figure, SS is not severely deteriorated with gate lengths from 1 μm to 0.08 μm.

Traditionally, PMOSFETs are two to three times lower in mobility than NMOSFETs due to effective mass mismatch. Therefore, the width of PMOSFETs is

ordinarily designed to be two to three times larger than that of NMOSFET in CMOS circuit design. One of the most important factors is the device’s driving current which determines the operation speed. Figure 3.14 shows on-state current at VG = -1.5V and V_DS = -0.05V with various gate length. The B-doped-gate split shows outstanding I_on characteristics as compared with the BF2-doped-gate split. Hence, output characteristics are superior as demonstrated in previous section. For comparison purpose, the transfer characteristics of a 0.1 μm NMOSFET characterized in one of our previous studies [40] are displayed in Fig. 3.15 together with 0.1 μm PMOSFETs.

As can be seen in the figure, the SS values of the PMOSFETs are comparable to those of the NMOSFFTs. Nonetheless, the off-state leakage seems to be much higher for the PMOSFETs. More efforts are demanded for improving the junction characteristics.

In the case of CMOS circuits, symmetrical threshold voltage is essential in circuit design. In this regard, the Vth (absolute value) seems too low for the B-doped device and too high for the BF₂-doped one. More refinement in halo doping is needed to adjust the Vth to an appropriate value.

For better understanding of the device performance, the C-V characteristics of the devices are represented in Fig. 3.16. The measurement frequency is 100 kHz and the device area is 10⁴ μm². Results for the devices with severe B-penetration characterized in previous sub-section are also included in this figure. Boron penetration leading to Vth and flat band voltage shifts is confirmed. Capacitance equivalent thickness (CET) is calculated by the following equation:

measured Si

C CET 

 A



where ε₀ is vacuum permittivity, ε_Si is silicon permittivity, A is the device gate area, and Cmeasured is the measured maximum capacitance in accumulation region or

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inversion region. The estimated CETs are listed in Table 3.1. Note that the CET extracted from the accumulation region is in good agreement with the process condition of 2.5 nm mentioned in last chapter. It also indicates that the gate depletion occurs in those devices. The CET differences between the accumulation and inversion regions of the devices are listed in Table 3.2. Among them, the device with BF2-doped gate exhibits the most serious gate depletion. This well explains the degraded current drive of the BF₂-doped split as compared with the B-doped counterpart.

3.2 Electrical Characteristics of Asymmetric-Extension Device

In this section, we present experimental results for transistors with asymmetric S/D extension whose source and drain received different implantation and annealing conditions. Fig. 3.17 displays the device structure in which the p⁺ junctions are formed with either B⁺ or BF2+

implant. Here we define forward mode as the

implant. Here we define forward mode as the