Chapter 3 Results and Discussion
3.1 Electrical Characteristics of Symmetric-Extension Devices…
3.1.1 Boron Penetration with Poly-Si Gate
In this work, we investigate the effects of gate stack formation and fluorine incorporation on boron penetration with S/D activation temperature at 1000℃ and gate oxide down to 2.5 nm. Figure 3.1 shows the transfer characteristics of B-implanted gate with length of 10 μm. It can be seen that the Vth dramatically shifts rightward to 0.62 V and the SS is also increased to 260 mV/dec. To verify whether DP is the culprit or not, we have also fabricated control devices with single-patterning (SP) technique as well. By single patterning we are referring to conventional self-aligned process with S/D extension formed directly after the standard gate definition. Comparisons between DP and SP splits show negligible difference, so we could exclude DP technique from being the culprit for the above abnormal Vth shift and SS degradation. From a survey of literature, the positive shift of Vth and SS degradation are typical behaviors of boron penetration [37]. That is, diffusion of boron from heavily-doped p+ ploy-Si gate through the thin oxide and into the underlying channel region, resulting in SS degradation and Vth shift. Furthermore, the presence of fluorine enhances boron diffusion through thin oxide [38]. Figure 3.2 confirms this trend, i.e., for a device with BF2+
-doped gate, larger Vth shift (0.72V) and much larger gate leakage current as compared with those shown in Fig. 3.1 are observed. Such F-enhanced boron-penetration phenomenon further worsens the short-channel effects. This can be understood from the comparison of the results
shown in Figs. 3.3 and 3.4. In the two figures it is seen that the on-state current does not increase with decreasing channel length. Moreover, Fig 3.4 shows the F-doped devices exhibit strong punch-through characteristics owing to F-enhanced boron diffusion and penetration. As a matter of fact, boron penetration through thin oxide and into the channel is detrimental to the success of surface channel PMOSFETs.
3.1.2 Accomplishment of 80nm Devices without Boron Penetration
It has been reported that nitrided oxide prepared by oxidizing Si in an N2O ambient shows good barrier property and blocks boron diffusion due to the pile-up of nitrogen at the Si/oxide interface (Fig. 3.5) [38]. In this work, we used RTA at 900℃
for 10 seconds to activate gate doping. Additional post-thermal process for the gate was the S/D activation step. For the reason of suppressing boron penetration, the temperature for S/D activation was reduced to 900℃. Figure 3.6 shows the transfer characteristics of devices with B- and BF2-doped gates. The channel length is 10μm.
The Vth is -0.06V and -0.78V for B- and BF2–doped gates, respectively. It is noticed that gate leakage currents are much smaller than the results shown in Figs. 3.1 and 3.2, implying that the B-penetration has been effectively suppressed, especially for the BF2–doped split. Figure 3.7 illustrates transfer characteristics of devices with B-doped gate and various channel length of 1 μm and 0.08 μm. The results indicate that a much better control over the short-channel effects is obtained as compared with that shown in Fig. 3.3. However, the source and drain depletion regions are so close to each other that the short-channel device still exhibits obvious short-channel behaviors such as DIBL. Another important parameter is SS which is expressed with the following equation:
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where Cdm is depletion layer capacitance and Cox is oxide capacitance. To get a steep SS for better gate controllability, we need to use ultra-thin oxide to reduce Cox for lower SS degradation in the short-channel device. A similar comparison of BF2-doped devices is shown in Fig. 3.8. In addition, the output characteristics are shown in Fig.
3.9 and Fig. 3.10, which look quite normal. The B-doped split exhibits much higher on-current than the BF2-doped one. This might be due to the lower substrate doping with the BF2-doped one which is implied by its lower Vth, as well as the poly deletion effect (see discussion later). The lower substrate doping could reduce the Coulomb scattering rate and improve the carrier mobility.
We also extract the Vth form the transfer characteristics at VDS = -0.05V with several gate lengths and the results are plotted in Fig. 3.11. The Vth is defined by constant current method, that is, the gate voltage at drain current of 10nA×(W/L), where W is the gate width, and L is the gate length. It is observed that two kinds of devices depict reverse short channel effect (RSCE) because of tilt-halo implantation which increases the doping concentration near the edge of the channel, especially in the short-channel devices [39]. Devices with B-doped gate possess more severe RSCE than the BF2-doped devices, but reveal less fluctuation in the short-channel devices.
Figure 3.12 shows the DIBL effect. It apparently exhibits worse DIBL while gate length is shrunk. SS is a key factor for switching the transistor current off, and the results are shown in Fig. 3.13 as a function of channel length. As can be seen in the
figure, SS is not severely deteriorated with gate lengths from 1 μm to 0.08 μm.
Traditionally, PMOSFETs are two to three times lower in mobility than NMOSFETs due to effective mass mismatch. Therefore, the width of PMOSFETs is
ordinarily designed to be two to three times larger than that of NMOSFET in CMOS circuit design. One of the most important factors is the device’s driving current which determines the operation speed. Figure 3.14 shows on-state current at VG = -1.5V and VDS = -0.05V with various gate length. The B-doped-gate split shows outstanding Ion characteristics as compared with the BF2-doped-gate split. Hence, output characteristics are superior as demonstrated in previous section. For comparison purpose, the transfer characteristics of a 0.1 μm NMOSFET characterized in one of our previous studies [40] are displayed in Fig. 3.15 together with 0.1 μm PMOSFETs.
As can be seen in the figure, the SS values of the PMOSFETs are comparable to those of the NMOSFFTs. Nonetheless, the off-state leakage seems to be much higher for the PMOSFETs. More efforts are demanded for improving the junction characteristics.
In the case of CMOS circuits, symmetrical threshold voltage is essential in circuit design. In this regard, the Vth (absolute value) seems too low for the B-doped device and too high for the BF2-doped one. More refinement in halo doping is needed to adjust the Vth to an appropriate value.
For better understanding of the device performance, the C-V characteristics of the devices are represented in Fig. 3.16. The measurement frequency is 100 kHz and the device area is 104 μm2. Results for the devices with severe B-penetration characterized in previous sub-section are also included in this figure. Boron penetration leading to Vth and flat band voltage shifts is confirmed. Capacitance equivalent thickness (CET) is calculated by the following equation:
measured Si
C CET
0 A
, (3.2)where ε0 is vacuum permittivity, εSi is silicon permittivity, A is the device gate area, and Cmeasured is the measured maximum capacitance in accumulation region or
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inversion region. The estimated CETs are listed in Table 3.1. Note that the CET extracted from the accumulation region is in good agreement with the process condition of 2.5 nm mentioned in last chapter. It also indicates that the gate depletion occurs in those devices. The CET differences between the accumulation and inversion regions of the devices are listed in Table 3.2. Among them, the device with BF2-doped gate exhibits the most serious gate depletion. This well explains the degraded current drive of the BF2-doped split as compared with the B-doped counterpart.