Chapter 3 Results and Discussion
3.3 NBTI and CHC Degradations on PMOSFETs
3.3.3 Comparisons between CHC and NBTI Stresses
To explore the CHC effect, we apply the same overdrive voltage (V = Vth -2V) on both gate and drain terminals while the source is grounded. Besides, we measure the currents under forward or reverse modes (see Fig. 3.32) to extract threshold voltage shift. Fig. 3.33 shows the threshold voltage shifts after CHC or NBTI stress.
As can be seen in the figure, the NBTI mode shows worse degradation while the results of the CHC effects under forward or reverse modes look quite different. Figure 3.34 depicts that the CHC mode generates fewer interface traps as compared with the NBTI mode, consistent with the less voltage shift. The results of lateral charging pumping measurements are shown in Fig. 3.35. In the figure we confirm that more
26
interface traps are generated near the drain side, leading to more threshold voltage shift for the forward mode shown in Fig. 3.34. At present, the lucky electron model is not sufficient to explain the CHC effects in PMOSFETs. The reasons are that holes have a smaller impact ionization rate and a higher Si-SiO2 barrier to overcome. More efforts are in demand for understanding the CHC effect. Finally, the NBTI effect is more serious and more attention should be paid.
Table 3.1 Capacitance equivalent thicknesses (CETs) of devices with B- or BF2-doped gates. Devices with serious boron penetration are also included.
CET(nm) B-doped gate
BF2-doped gate
B-doped gate with penetration
BF2-doped gate with penetration accumulation 2.7317 2.8075 2.8515 2.7485
inversion 3.1796 3.5261 3.1633 3.2015
Table 3.2 Estimated poly-depletion thickness from the difference in CETs measured in accumulation and inversion regions.
B gate BF2 gate Poly depletion (nm) 0.448 0.719
28
Chapter 4
Conclusion and Future Work
4.1 Recapitulation and Conclusion
In this thesis, we have employed a novel DP technique for fabricating PMOSFETs with gate length down to 80 nm using only conventional I-line stepper.
By taking advantage of the technique, devices with symmetric or asymmetric S/D extension structures were fabricated and characterized in our study. The effects of boron penetration, gate stack module, poly depletion, asymmetric extension behavior, and reliability issues, were carefully studied. Here, we briefly review and summarize the principal findings discovered in this work.
Although the DP technique requires an additional mask and extra process steps in comparison with traditional single-patterning self-aligned process, it is still an attractive alternative to fabricate deep-submicron and nano-scale devices with good CD control. TCAD simulation provides essential guidelines in combination with the DP technique, which are helpful in settling the process steps and decision on the implantation conditions.
The effects of boron penetration are scrutinized for the fabricated devices.
Devices show positive shift in Vth, SS degradation, and higher gate leakage current as the effect occurs. Moreover, fluorine enhances boron penetration so the activation temperature has to be reduced accordingly. Therefore, activation temperature plays an important role in devices demanding ultra-shallow junctions. On the other hand, BF2-gate devices exhibit severe gate depletion, causing the degraded current drive.
However, BF2 implantation is an excellent approach to achieve ultra shallow junction.
The effects of halo implantation were studied. Although devices with halo implantation show improved SCEs, increased Vth as well as more severe RSCE are
observed in short-channel devices, not to mention that halo doping is difficult to refine and optimize to an appropriate value. As for the comparison between B- and BF2-gate devices, the former shows better current drive, albeit more severe RSCE.
For better performance in CMOS circuits, the B-gate devices are preferable without suffering from boron penetration enhanced by fluorine.
The asymmetric devices are attractive because they allow more margins for performance optimization. We have successfully fabricated asymmetric devices with the aid of TCAD simulation. However, the depth of B-doped junctions seems to be underestimated, owing to the use of a screen oxide which may cause undesired OED.
However the off-state leakage current is reduced with such deepened junction, indicating the tradeoff between junction depth and leakage current.
We’ve also investigated reliability issues including NBTI and CHC effects with various gate stack modules. It is found that NBTI-induced degradation is worse than the CHC-induced degradation on PMOSFETs, especially in the short-channel devices stressed at a high temperature. For the BF2-gate devices, the fluorine incorporation in both gate and overlap regions causes a reduction in the donor-like interface traps.
However, fluorine enhances boron penetrations and brings about several concerns as mentioned above. By means of the CP measurements, we confirm that NBTI stress indeed generates more interface states and causes more severe degradation over CHC.
For lateral CP measurements in CHC mode, we observe more interface traps are generated near the drain side, which is consistent with the larger threshold voltage shift under the forward mode of measurements. Nonetheless, our findings don’t support the observed trend reported previously by other groups that CHC would result in more severe damage than NBTI stress [49-51]. More efforts are needed to comprehend the whole picture of the PMOS reliability.
30
4.2 Future Work
In this work, we have successfully developed a DP technique to achieve gate patterns of 80 nm with an I-line steeper. Nevertheless, ultra shallow junction is a crucial subject for device scaling against SCEs. It is noticed that the impacts of OED must be taken into account in TCAD simulation for accurately predicting the junction depth. Carefully adjusting the conditions of halo implantation and activation temperature is essential to optimize performance in terms of suppressed boron penetration and reduced off-state leakage current.
In this work only PMOSFETs were fabricated and characterized. In future we could design and fabricate basic CMOS components and circuitries, such as inverters and ring oscillators with the developed DP technique, exploring the applications of asymmetric devices on the circuit level.
Our group has recently purchased an Agilent B1500 system, which is capable of on-the-fly measurements. The time to measure fundamental device characteristics during the stressing test is reduced to 100 μs. This procedure can reduce the impacts of these fundamental measurements on the stress characterization. Therefore, the NBTI recovery effect can be more precisely examined and trapping or de-trapping of oxide traps can be measured by the ultra-fast on-the-fly setup. It is constructive in separation of Nit and oxide traps. The R-D model for AC NBTI stress has been modified and received a lot of attention in recent years. The above scheme may also be helpful for clarifying the cryptic natures of NBTI and CHC stresses.
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38
Fig. 1.1. Historical trends of physical gate length of microprocessor unit (MPU) versus year [2].
Fig. 2.1. Design of the double patterning masks. Overlap region of G1 and G2 masks in the active region is the nominal gate length.
Fig. 2.2. In-line SEM images and measured gate lengths for poly-Si patterns in the selected dies with nominal gate length of 100nm.
40
Fig. 2.3. In-line SEM images and measured gate lengths for poly-Si patterns with nominal gate length of 80nm. The test structures were selected from dies characterized in Fig. 2.2.
Fig. 2.4. In-line SEM images and measured gate lengths for poly-Si patterns with nominal gate length of 60nm. The test structures were selected from dies characterized in Fig. 2.2. The measured dimension is much smaller than Lmask, indicating the CD is out of control at such a small dimension.
Fig. 2.5. In-line SEM images for poly-Si patterns measured in four different dies with nominal gate length of 80nm. The measured gate lengths show good CD control even for the corner dies.
42
Fig. 2.6. Due to the use of source-side screen oxide, junctions formed by B+ and BF2+ have similar junction profile.
Fig. 2.7. The activated carrier concentration of the As-doped regions implies that halo implantation participated in the S/D junction construction.
Fig. 2.8. The highlight of lateral doping profile along the channel shows no significant discrepancy between S and D extensions.
Fig. 2.9. Illustration of device fabrication flow:
(b) LOCOS isolation; (b) gate oxide and poly deposition; (c) gate implantation; (d) hard mask deposition;
44
Fig. 2.10. (cont.) (e) G1 mask definition; (f) symmetric devices defined by G2 mask first; (g) halo implantation;
Fig. 2.11. (cont.) (h) capping screened oxide; (i) source side extension of asymmetric devices and the split A of symmetric devices formed by B+;
Fig. 2.12. (cont.) (j) asymmetric devices defined by G2 mask; (k) halo implantation;
(l) drain side extension of asymmetric devices and the split B of symmetric devices formed by BF2+;
Fig. 2.13. (cont.) (m) sidewall spacer formation; (n) deep S/D implantation; (o) TEOS passivation; (p) metal contact definition and forming gas annealing.
46
Fig. 2.14. Schematics showing the measurement biases for the NBTI mode and CHC mode.
Fig. 2.15. Fundamental setup structure for charge pumping measurements.
Fig. 2.16. Lateral charge pumping measurement setup for detached side of single junction. For example, the lateral distribution of generated interface states after stress was extracted near the drain side.
Fig. 2.17. Schematic illustrations for the charge pumping measurement of different pulse conditions: (a) fixed amplitude; (b) fixed peak sweep; (c) fixed base sweep.
48
Fig. 3.1. Transfer characteristics of devices with channel length of 10 μm and B-doped gate fabricated with double patterning or single patterning scheme.
Fig. 3.2. Transfer characteristics of devices with channel length of 10 μm and BF2-doped gate fabricated with double patterning or single patterning scheme. Gate leakage current is high, presumably because of fluorine incorporation.
Gate Voltage (V)
Fig. 3.3. Transfer characteristics of devices with B-doped gate for channel length of 0.2 μm and 0.12 μm.
Fig. 3.4. Transfer characteristics of devices with BF2 -doped gate for channel length of 0.2 μm and 0.12 μm.
50
Fig. 3.5. (a) Schematic showing boron diffusion from the heavily doped P+ ploy gate into gate oxide and interface region for conventional SiO2 and (b) interaction of the boron with the nitrogen piled-up at the channel/oxide interface [38].
Fig. 3.6. Transfer characteristics of B- and BF2-doped devices with channel length of
52
Fig. 3.8. Transfer characteristics of devices with BF2-doped gate and various channel length of 1 μm and 0.08 μm.
Fig. 3.10. Output characteristics of devices with BF2-doped gate and channel length of
54
Fig. 3.12. DIBL as a function of gate length for devices with BF2- or B-doped gate.
Fig. 3.13. SS as a function of gate length for devices with BF2- or B-doped gate.
Gate Length (m)
0.1 1 10
D IB L (m V /V )
0 50 100 150 200 250
BF2-Gate B-Gate DIBL = 10nA*(W/L)
Gate Length (m)
0.1 1 10
SS (mV/dec.)
80 100 120 140
BF2-Gate B-Gate VDS = -0.05V
Fig. 3.14. Ion as a function of gate length ranging from 0.08 to 10 μm for devices with BF2- or B-doped gate.
Fig. 3.15. Comparisons of transfer characteristics of an NMOSFET with PMOSFETs with BF2- or B-doped gate. The devices are with an identical channel length of 0.1μm.
The solid symbols are for VDS = -0.05V and hollow symbols for VDS = -1V.
Gate Length (m)
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45
I
on(A)
56
Fig. 3.16. C-V curves of devices with B- or BF2-doped gate. Results for devices exhibiting B-penetration effects are also shown. The measurement frequency is 100 kHz.
Fig. 3.17. A sketch of the asymmetrical PMOSFETs and configuration of forward and reverse modes of operation.
x m2
Voltage Bias (V)
-4 -3 -2 -1 0 1 2 3 4
Capa citance (C)
0 20x10-12 40x10-12 60x10-12 80x10-12 100x10-12 120x10-12 140x10-12
B-Gate BF2-Gate
B-Gate B-penetration BF2-Gate B-penetration
Fig. 3.18. Transfer characteristics of the asymmetric device with channel length of 10 μm.
Fig. 3.19. Output characteristics of the asymmetric device with channel length of 10 μm.
58
Fig. 3.20. Transfer characteristics of the single-patterning device with symmetric extension by B implantation. It suggests that leakage current is not incurred by the DP technique.
Fig. 3.21. Transfer characteristics of the asymmetric device with channel length of 0.2 μm.
Fig. 3.22. Output characteristics of the asymmetric device with channel length of 0.2
60
Fig. 3.24. Transfer characteristics of the asymmetric device under forward mode.
Drain voltage increases from -0.1V to -1V by step of -0.1V.
Fig. 3.25. Transfer characteristics of the asymmetric device under forward mode measured at different temperature.
Fig. 3.26. Threshold voltage shift versus stress time for B-gate devices of different channel lengths at various temperatures under NBTI mode.
Fig. 3.26. Threshold voltage shift versus stress time for B-gate devices of different channel lengths at various temperatures under NBTI mode.