Chapter 3 Results and Discussion
3.2 Electrical Characteristics of Asymmetric-Extension Device
In this section, we present experimental results for transistors with asymmetric S/D extension whose source and drain received different implantation and annealing conditions. Fig. 3.17 displays the device structure in which the p+ junctions are formed with either B+ or BF2+
implant. Here we define forward mode as the measurements while the drain voltage is applied to the BF2-doped-extension side.
While reverse mode refers to the measurements with the drain voltage applied to the B-doped-extension side. An example is shown in Fig. 3.18, in which the transfer characteristics of a device with channel length of 10μm under forward and reverse modes show almost identical characteristics except the off-state leakage currents. It is observed that the leakage is anomalously high when a high drain voltage is applied to the BF2-doped-extension side. Besides, in Fig. 3.19 the output characteristics indicate that the reverse mode exhibits a slightly higher current drive. The characteristics of the symmetrical device are exhibited in Fig. 3.20. The symmetrical device was fabricated by a self-aligned process with the S/D extensions formed by an implantation step identical to the B-doped extension of the asymmetric devices. It clarifies that there is no relationship between leakage current and the DP technique.
That is, DP technique would not induce additional etching damage. In fact, the revere mode shows severe SCEs as the channel length is reduced to 0.2μm, as shown in Fig.
3.21. As can be seen in Fig. 3.22, the output characteristic of reverse mode shows significantly punch behavior which indicates the gate losses effective control of the channel. The distinct difference in behavior is ascribed to the asymmetric junction profile, as boron diffuses more rapidly than BF2 under the same temperature, resulting in a deeper junction for the B-doped-extension side. Our simulation results indeed confirm the results, as shown in Fig. 2.6. Nonetheless, the junction depth is underestimated and the use of the screen oxide appears to be futile. A probable explanation is oxygen enhanced diffusion (OED), resulting in enhanced boron diffusion due to the presence of the surface screen oxide [41]. The benefit of screen oxide is vanished and falls short of the purpose of forming ultra shallow junction.
Figure 3.23 illustrates the threshold voltage with the drain bias applied to different extensions. The RSCE is investigated and it resorts to the halo implantation.
The halo concentration is so heavy that even the long channel devices with gate length from 10μm to 1μm depict the RSCE. However, the threshold voltage roll-off trends are observed in the asymmetric devices. The reason is that the width of channel depletion region along the horizontal direction is comparable to the channel length. A fraction of charge sharing at S/D junction is leading to threshold voltage lowering.
The results imply that deeper junction is formed by boron implantation again. In contrast, BF2 extension is constructive against threshold voltage roll-off due to shallower junction depth, as described by the forward mode measurement shown in Fig. 3.17. The results clearly indicate that boron implantation is not suitable for forming ultra shallow junction in deep-submicron devices.
To further inspect leakage current in forward mode, we apply various drain voltages
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to BF2 extension side. As shown in Fig. 3.24, the leakage currents are extremely dependent on the drain bias, which are proportional to the electric filed on the gate and drain overlap region. When the field crowding occurs in drain junction of the device, the increased junction leakage current is called gate-induced drain leakage (GIDL). The vertical electric field at drain side is enormous when a higher drain voltage is applied. Additional evidence is the temperature effect represented in Fig.
3.25. If it is caused by the reverse-biased p-n junction, it should show strong temperature dependence. The linear current at drain bias of -0.05V fits this description, but the saturation current does not show any strong temperature dependence.
3.3 NBTI and CHC Degradations on PMOSFETs 3.3.1 Background
It is well-known that integrated circuits are inevitably operated at higher and higher temperature as the device density increases. Moreover, the scaling of gate dielectric has rendered NBTI the major factor that limits the lifetime of PMOSFETs rather than hot-carrier degradation [42]. Temperature effect and quality control of the ultrathin gate dielectric thus become serious reliability issues. In this work, we investigate the degradation of PMOS stressed under either NBTI mode or CHC mode and examine which one might cause worse degradation.
Most of current understanding about the NBTI effect is on the basis of reaction-diffusion (R-D) model [43]. The generation of interface traps and fixed oxide charges during the stress brings about the shift in threshold voltage. Holes and hydrogen (H) species generated by the Si-H bonds breaking during NBTI stress play important roles. The mechanisms are expressed as follows [44]:
H
o hydrogen atom. Equations (3.3) and (3.4) can be used to represent the generation of interface trap (Nit) and fixed oxide charge (Nf), respectively. The net contribution to the total threshold voltage shift is thus given by
where q is electron charge and Cox is the oxide capacitance.
In general, R-D model is used to express interface generation by the following
where kF is Si-H dissociation rate constant, kR is rate of reverse annealing of Si-H, N0
is the total number of Si-H bonds, NH is hydrogen density, and DH is hydrogen diffusion coefficient. Equation (3.7) is related to the diffusion of neutral H and shows power-law dependence with stress time. However, fixed oxide charges are arduous to charge and discharge due to their locations inside oxide. Thus, trapping or de-trapping of holes is a fast component and difficult to govern [46]. In our work, we perform conventional DC method including measure-stress-measure (MSM) technique aimed at extracting the generated interface-state density.
Hot-carrier effect has received much attention in past years. The lucky electron model is widely used to describe the observed results [47]. The worst case of hot-carrier effect for NMOSFETs usually occurs at maximum substrate current [48],
24
although still not clear for PMOSFETs. Several reports showed that the CHC effect in short-channel devices at high temperature is even worse than NBTI [49-51]. We choose the condition of CHC stress with the same voltages applied to both gate and drain at an elevated temperature to verify the aforementioned issue.
3.3.2 Channel Length and Gate Stack Dependences on NBTI
In this section, we investigate the static NBTI effect in poly-Si gated PMOSFETs.
Effects of channel length and different gate stack modules are evaluated. Figure 3.26 shows threshold voltage shift versus stress time in B-gate devices. As anticipated in devices with ultra-thin gate oxide, NBTI effect is manifested with increasing temperature or decreasing channel length. The temperature effect is particularly pronounced for the short-channel device. However, the behavior seems different in BF2-gate devices, as shown in Fig. 3.27. In this figure, although NBTI effect is still augmenting as channel length reduces at room temperature, there is no significant channel dependence at 125 ℃. The difference between the two types of devices can be interpreted by the fluorine incorporation [29][52]. Fluorine incorporation is conducive in reducing the donor-like interface traps under NBTI stress. That is, the strain at the interface is relaxed or the weak Si-H bonds are replaced by the robust Si-F bonds [53]. It has been reported that the formation of Si-F bonds could effectively decrease the generation of interface traps of NBTI due to the higher binding energy than the Si-H bonds [54]. According to the R-D model, the holes in the inversion layer at elevated temperature tend to interact with and break the Si-H bonds, resulting in the dissociation of hydrogen atoms and generation of interface traps. On the contrary, the robust Si-F bonds are less likely to be broken and generate interface traps. Note that the S/D extensions were also implanted with BF2 for the BF2-gate devices, the gate and S/D overlap regions thus contain abundant fluorine
atoms to form Si-F bonds. Therefore, the short-channel devices possess more Si-F bonds at interface in the channel as compared with the long-channel one.
In Fig. 3.28 we compare the results of the devices characterized at 125℃.
Apparently the short-channel device with B-gate performs the worst among the devices. Moreover, the results indicate that long-channel devices essentially have nothing to do with fluorine incorporation. It is elucidated that both fluorine incorporation in gate and overlap regions can influence the NBTI effect. Figure 3.29 illustrates the results of charge pumping measurements performed on the long-channel B-gate devices showing that only few interface traps are generated after NBTI stress, but the short-channel device tells a quite different story in Fig. 3.30. Results of the normal and reverse lateral charge pumping measurements are shown in Fig. 3.31 Normal and reverse modes mean the source and drain side, respectively, is floating during the measurements (see the measurement setup described in Chap. 2). The results exhibit that the generated interface traps are symmetrical to the center of the channel.
3.3.3 Comparisons between CHC and NBTI Stresses
To explore the CHC effect, we apply the same overdrive voltage (V = Vth -2V) on both gate and drain terminals while the source is grounded. Besides, we measure the currents under forward or reverse modes (see Fig. 3.32) to extract threshold voltage shift. Fig. 3.33 shows the threshold voltage shifts after CHC or NBTI stress.
As can be seen in the figure, the NBTI mode shows worse degradation while the results of the CHC effects under forward or reverse modes look quite different. Figure 3.34 depicts that the CHC mode generates fewer interface traps as compared with the NBTI mode, consistent with the less voltage shift. The results of lateral charging pumping measurements are shown in Fig. 3.35. In the figure we confirm that more
26
interface traps are generated near the drain side, leading to more threshold voltage shift for the forward mode shown in Fig. 3.34. At present, the lucky electron model is not sufficient to explain the CHC effects in PMOSFETs. The reasons are that holes have a smaller impact ionization rate and a higher Si-SiO2 barrier to overcome. More efforts are in demand for understanding the CHC effect. Finally, the NBTI effect is more serious and more attention should be paid.
Table 3.1 Capacitance equivalent thicknesses (CETs) of devices with B- or BF2-doped gates. Devices with serious boron penetration are also included.
CET(nm) B-doped gate
BF2-doped gate
B-doped gate with penetration
BF2-doped gate with penetration accumulation 2.7317 2.8075 2.8515 2.7485
inversion 3.1796 3.5261 3.1633 3.2015
Table 3.2 Estimated poly-depletion thickness from the difference in CETs measured in accumulation and inversion regions.
B gate BF2 gate Poly depletion (nm) 0.448 0.719
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Chapter 4
Conclusion and Future Work
4.1 Recapitulation and Conclusion
In this thesis, we have employed a novel DP technique for fabricating PMOSFETs with gate length down to 80 nm using only conventional I-line stepper.
By taking advantage of the technique, devices with symmetric or asymmetric S/D extension structures were fabricated and characterized in our study. The effects of boron penetration, gate stack module, poly depletion, asymmetric extension behavior, and reliability issues, were carefully studied. Here, we briefly review and summarize the principal findings discovered in this work.
Although the DP technique requires an additional mask and extra process steps in comparison with traditional single-patterning self-aligned process, it is still an attractive alternative to fabricate deep-submicron and nano-scale devices with good CD control. TCAD simulation provides essential guidelines in combination with the DP technique, which are helpful in settling the process steps and decision on the implantation conditions.
The effects of boron penetration are scrutinized for the fabricated devices.
Devices show positive shift in Vth, SS degradation, and higher gate leakage current as the effect occurs. Moreover, fluorine enhances boron penetration so the activation temperature has to be reduced accordingly. Therefore, activation temperature plays an important role in devices demanding ultra-shallow junctions. On the other hand, BF2-gate devices exhibit severe gate depletion, causing the degraded current drive.
However, BF2 implantation is an excellent approach to achieve ultra shallow junction.
The effects of halo implantation were studied. Although devices with halo implantation show improved SCEs, increased Vth as well as more severe RSCE are
observed in short-channel devices, not to mention that halo doping is difficult to refine and optimize to an appropriate value. As for the comparison between B- and BF2-gate devices, the former shows better current drive, albeit more severe RSCE.
For better performance in CMOS circuits, the B-gate devices are preferable without suffering from boron penetration enhanced by fluorine.
The asymmetric devices are attractive because they allow more margins for performance optimization. We have successfully fabricated asymmetric devices with the aid of TCAD simulation. However, the depth of B-doped junctions seems to be underestimated, owing to the use of a screen oxide which may cause undesired OED.
However the off-state leakage current is reduced with such deepened junction, indicating the tradeoff between junction depth and leakage current.
We’ve also investigated reliability issues including NBTI and CHC effects with various gate stack modules. It is found that NBTI-induced degradation is worse than the CHC-induced degradation on PMOSFETs, especially in the short-channel devices stressed at a high temperature. For the BF2-gate devices, the fluorine incorporation in both gate and overlap regions causes a reduction in the donor-like interface traps.
However, fluorine enhances boron penetrations and brings about several concerns as mentioned above. By means of the CP measurements, we confirm that NBTI stress indeed generates more interface states and causes more severe degradation over CHC.
For lateral CP measurements in CHC mode, we observe more interface traps are generated near the drain side, which is consistent with the larger threshold voltage shift under the forward mode of measurements. Nonetheless, our findings don’t support the observed trend reported previously by other groups that CHC would result in more severe damage than NBTI stress [49-51]. More efforts are needed to comprehend the whole picture of the PMOS reliability.
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4.2 Future Work
In this work, we have successfully developed a DP technique to achieve gate patterns of 80 nm with an I-line steeper. Nevertheless, ultra shallow junction is a crucial subject for device scaling against SCEs. It is noticed that the impacts of OED must be taken into account in TCAD simulation for accurately predicting the junction depth. Carefully adjusting the conditions of halo implantation and activation temperature is essential to optimize performance in terms of suppressed boron penetration and reduced off-state leakage current.
In this work only PMOSFETs were fabricated and characterized. In future we could design and fabricate basic CMOS components and circuitries, such as inverters and ring oscillators with the developed DP technique, exploring the applications of asymmetric devices on the circuit level.
Our group has recently purchased an Agilent B1500 system, which is capable of on-the-fly measurements. The time to measure fundamental device characteristics during the stressing test is reduced to 100 μs. This procedure can reduce the impacts of these fundamental measurements on the stress characterization. Therefore, the NBTI recovery effect can be more precisely examined and trapping or de-trapping of oxide traps can be measured by the ultra-fast on-the-fly setup. It is constructive in separation of Nit and oxide traps. The R-D model for AC NBTI stress has been modified and received a lot of attention in recent years. The above scheme may also be helpful for clarifying the cryptic natures of NBTI and CHC stresses.
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