Chapter 2 Device Fabrication and Measurement Setup
2.3 Measurement Setup…
2.3.3 Charge Pumping Measurement
2.3.3 Charge Pumping Measurements
The charge pumping (CP) measurement has been widely used to characterize the interface state density in MOSFET devices [34-35]. Both fixed amplitude sweep and fixed base sweep schemes are employed in this work to determine the density and lateral distribution of the interface traps generated during the CHC stress and NBTI stress. Figure 2.15 shows the schematic of fixed amplitude sweep CP measurement.
The substrate current was measured and recorded by applying a series of voltage with fixed amplitude to the gate while both source and drain were biased with a small reverse bias and substrate was connected to ground. On the other hand, the fixed peak sweep CP measurement is used to analyze the lateral distribution of interface traps, as shown in Fig. 2.16. In this work, the CP measurement was pulsed with square-waveforms at frequency of 1 MHz, duty cycle of 50, leading and trailing of 80 nanoseconds. In the fixed amplitude sweep, the base voltage was modulated by step of 50 mV and constant pulse amplitude at 1.5 V to operate the device from accumulation to inversion. Nevertheless, the peak voltage was constant and
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modulated pulse amplitude by step of 100 mV in the fixed peak sweep. Figure 2.17 illustrates three types of different voltage pulse applied to the gate, but we merely use the foregoing sweep to examine and analyze our devices.
Table 2.1 Process conditions for TCAD simulation
Poly Gate 120nm
N2O thermal oxide 2.5nm Source side screen oxide 10nm Implantation conditions
N-well P+/120keV /7.5×1012 cm-2
Anti-punch through P+/120keV /4×1012 cm-2 Threshold voltage adjustment As+/80keV/1×1013 cm-2 Poly gate BF2+/15keV/5×1015 cm-2
Rapid Thermal Annealing In N2 ambient at 1000 C for 1 second
Table 2.2 Split conditions for extension structure with the DP technique.
Halo implantation As+/50keV/1×1013 cm-2/Tilt 45˚/Twist 27˚/Rotation 4 times Symmetric
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Chapter 3
Results and Discussion
3.1 Electrical Characteristics of Symmetric-Extension Devices
3.1.1 Boron Penetration with Poly-Si Gate
In this work, we investigate the effects of gate stack formation and fluorine incorporation on boron penetration with S/D activation temperature at 1000℃ and gate oxide down to 2.5 nm. Figure 3.1 shows the transfer characteristics of B-implanted gate with length of 10 μm. It can be seen that the Vth dramatically shifts rightward to 0.62 V and the SS is also increased to 260 mV/dec. To verify whether DP is the culprit or not, we have also fabricated control devices with single-patterning (SP) technique as well. By single patterning we are referring to conventional self-aligned process with S/D extension formed directly after the standard gate definition. Comparisons between DP and SP splits show negligible difference, so we could exclude DP technique from being the culprit for the above abnormal Vth shift and SS degradation. From a survey of literature, the positive shift of Vth and SS degradation are typical behaviors of boron penetration [37]. That is, diffusion of boron from heavily-doped p+ ploy-Si gate through the thin oxide and into the underlying channel region, resulting in SS degradation and Vth shift. Furthermore, the presence of fluorine enhances boron diffusion through thin oxide [38]. Figure 3.2 confirms this trend, i.e., for a device with BF2+
-doped gate, larger Vth shift (0.72V) and much larger gate leakage current as compared with those shown in Fig. 3.1 are observed. Such F-enhanced boron-penetration phenomenon further worsens the short-channel effects. This can be understood from the comparison of the results
shown in Figs. 3.3 and 3.4. In the two figures it is seen that the on-state current does not increase with decreasing channel length. Moreover, Fig 3.4 shows the F-doped devices exhibit strong punch-through characteristics owing to F-enhanced boron diffusion and penetration. As a matter of fact, boron penetration through thin oxide and into the channel is detrimental to the success of surface channel PMOSFETs.
3.1.2 Accomplishment of 80nm Devices without Boron Penetration
It has been reported that nitrided oxide prepared by oxidizing Si in an N2O ambient shows good barrier property and blocks boron diffusion due to the pile-up of nitrogen at the Si/oxide interface (Fig. 3.5) [38]. In this work, we used RTA at 900℃
for 10 seconds to activate gate doping. Additional post-thermal process for the gate was the S/D activation step. For the reason of suppressing boron penetration, the temperature for S/D activation was reduced to 900℃. Figure 3.6 shows the transfer characteristics of devices with B- and BF2-doped gates. The channel length is 10μm.
The Vth is -0.06V and -0.78V for B- and BF2–doped gates, respectively. It is noticed that gate leakage currents are much smaller than the results shown in Figs. 3.1 and 3.2, implying that the B-penetration has been effectively suppressed, especially for the BF2–doped split. Figure 3.7 illustrates transfer characteristics of devices with B-doped gate and various channel length of 1 μm and 0.08 μm. The results indicate that a much better control over the short-channel effects is obtained as compared with that shown in Fig. 3.3. However, the source and drain depletion regions are so close to each other that the short-channel device still exhibits obvious short-channel behaviors such as DIBL. Another important parameter is SS which is expressed with the following equation:
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where Cdm is depletion layer capacitance and Cox is oxide capacitance. To get a steep SS for better gate controllability, we need to use ultra-thin oxide to reduce Cox for lower SS degradation in the short-channel device. A similar comparison of BF2-doped devices is shown in Fig. 3.8. In addition, the output characteristics are shown in Fig.
3.9 and Fig. 3.10, which look quite normal. The B-doped split exhibits much higher on-current than the BF2-doped one. This might be due to the lower substrate doping with the BF2-doped one which is implied by its lower Vth, as well as the poly deletion effect (see discussion later). The lower substrate doping could reduce the Coulomb scattering rate and improve the carrier mobility.
We also extract the Vth form the transfer characteristics at VDS = -0.05V with several gate lengths and the results are plotted in Fig. 3.11. The Vth is defined by constant current method, that is, the gate voltage at drain current of 10nA×(W/L), where W is the gate width, and L is the gate length. It is observed that two kinds of devices depict reverse short channel effect (RSCE) because of tilt-halo implantation which increases the doping concentration near the edge of the channel, especially in the short-channel devices [39]. Devices with B-doped gate possess more severe RSCE than the BF2-doped devices, but reveal less fluctuation in the short-channel devices.
Figure 3.12 shows the DIBL effect. It apparently exhibits worse DIBL while gate length is shrunk. SS is a key factor for switching the transistor current off, and the results are shown in Fig. 3.13 as a function of channel length. As can be seen in the
figure, SS is not severely deteriorated with gate lengths from 1 μm to 0.08 μm.
Traditionally, PMOSFETs are two to three times lower in mobility than NMOSFETs due to effective mass mismatch. Therefore, the width of PMOSFETs is
ordinarily designed to be two to three times larger than that of NMOSFET in CMOS circuit design. One of the most important factors is the device’s driving current which determines the operation speed. Figure 3.14 shows on-state current at VG = -1.5V and VDS = -0.05V with various gate length. The B-doped-gate split shows outstanding Ion characteristics as compared with the BF2-doped-gate split. Hence, output characteristics are superior as demonstrated in previous section. For comparison purpose, the transfer characteristics of a 0.1 μm NMOSFET characterized in one of our previous studies [40] are displayed in Fig. 3.15 together with 0.1 μm PMOSFETs.
As can be seen in the figure, the SS values of the PMOSFETs are comparable to those of the NMOSFFTs. Nonetheless, the off-state leakage seems to be much higher for the PMOSFETs. More efforts are demanded for improving the junction characteristics.
In the case of CMOS circuits, symmetrical threshold voltage is essential in circuit design. In this regard, the Vth (absolute value) seems too low for the B-doped device and too high for the BF2-doped one. More refinement in halo doping is needed to adjust the Vth to an appropriate value.
For better understanding of the device performance, the C-V characteristics of the devices are represented in Fig. 3.16. The measurement frequency is 100 kHz and the device area is 104 μm2. Results for the devices with severe B-penetration characterized in previous sub-section are also included in this figure. Boron penetration leading to Vth and flat band voltage shifts is confirmed. Capacitance equivalent thickness (CET) is calculated by the following equation:
measured Si
C CET
0 A
, (3.2)where ε0 is vacuum permittivity, εSi is silicon permittivity, A is the device gate area, and Cmeasured is the measured maximum capacitance in accumulation region or
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inversion region. The estimated CETs are listed in Table 3.1. Note that the CET extracted from the accumulation region is in good agreement with the process condition of 2.5 nm mentioned in last chapter. It also indicates that the gate depletion occurs in those devices. The CET differences between the accumulation and inversion regions of the devices are listed in Table 3.2. Among them, the device with BF2-doped gate exhibits the most serious gate depletion. This well explains the degraded current drive of the BF2-doped split as compared with the B-doped counterpart.
3.2 Electrical Characteristics of Asymmetric-Extension Device
In this section, we present experimental results for transistors with asymmetric S/D extension whose source and drain received different implantation and annealing conditions. Fig. 3.17 displays the device structure in which the p+ junctions are formed with either B+ or BF2+
implant. Here we define forward mode as the measurements while the drain voltage is applied to the BF2-doped-extension side.
While reverse mode refers to the measurements with the drain voltage applied to the B-doped-extension side. An example is shown in Fig. 3.18, in which the transfer characteristics of a device with channel length of 10μm under forward and reverse modes show almost identical characteristics except the off-state leakage currents. It is observed that the leakage is anomalously high when a high drain voltage is applied to the BF2-doped-extension side. Besides, in Fig. 3.19 the output characteristics indicate that the reverse mode exhibits a slightly higher current drive. The characteristics of the symmetrical device are exhibited in Fig. 3.20. The symmetrical device was fabricated by a self-aligned process with the S/D extensions formed by an implantation step identical to the B-doped extension of the asymmetric devices. It clarifies that there is no relationship between leakage current and the DP technique.
That is, DP technique would not induce additional etching damage. In fact, the revere mode shows severe SCEs as the channel length is reduced to 0.2μm, as shown in Fig.
3.21. As can be seen in Fig. 3.22, the output characteristic of reverse mode shows significantly punch behavior which indicates the gate losses effective control of the channel. The distinct difference in behavior is ascribed to the asymmetric junction profile, as boron diffuses more rapidly than BF2 under the same temperature, resulting in a deeper junction for the B-doped-extension side. Our simulation results indeed confirm the results, as shown in Fig. 2.6. Nonetheless, the junction depth is underestimated and the use of the screen oxide appears to be futile. A probable explanation is oxygen enhanced diffusion (OED), resulting in enhanced boron diffusion due to the presence of the surface screen oxide [41]. The benefit of screen oxide is vanished and falls short of the purpose of forming ultra shallow junction.
Figure 3.23 illustrates the threshold voltage with the drain bias applied to different extensions. The RSCE is investigated and it resorts to the halo implantation.
The halo concentration is so heavy that even the long channel devices with gate length from 10μm to 1μm depict the RSCE. However, the threshold voltage roll-off trends are observed in the asymmetric devices. The reason is that the width of channel depletion region along the horizontal direction is comparable to the channel length. A fraction of charge sharing at S/D junction is leading to threshold voltage lowering.
The results imply that deeper junction is formed by boron implantation again. In contrast, BF2 extension is constructive against threshold voltage roll-off due to shallower junction depth, as described by the forward mode measurement shown in Fig. 3.17. The results clearly indicate that boron implantation is not suitable for forming ultra shallow junction in deep-submicron devices.
To further inspect leakage current in forward mode, we apply various drain voltages
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to BF2 extension side. As shown in Fig. 3.24, the leakage currents are extremely dependent on the drain bias, which are proportional to the electric filed on the gate and drain overlap region. When the field crowding occurs in drain junction of the device, the increased junction leakage current is called gate-induced drain leakage (GIDL). The vertical electric field at drain side is enormous when a higher drain voltage is applied. Additional evidence is the temperature effect represented in Fig.
3.25. If it is caused by the reverse-biased p-n junction, it should show strong temperature dependence. The linear current at drain bias of -0.05V fits this description, but the saturation current does not show any strong temperature dependence.
3.3 NBTI and CHC Degradations on PMOSFETs 3.3.1 Background
It is well-known that integrated circuits are inevitably operated at higher and higher temperature as the device density increases. Moreover, the scaling of gate dielectric has rendered NBTI the major factor that limits the lifetime of PMOSFETs rather than hot-carrier degradation [42]. Temperature effect and quality control of the ultrathin gate dielectric thus become serious reliability issues. In this work, we investigate the degradation of PMOS stressed under either NBTI mode or CHC mode and examine which one might cause worse degradation.
Most of current understanding about the NBTI effect is on the basis of reaction-diffusion (R-D) model [43]. The generation of interface traps and fixed oxide charges during the stress brings about the shift in threshold voltage. Holes and hydrogen (H) species generated by the Si-H bonds breaking during NBTI stress play important roles. The mechanisms are expressed as follows [44]:
H
o hydrogen atom. Equations (3.3) and (3.4) can be used to represent the generation of interface trap (Nit) and fixed oxide charge (Nf), respectively. The net contribution to the total threshold voltage shift is thus given by
where q is electron charge and Cox is the oxide capacitance.
In general, R-D model is used to express interface generation by the following
where kF is Si-H dissociation rate constant, kR is rate of reverse annealing of Si-H, N0
is the total number of Si-H bonds, NH is hydrogen density, and DH is hydrogen diffusion coefficient. Equation (3.7) is related to the diffusion of neutral H and shows power-law dependence with stress time. However, fixed oxide charges are arduous to charge and discharge due to their locations inside oxide. Thus, trapping or de-trapping of holes is a fast component and difficult to govern [46]. In our work, we perform conventional DC method including measure-stress-measure (MSM) technique aimed at extracting the generated interface-state density.
Hot-carrier effect has received much attention in past years. The lucky electron model is widely used to describe the observed results [47]. The worst case of hot-carrier effect for NMOSFETs usually occurs at maximum substrate current [48],
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although still not clear for PMOSFETs. Several reports showed that the CHC effect in short-channel devices at high temperature is even worse than NBTI [49-51]. We choose the condition of CHC stress with the same voltages applied to both gate and drain at an elevated temperature to verify the aforementioned issue.
3.3.2 Channel Length and Gate Stack Dependences on NBTI
In this section, we investigate the static NBTI effect in poly-Si gated PMOSFETs.
Effects of channel length and different gate stack modules are evaluated. Figure 3.26 shows threshold voltage shift versus stress time in B-gate devices. As anticipated in devices with ultra-thin gate oxide, NBTI effect is manifested with increasing temperature or decreasing channel length. The temperature effect is particularly pronounced for the short-channel device. However, the behavior seems different in BF2-gate devices, as shown in Fig. 3.27. In this figure, although NBTI effect is still augmenting as channel length reduces at room temperature, there is no significant channel dependence at 125 ℃. The difference between the two types of devices can be interpreted by the fluorine incorporation [29][52]. Fluorine incorporation is conducive in reducing the donor-like interface traps under NBTI stress. That is, the strain at the interface is relaxed or the weak Si-H bonds are replaced by the robust Si-F bonds [53]. It has been reported that the formation of Si-F bonds could effectively decrease the generation of interface traps of NBTI due to the higher binding energy than the Si-H bonds [54]. According to the R-D model, the holes in the inversion layer at elevated temperature tend to interact with and break the Si-H bonds, resulting in the dissociation of hydrogen atoms and generation of interface traps. On the contrary, the robust Si-F bonds are less likely to be broken and generate interface traps. Note that the S/D extensions were also implanted with BF2 for the BF2-gate devices, the gate and S/D overlap regions thus contain abundant fluorine
atoms to form Si-F bonds. Therefore, the short-channel devices possess more Si-F bonds at interface in the channel as compared with the long-channel one.
In Fig. 3.28 we compare the results of the devices characterized at 125℃.
Apparently the short-channel device with B-gate performs the worst among the devices. Moreover, the results indicate that long-channel devices essentially have nothing to do with fluorine incorporation. It is elucidated that both fluorine incorporation in gate and overlap regions can influence the NBTI effect. Figure 3.29 illustrates the results of charge pumping measurements performed on the long-channel B-gate devices showing that only few interface traps are generated after NBTI stress, but the short-channel device tells a quite different story in Fig. 3.30. Results of the normal and reverse lateral charge pumping measurements are shown in Fig. 3.31 Normal and reverse modes mean the source and drain side, respectively, is floating during the measurements (see the measurement setup described in Chap. 2). The results exhibit that the generated interface traps are symmetrical to the center of the channel.
3.3.3 Comparisons between CHC and NBTI Stresses
To explore the CHC effect, we apply the same overdrive voltage (V = Vth -2V) on both gate and drain terminals while the source is grounded. Besides, we measure the currents under forward or reverse modes (see Fig. 3.32) to extract threshold voltage shift. Fig. 3.33 shows the threshold voltage shifts after CHC or NBTI stress.
As can be seen in the figure, the NBTI mode shows worse degradation while the results of the CHC effects under forward or reverse modes look quite different. Figure 3.34 depicts that the CHC mode generates fewer interface traps as compared with the NBTI mode, consistent with the less voltage shift. The results of lateral charging pumping measurements are shown in Fig. 3.35. In the figure we confirm that more
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interface traps are generated near the drain side, leading to more threshold voltage shift for the forward mode shown in Fig. 3.34. At present, the lucky electron model is
interface traps are generated near the drain side, leading to more threshold voltage shift for the forward mode shown in Fig. 3.34. At present, the lucky electron model is