Chapter 1 Introduction
1.2 Organization of This Dissertation
In Chapter 2, some ESD protection devices such as diode will be introduced.
Four discharge path including positive-to-VSS(PS) mode, negative-to-VSS (NS) mode, positive-to-VDD (PD) mode, and negative-to-VDD (ND) mode of each circuit will be introduced in this chapter.
In Chapter 3, inductor-assisted silicon-controlled rectifier (LASCR) ESD
3
protection devices will be introduced in detail. In this study, all testing devices are fabricated in 0.18um CMOS process. This chapter also includes simulation and measurement results of LASCR.
In Chapter 4, K/Ka-band low-noise amplifier (LNA) has been fabricated in 0.18um CMOS process. In this chapter, some parameters of the LNA such as S-parameter and stability will be introduced. Next, the design procedure of LNA will be described, including the selection of transistor and design of the matching network. The LNA will also be equipped with the ESD protection device to measure the ESD robustness of the circuit.
In Chapter 5, the conclusions and some suggestions for future investigation have been indicated.
4
Chapter 2
ESD Protection Device for RF Applications
2.1 Introduction
Nanoscale CMOS technologies have been used to implement the high-frequency integrated circuits with the advantages of scaling-down feature size, low power consumption, high integration capability, improving high-frequency characteristics, and low cost for mass production [1]. However, the MOS transistors are very sensitive to the electrostatic discharges (ESD) events [2], [3].
In order to sustain the required ESD robustness, such as 2kV in human-body model (HBM) [4], [5], the on-chip ESD protection circuit must be equipped for the pads that may be stressed by ESD, including the input/output (I/O) pads [6], as shown in Fig. 2.1. Conventional ESD protection devices with large dimensions have large parasitic capacitances. The parasitic capacitance will cause signal loss from the pad to ground. Therefore, the ESD protection device couldn’t introduce too large parasitic capacitance to degrade the circuit performance [7].
The conventional on-chip ESD protection scheme is shown in Fig. 2.2, where dual diodes at I/O pad are assisted with the power-rail ESD clamp circuit to prevent internal circuits from ESD damage [6]-[8]. The diode is typically used as effective on-chip ESD protection device due to the small parasitic loading effect and high ESD robustness [9], [10]. However, as the operating frequency of circuits increase, the parasitic capacitance is more strictly limited. To overcome this challenge, several prior designs have been reported. The ESD
5
protection designs with T-coil [11] and T-diode [12] have been presented for teen GHz applications. The stacked diodes [13] and inductor-to-ground [14] have been presented for 24GHz applications. Some ESD protection designs for 60GHz applications have been presented, including inductor-to-ground [15], [16], distributed ESD protection [17], modified LC tank [18], inductor-trigger SCR [19], diodes hidden behind an inductor [20], T-coil with distributed ESD diodes [21], and pi-type ESD block [22].
Fig. 2.1. Whole-chip ESD protection for internal circuit.
Fig. 2.2. Conventional ESD protection with dual diodes.
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2.2 Whole-Chip ESD Protection Design
Electrostatic discharge (ESD) becomes an important issue on the reliability of integrated circuit (IC). The advanced processes obviously degrade the ESD robustness of IC’s in the CMOS technologies. Generally, a typical specification for an RF circuit on human-body-model (HBM) ESD robustness and machine-model (MM) ESD robustness are 2 kV and 200 V, respectively [23], [24]. Both of them are used to evaluate the robustness of the ESD when the IC has been charged through touching by human body or machine. The equivalent circuits of HBM and MM ESD tests are show in Fig. 2.3(a) and (b), respectively. In the HBM ESD test, the charges stored in the capacitor would be discharged through the 1.5kΩ resistor into the device under test (DUT). On the other hand, the charges stored in the capacitor would be discharged directly into the DUT in the MM ESD test.
Therefore, it is necessary to adding the ESD protection circuit beside I/O pads, which provide electrostatic discharge path and keep the circuit without damage from ESD stress. There’s also equipped power-rail ESD clamp circuit between 𝑉𝐷𝐷 and 𝑉𝑆𝑆 to realize whole-chip ESD protection design.
7
(a)
(b)
Fig. 2.3. Equivalent circuits of (a) HBM and (b) MM ESD tests.
8
2.3 CMOS ESD Protection Device for RF Circuit
2.3.1 ESD Protection Design with Diodes.
Forward bias diode is an ESD protection device with good ESD robustness and has been widely used in the design of RF electrostatic discharge protection circuit. Fig. 2.4 show the four ESD-stress modes on I/O pads. When positive electrostatic discharge from I/O pads to 𝑉𝐷𝐷 (positive-to-𝑉𝐷𝐷, PD), electrostatic current will release by forward bias 𝐷𝑃. When positive electrostatic discharge from I/O pads to 𝑉𝑆𝑆 (positive-to-𝑉𝑆𝑆, PS), electrostatic current will flowing through 𝐷𝑃 and then release by the power-rail ESD clamp circuit. When negative electrostatic discharge form I/O pads to 𝑉𝑆𝑆 (negative-to-𝑉𝑆𝑆, NS), electrostatic current will release by forward bias 𝐷𝑁 . When negative electrostatic discharge from I/O pads to 𝑉𝐷𝐷 (negative-to- 𝑉𝐷𝐷 , ND), electrostatic current will flowing through the power-rail ESD clamp circuit and release by forward bias 𝐷𝑁. However, the parasitic capacitance of ESD protection diodes would degrade the performance of circuit when circuit operating frequency gradually increase.
Fig. 2.4. ESD protection design with diodes.
Internal
9
2.3.2 ESD Protection Design with SCR
Silicon-controlled rectifier (SCR) device consists of a lateral NPN and a vertical PNP bipolar transistor to form a 4-layer PNPN structure is shown in Fig.
2.5. This four-layer structure has the same performance with the structure which will occur the latch up problem. SCR has excellent ability to provide the good ESD robustness with minimal layout area. Fig. 2.5 also marked the electrostatic discharge path when this circuit is affected by ESD stress. Compared with the diode, silicon controlled rectifier has smaller parasitic capacitance. Furthermore, advanced process operating voltage gradually decline lets the risk of the latch up gradually reduced. Therefore, SCR becomes a very potentially ESD protection device. In the practical application, Silicon-controlled rectifier must design with the trigger circuit to enhance the turn on speed. The trigger circuit may consist of transistors, diodes, resistors, capacitors and other active and passive components.
Fig. 2.5. ESD protection design with SCR.
Internal
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2.3.3 ESD Protection Design with Inductor-Triggered SCR.
When the operating frequency of the circuit is gradually increased to more than ten GHz, the parasitic capacitance of silicon controlled rectifier may still too large to the high-frequency circuits. Thus, Fig. 2.6 is a concept based on silicon-controlled rectifiers parallel with an inductor [25]. This design can lets the signal loss be zero because the equivalent impedance at the resonant frequency is infinite. However, this design requires a MOS switch. This switch is operating at high frequencies and it should turn on when the circuit stressed by ESD. Furthermore, the control signals of this MOS switch required by the power clamp ESD protection circuit. Therefore, this design might be more complex to achieve.
Fig. 2.6. ESD protection design with LTSCR.
Internal
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Chapter 3
Design of Inductor-Assisted Silicon-Controlled Rectifier
3.1 Introduction
The integrated circuits operated in K-band (18-27GHz) and Ka-band (26.5-40GHz) have been developed for short-range communication [26]-[30]. For example, 24GHz for wireless network solutions [26], 22-29GHz for short-range automotive radars [27], and 22-46GHz for local multipoint distribution service [28], [29]. The ESD protection design for the integrated circuits operated in K/Ka band is needed. In this work, a novel inductor-assisted silicon-controlled rectifier (LASCR) device is proposed for effective on-chip ESD protection in K/Ka-band.
Fig. 3.1. SCR cross-sectional view and ESD current paths.
The proposed LASCR is shown in Fig. 3.1, which consists of an SCR [31], an inductor, and a diode string. The ESD current path from anode to cathode
12
consists of P+/N-well/P-well/N+ SCR. The diode string is used to enhance the turn-on efficiency of SCR [32], [33]. The ESD current path from cathode to anode consists of P-well/N-well diode and inductor. The equivalent circuit of the LASCR is shown in Fig. 3.2(a), where 𝑄𝑃𝑁𝑃 is formed by the P+, N-well, and P-well, and the 𝑄𝑁𝑃𝑁 is formed by the N-well, P-well, and N+. As ESD zapping from anode to cathode, the positive-feedback regenerative mechanism of 𝑄𝑃𝑁𝑃 and 𝑄𝑁𝑃𝑁 results in the SCR device highly conductive to make SCR very robust against ESD stresses. Under normal circuit operating condition, the inductor can resonate with the parasitic capacitance.
(a) (b)
Fig. 3.2. Equivalent circuit of LASCR, where SCR expressed by (a) BJT and (b) diodes.
To simulate this device by using foundry provided model, the equivalent circuit of the LASCR can be further expressed by P+/N-well diode (𝐷𝑃+ 𝑁𝑊⁄ ),
P-13
well/N-well diode (𝐷𝑃𝑊 𝑁𝑊⁄ ), inductor (L), and diode string (𝐷1, ..., 𝐷𝑛), as shown in Fig. 3.2(b). The dimension of SCR depends on the required ESD robustness, and the diode numbers and dimension of diode string depend on the trigger ability. Once the dimension of SCR has been chosen, the inductor can be designed to minimize the high-frequency performance degradation by using
L = 1
𝐶𝑃+ 𝑁−𝑤𝑒𝑙𝑙⁄ ×(2𝜋𝑓0)2 (3.1) where 𝑓0 is the operating frequency and 𝐶𝑃+ 𝑁𝑊⁄ is the parasitic capacitance of 𝐷𝑃+ 𝑁𝑊⁄ and is show in Fig. 3.3. Of course, the high-frequency performances are also affected by the parasitic resistances of diodes and inductor, and they can be simulated by using the real diode and inductor models.
CP+/N-well
Fig. 3.3. Equivalent circuit of LASCR.
Fig. 2.8 shows that electrostatic discharge path of inductor-assisted silicon-controlled rectifier when the circuit is stressed by ESD. When positive electrostatic discharge from I/O pads to VSS (positive-to-VSS, PS), electrostatic current will release by silicon-controlled rectifier. When positive electrostatic
14
discharge from I/O pads to VDD (positive-to-VDD, PD), electrostatic current will flows through silicon-controlled rectifier to VSS and then release by power-rail ESD clamp circuit. When negative electrostatic discharge form I/O pads to VSS (negative-to-VSS, NS), electrostatic current will release by inductor and PN junction (N − well P − well⁄ ) which is in the silicon-controlled rectifier. When negative electrostatic discharge from I/O pads to VDD (negative-to-VDD, ND), electrostatic current will flowing through the power-rail ESD clamp circuit and release by PN junction (N − well P − well⁄ ) and inductor. Besides, LASCR provide the bidirectional ESD current paths between I/O pads and VSS, so it can achieve the whole chip ESD protection by using only an LASCR and a power-rail ESD clamp circuit.
Fig. 3.4. Co-design of SCR and inductor’s ESD protection circuit.
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3.2 Design of LASCR
In this work, all LASCR devices are fabricated in 0.18 CMOS process and shown in Table 3.1. The sizes of SCR are selected as 30um and 60um. Since the circuit which fabricated in 0.18 CMOS process typically operated at 1.8V, the diode number in the diode string should more then 3, so as not to trigger the ESD protection device when the circuit is under the normal operation mode. As the result, the diode numbers in the diode string are selected as 3 and 5, and the size of each diode is 15um or 30um. The CP+ NW⁄ of 30um and 60um SCR around 30GHz are ~60fF and ~120fF, respectively. Therefore, the values of required L for K/Ka-band applications are 460pH and 230pH, respectively. The simulation of inductor is completed by using HFSS, as shown in Fig. 3.3.
Fig. 3.5. 3D EM simulation of inductor.
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Table 3.1
Design specification of the proposed LASCR
Cell Name (DTSCR) and diode devises. Table 3.2 show that size of SCR are selected to be 30um and 60um, while the diode numbers in the diode string are 3 and 5, the dimension of each diode is 15um or 30um, four devices are not equipped with the power-rail ESD clamp circuit. Fig. 3.6 is the equivalent circuit of DTSCR and can be seen that inductance is the only difference between DTSCR and LASCR. The size of diode device is show in Table 3.3.
Fig. 3.6. Equivalent circuit of DTSCR.
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Table 3.2
Design specification of the proposed DTSCR
Cell Name
Design specification of the proposed diode
Cell Name Diode Type Diode Width (um)
The high-frequency characteristics are simulated by using the microwave circuit simulator ADS with the selected device dimensions. In the two-port simulation, a signal source with 50Ω impedance drives the port 1 and a 50Ω load is connected to the port 2. The port 1, port 2, and the anode of LASCR are connected together, and the cathode of LASCR is connected to ground. The simulated S11 and S21 of test devices are compared in Fig. 3.5. At 30GHz, the
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30um dual diodes (Dual Diodes_W30) have 2.5dB loss, while the 30um LASCR with three diodes (LASCR_W30_3D), the 30um LASCR with five diodes (LASCR_W30_5D), the 60um LASCR with three diodes (LASCR_W60_3D), and the 60um LASCR with five diodes (LASCR_W60_5D) only have 0.5dB, 0.4dB, 0.8dB, and 0.8dB loss, respectively. Among the K/Ka-band, the loss of each LASCR is lower than 3dB, which is more suitable for ESD protection.
The proposed devices under normal power-on conditions and ESD transient events are simulated by using HSPICE. Fig. 3.6(a) shows the HSPICE-simulated voltage/current waveforms of one test device, LASCR_W30_5D, under the normal power-on condition. Under the normal power-on condition, the dc bias of anode is raised from 0V to 1.8V with 0.5ms rise time. The test device is kept off with very low leakage current. Fig. 3.6(b) shows the simulated voltage/current waveforms of LASCR_W30_5D under the ESD transition, where a 0V-to-5V voltage pulse with 10ns rise time is applied to the test device to simulate the fast transient voltage of HBM ESD event. When a positive fast-transient ESD voltage is applied to anode with cathode grounded, the LASCR_W30_5D can be turned on to discharge ESD current from anode to cathode. With the limited voltage height of 5 V in the voltage pulse, the simulation result can check the clamping ability of LASCR before the internal circuit breakdown.
19
(a) (b) Fig. 3.7. Simulated 𝑆11 and 𝑆21 of test devices.
(a) (b)
Fig. 3.8. Simulated voltage/current waveforms of LASCR_W30_5D under (a) normal power-on condition and (b) ESD-like transition.
3.5 Experimental Results of Test Devices
Five test devices have been fabricated in a nanoscale CMOS process. All test devices are implemented with ground-signal-ground (G-S-G) pads to facilitate on-wafer two-port S-parameters measurement. Fig. 3.7 shows the chip micrograph of one test device, LASCR_W30_3D. The other LASCR devices
20
have almost the same layout arrangement. The cell area of LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D are 100x95um2, 100x105um2, 90x90um2, and 90x100um2, respectively.
Fig. 3.9. Chip micrograph of LASCR_W30_3D.
3.5.1 High-Frequency Performances
In order to extract the intrinsic characteristics of the test devices in high frequencies, the parasitic effects of the G-S-G pads have been removed by using the de-embedding technique [34]. With the on-wafer two-port measurement, the S-parameters of these test devices have been extracted. The source and load resistances to the test circuits are kept at 50 Ω. The measured S11 and S21 versus frequencies among the test devices are shown in Fig. 3.8. As shown in Fig. 3.8(a), the LASCR devices exhibit good input matching (S11 < -15dB) around 30 GHz, while Dual Diodes_W30 only has S11 = -8.1dB. At 30GHz, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D have 1.3dB, 1.4dB, 1.6dB, and 1.5dB loss, respectively, while Dual Diodes_W30 has 2.7dB loss.
21
(a) (b) Fig. 3.10. Measured 𝑆11 and 𝑆21 of test devices.
3.5.2 ESD Robustness
The HBM ESD robustness of each device is tested. The failure criterion is defined as the I-V curve seen between test pads shifting over 30% from its original curve after ESD stressed at every ESD test level. According to the measurement results, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D can pass +4.5kV, +4kV, +7.5kV, and +7.5kV HBM ESD tests, respectively. Besides, these LASCR devices can also pass 4kV, 4kV, -7.5kV, and -7.5kV HBM ESD tests, respectively. The Dual Diodes_W30 can only pass +3kV and -3.5kV HBM ESD tests.
To investigate the turn-on behavior and the I-V characteristics in high-current regions of the test devices, the transmission line pulsing (TLP) system with a 10ns rise time and a 100ns pulse width is used. The trigger voltage (𝑉𝑡1), holding voltage (𝑉ℎ), and secondary breakdown current (𝐼𝑡2) of test devices in the time domain of HBM ESD event can be extracted from the TLP-measured I-V curves. The TLP-measured I-I-V curves of test devices are shown in Fig. 3.9.
Once the pulses stressed to the test devices, LASCR_W30_3D and
22
LASCR_W60_3D (LASCR_W30_5D and LASCR_W60_5D) can be triggered on at ~5V (~7.6V). The 𝑉ℎ of all LASCR devices exceed 𝑉𝐷𝐷 (1.8V in the given CMOS process), which is safe from latchup event. For the current-handling ability of ESD protection devices, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D can achieve the TLP-measured 𝐼𝑡2 of 2.4A,2.1A, 4.2A, and 4.0A, respectively, while Dual Diodes_W30 has only 1.8A. The turn-on behavior can ensure the effective ESD protection capability of the proposed LASCR.
The standby leakage current of the test devices can also be measured by using the TLP system. At 1.8V bias, all LASCR devices have the leakage current of <1nA. All measurement results of the test devices are summarized in Table 3.4.
Fig. 3.11. TLP I-V curves of test devices.
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Table 3.4
Design Parameters and Measurement Results of Test Devices
LASCR_W30
Level +4.5kV/-4kV +4kV/-4kV +7.5kV/-7.5kV +7.5kV/-7.5kV +3kV/-3.5kV
TLP 𝑽𝒕𝟏 5.1V 7.6V 5.0V 7.6V N/A
The failure analysis (FA) has been done to seek the failure location. The FA picture of the LASCR_W30_3D after 5kV HBM ESD stress, LASCR_W30_5D after 4.5kV HBM ESD stress, LASCR_W60_3D after 8kV HBM ESD stress, and LASCR_W60_5D after 8kV HBM ESD stress are shown in Figs. 3.12-3.15. After HBM ESD stress, the damaged regions are all located on the SCR device.
24 diode string
P+
N+
P+
N+
Fig. 3.12. The SEM pictures of the LASCR_W30_3D after +5kV HBM stresses.
diode string
P+
N+
P+
N+
Fig. 3.13. The SEM pictures of the LASCR_W30_5D after +4.5kV HBM stresses.
25 diode string
N+
P+
N+
P+
Fig. 3.14. The SEM pictures of the LASCR_W60_3D after +8kV HBM stresses.
diode string
N+
P+
P+
N+
N+
P+
Fig. 3.15. The SEM pictures of the LASCR_W60_5D after +8kV HBM stresses.
26 LASCR_W60_3D is 0.9 nA, and LASCR_W60_5D is 0.5 nA, respectively. At 100°C, leakage of LASCR_W30_3D is 4.5 nA, LASCR_W30_5D is 4.0 nA, LASCR_W60_3D is 7.9 nA, and LASCR_W60_5D is 8.6 nA, respectively. It can be seen that leakage of the LASCR devices are still small under high temperature.
3.6 Conclusion
The proposed ESD protection device of LASCR has been developed in nanoscale CMOS process for K/Ka-band applications. Verified in silicon chip, LASCR devices with 30um (LASCR_W30_3D and LASCR_W30_5D) and 60um (LASCR_W60_3D and LASCR_W60_5D) width can pass 4kV and 7.5kV HBM ESD tests, respectively, and they have the loss lower than 3dB in K/Ka-band. In fact, LASCR devices exhibit good high-frequency performances between 0~40 GHz, so they can also be used for wideband or high-speed applications. Measurement results verify the high-frequency performances and confirm the ESD protection ability of LASCR. Therefore, the proposed LASCR can be a good solution for ESD protection.
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Chapter 4
K/Ka-Band Low Nosie Amplifier
4.1 Introduction
As technology progresses, more important applications are use in the K/Ka band, such as wireless network, short-range automotive radars, and local multipoint distribution service. Considering the sensitivity of the system in RF applications, the low noise receiver is necessary. In the receiver system, low noise amplifier (LNA) is a very important and critical circuit as shown in Fig.
4.1.
Fig. 4.1. Receiver system architecture.
The function of low noise amplifier is to provide enough gain to amplify the weak RF signal received by antenna and suppress the influence of noise generated by subsequent stage at the same time. It can also improve signal to
28
noise ratio (SNR) and let signal without distortion. Thereby allowing received signals can be correctly demodulation out by the subsequent circuit.
Therefore, the needed of accurate transistor small signal model and noise model when design the low noise amplifier is necessary. Because the noise from transistor is the main noise of the overall circuit and may interfere RF signal, then signal will distortion and couldn’t be demodulated by the subsequent stage circuit. Therefore, an accurate transistor small signal model and noise model is very important.
4.2 Source of Transistor Noise
Transistor noise generated by interpreting the results as Brownian motion caused. However, transistors is susceptible noise in the small signal operating
Transistor noise generated by interpreting the results as Brownian motion caused. However, transistors is susceptible noise in the small signal operating