ESD Protection Design with Inductor-Triggered SCR

When the operating frequency of the circuit is gradually increased to more than ten GHz, the parasitic capacitance of silicon controlled rectifier may still too large to the high-frequency circuits. Thus, Fig. 2.6 is a concept based on silicon-controlled rectifiers parallel with an inductor [25]. This design can lets the signal loss be zero because the equivalent impedance at the resonant frequency is infinite. However, this design requires a MOS switch. This switch is operating at high frequencies and it should turn on when the circuit stressed by ESD. Furthermore, the control signals of this MOS switch required by the power clamp ESD protection circuit. Therefore, this design might be more complex to achieve.

Fig. 2.6. ESD protection design with LTSCR.

Internal

11

Chapter 3

Design of Inductor-Assisted Silicon-Controlled Rectifier

3.1 Introduction

The integrated circuits operated in K-band (18-27GHz) and Ka-band (26.5-40GHz) have been developed for short-range communication [26]-[30]. For example, 24GHz for wireless network solutions [26], 22-29GHz for short-range automotive radars [27], and 22-46GHz for local multipoint distribution service [28], [29]. The ESD protection design for the integrated circuits operated in K/Ka band is needed. In this work, a novel inductor-assisted silicon-controlled rectifier (LASCR) device is proposed for effective on-chip ESD protection in K/Ka-band.

Fig. 3.1. SCR cross-sectional view and ESD current paths.

The proposed LASCR is shown in Fig. 3.1, which consists of an SCR [31], an inductor, and a diode string. The ESD current path from anode to cathode

12

consists of P+/N-well/P-well/N+ SCR. The diode string is used to enhance the turn-on efficiency of SCR [32], [33]. The ESD current path from cathode to anode consists of P-well/N-well diode and inductor. The equivalent circuit of the LASCR is shown in Fig. 3.2(a), where 𝑄_𝑃𝑁𝑃 is formed by the P+, N-well, and P-well, and the 𝑄_𝑁𝑃𝑁 is formed by the N-well, P-well, and N+. As ESD zapping from anode to cathode, the positive-feedback regenerative mechanism of 𝑄_𝑃𝑁𝑃 and 𝑄_𝑁𝑃𝑁 results in the SCR device highly conductive to make SCR very robust against ESD stresses. Under normal circuit operating condition, the inductor can resonate with the parasitic capacitance.

(a) (b)

Fig. 3.2. Equivalent circuit of LASCR, where SCR expressed by (a) BJT and (b) diodes.

To simulate this device by using foundry provided model, the equivalent circuit of the LASCR can be further expressed by P+/N-well diode (𝐷_{𝑃+ 𝑁𝑊⁄} ),

P-13

well/N-well diode (𝐷_{𝑃𝑊 𝑁𝑊⁄} ), inductor (L), and diode string (𝐷₁, ..., 𝐷_𝑛), as shown in Fig. 3.2(b). The dimension of SCR depends on the required ESD robustness, and the diode numbers and dimension of diode string depend on the trigger ability. Once the dimension of SCR has been chosen, the inductor can be designed to minimize the high-frequency performance degradation by using

L = ¹

𝐶_{𝑃+ 𝑁−𝑤𝑒𝑙𝑙}⁄ ×(2𝜋𝑓0)² (3.1) where 𝑓₀ is the operating frequency and 𝐶_{𝑃+ 𝑁𝑊}⁄ is the parasitic capacitance of 𝐷_{𝑃+ 𝑁𝑊⁄} and is show in Fig. 3.3. Of course, the high-frequency performances are also affected by the parasitic resistances of diodes and inductor, and they can be simulated by using the real diode and inductor models.

C_P+/N-well

Fig. 3.3. Equivalent circuit of LASCR.

Fig. 2.8 shows that electrostatic discharge path of inductor-assisted silicon-controlled rectifier when the circuit is stressed by ESD. When positive electrostatic discharge from I/O pads to V_SS (positive-to-V_SS, PS), electrostatic current will release by silicon-controlled rectifier. When positive electrostatic

14

discharge from I/O pads to V_DD (positive-to-V_DD, PD), electrostatic current will flows through silicon-controlled rectifier to V_SS and then release by power-rail ESD clamp circuit. When negative electrostatic discharge form I/O pads to V_SS (negative-to-V_SS, NS), electrostatic current will release by inductor and PN junction (N − well P − well⁄ ) which is in the silicon-controlled rectifier. When negative electrostatic discharge from I/O pads to V_DD (negative-to-V_DD, ND), electrostatic current will flowing through the power-rail ESD clamp circuit and release by PN junction (N − well P − well⁄ ) and inductor. Besides, LASCR provide the bidirectional ESD current paths between I/O pads and V_SS, so it can achieve the whole chip ESD protection by using only an LASCR and a power-rail ESD clamp circuit.

Fig. 3.4. Co-design of SCR and inductor’s ESD protection circuit.

15

3.2 Design of LASCR

In this work, all LASCR devices are fabricated in 0.18 CMOS process and shown in Table 3.1. The sizes of SCR are selected as 30um and 60um. Since the circuit which fabricated in 0.18 CMOS process typically operated at 1.8V, the diode number in the diode string should more then 3, so as not to trigger the ESD protection device when the circuit is under the normal operation mode. As the result, the diode numbers in the diode string are selected as 3 and 5, and the size of each diode is 15um or 30um. The C_{P+ NW⁄} of 30um and 60um SCR around 30GHz are ~60fF and ~120fF, respectively. Therefore, the values of required L for K/Ka-band applications are 460pH and 230pH, respectively. The simulation of inductor is completed by using HFSS, as shown in Fig. 3.3.

Fig. 3.5. 3D EM simulation of inductor.

16

Table 3.1

Design specification of the proposed LASCR

Cell Name (DTSCR) and diode devises. Table 3.2 show that size of SCR are selected to be 30um and 60um, while the diode numbers in the diode string are 3 and 5, the dimension of each diode is 15um or 30um, four devices are not equipped with the power-rail ESD clamp circuit. Fig. 3.6 is the equivalent circuit of DTSCR and can be seen that inductance is the only difference between DTSCR and LASCR. The size of diode device is show in Table 3.3.

Fig. 3.6. Equivalent circuit of DTSCR.

17

Table 3.2

Design specification of the proposed DTSCR

Cell Name

Design specification of the proposed diode

Cell Name Diode Type Diode Width (um)

The high-frequency characteristics are simulated by using the microwave circuit simulator ADS with the selected device dimensions. In the two-port simulation, a signal source with 50Ω impedance drives the port 1 and a 50Ω load is connected to the port 2. The port 1, port 2, and the anode of LASCR are connected together, and the cathode of LASCR is connected to ground. The simulated S11 and S21 of test devices are compared in Fig. 3.5. At 30GHz, the

18

30um dual diodes (Dual Diodes_W30) have 2.5dB loss, while the 30um LASCR with three diodes (LASCR_W30_3D), the 30um LASCR with five diodes (LASCR_W30_5D), the 60um LASCR with three diodes (LASCR_W60_3D), and the 60um LASCR with five diodes (LASCR_W60_5D) only have 0.5dB, 0.4dB, 0.8dB, and 0.8dB loss, respectively. Among the K/Ka-band, the loss of each LASCR is lower than 3dB, which is more suitable for ESD protection.

The proposed devices under normal power-on conditions and ESD transient events are simulated by using HSPICE. Fig. 3.6(a) shows the HSPICE-simulated voltage/current waveforms of one test device, LASCR_W30_5D, under the normal power-on condition. Under the normal power-on condition, the dc bias of anode is raised from 0V to 1.8V with 0.5ms rise time. The test device is kept off with very low leakage current. Fig. 3.6(b) shows the simulated voltage/current waveforms of LASCR_W30_5D under the ESD transition, where a 0V-to-5V voltage pulse with 10ns rise time is applied to the test device to simulate the fast transient voltage of HBM ESD event. When a positive fast-transient ESD voltage is applied to anode with cathode grounded, the LASCR_W30_5D can be turned on to discharge ESD current from anode to cathode. With the limited voltage height of 5 V in the voltage pulse, the simulation result can check the clamping ability of LASCR before the internal circuit breakdown.

19

(a) (b) Fig. 3.7. Simulated 𝑆₁₁ and 𝑆₂₁ of test devices.

(a) (b)

Fig. 3.8. Simulated voltage/current waveforms of LASCR_W30_5D under (a) normal power-on condition and (b) ESD-like transition.

3.5 Experimental Results of Test Devices

Five test devices have been fabricated in a nanoscale CMOS process. All test devices are implemented with ground-signal-ground (G-S-G) pads to facilitate on-wafer two-port S-parameters measurement. Fig. 3.7 shows the chip micrograph of one test device, LASCR_W30_3D. The other LASCR devices

20

have almost the same layout arrangement. The cell area of LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D are 100x95um², 100x105um², 90x90um², and 90x100um², respectively.

Fig. 3.9. Chip micrograph of LASCR_W30_3D.

3.5.1 High-Frequency Performances

In order to extract the intrinsic characteristics of the test devices in high frequencies, the parasitic effects of the G-S-G pads have been removed by using the de-embedding technique [34]. With the on-wafer two-port measurement, the S-parameters of these test devices have been extracted. The source and load resistances to the test circuits are kept at 50 Ω. The measured S11 and S21 versus frequencies among the test devices are shown in Fig. 3.8. As shown in Fig. 3.8(a), the LASCR devices exhibit good input matching (S11 < -15dB) around 30 GHz, while Dual Diodes_W30 only has S11 = -8.1dB. At 30GHz, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D have 1.3dB, 1.4dB, 1.6dB, and 1.5dB loss, respectively, while Dual Diodes_W30 has 2.7dB loss.

21

(a) (b) Fig. 3.10. Measured 𝑆₁₁ and 𝑆₂₁ of test devices.

3.5.2 ESD Robustness

The HBM ESD robustness of each device is tested. The failure criterion is defined as the I-V curve seen between test pads shifting over 30% from its original curve after ESD stressed at every ESD test level. According to the measurement results, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D can pass +4.5kV, +4kV, +7.5kV, and +7.5kV HBM ESD tests, respectively. Besides, these LASCR devices can also pass 4kV, 4kV, -7.5kV, and -7.5kV HBM ESD tests, respectively. The Dual Diodes_W30 can only pass +3kV and -3.5kV HBM ESD tests.

To investigate the turn-on behavior and the I-V characteristics in high-current regions of the test devices, the transmission line pulsing (TLP) system with a 10ns rise time and a 100ns pulse width is used. The trigger voltage (𝑉_𝑡1), holding voltage (𝑉_ℎ), and secondary breakdown current (𝐼_𝑡2) of test devices in the time domain of HBM ESD event can be extracted from the TLP-measured I-V curves. The TLP-measured I-I-V curves of test devices are shown in Fig. 3.9.

Once the pulses stressed to the test devices, LASCR_W30_3D and

22

LASCR_W60_3D (LASCR_W30_5D and LASCR_W60_5D) can be triggered on at ~5V (~7.6V). The 𝑉_ℎ of all LASCR devices exceed 𝑉_𝐷𝐷 (1.8V in the given CMOS process), which is safe from latchup event. For the current-handling ability of ESD protection devices, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D can achieve the TLP-measured 𝐼_𝑡2 of 2.4A,2.1A, 4.2A, and 4.0A, respectively, while Dual Diodes_W30 has only 1.8A. The turn-on behavior can ensure the effective ESD protection capability of the proposed LASCR.

The standby leakage current of the test devices can also be measured by using the TLP system. At 1.8V bias, all LASCR devices have the leakage current of <1nA. All measurement results of the test devices are summarized in Table 3.4.

Fig. 3.11. TLP I-V curves of test devices.

23

Table 3.4

Design Parameters and Measurement Results of Test Devices

LASCR_W30

Level +4.5kV/-4kV +4kV/-4kV +7.5kV/-7.5kV +7.5kV/-7.5kV +3kV/-3.5kV

TLP 𝑽𝒕𝟏 5.1V 7.6V 5.0V 7.6V N/A

The failure analysis (FA) has been done to seek the failure location. The FA picture of the LASCR_W30_3D after 5kV HBM ESD stress, LASCR_W30_5D after 4.5kV HBM ESD stress, LASCR_W60_3D after 8kV HBM ESD stress, and LASCR_W60_5D after 8kV HBM ESD stress are shown in Figs. 3.12-3.15. After HBM ESD stress, the damaged regions are all located on the SCR device.

24 diode string

P+

N+

P+

N+

Fig. 3.12. The SEM pictures of the LASCR_W30_3D after +5kV HBM stresses.

diode string

P+

N+

P+

N+

Fig. 3.13. The SEM pictures of the LASCR_W30_5D after +4.5kV HBM stresses.

25 diode string

N+

P+

N+

P+

Fig. 3.14. The SEM pictures of the LASCR_W60_3D after +8kV HBM stresses.

diode string

N+

P+

P+

N+

N+

P+

Fig. 3.15. The SEM pictures of the LASCR_W60_5D after +8kV HBM stresses.

26 LASCR_W60_3D is 0.9 nA, and LASCR_W60_5D is 0.5 nA, respectively. At 100^°C, leakage of LASCR_W30_3D is 4.5 nA, LASCR_W30_5D is 4.0 nA, LASCR_W60_3D is 7.9 nA, and LASCR_W60_5D is 8.6 nA, respectively. It can be seen that leakage of the LASCR devices are still small under high temperature.

3.6 Conclusion

The proposed ESD protection device of LASCR has been developed in nanoscale CMOS process for K/Ka-band applications. Verified in silicon chip, LASCR devices with 30um (LASCR_W30_3D and LASCR_W30_5D) and 60um (LASCR_W60_3D and LASCR_W60_5D) width can pass 4kV and 7.5kV HBM ESD tests, respectively, and they have the loss lower than 3dB in K/Ka-band. In fact, LASCR devices exhibit good high-frequency performances between 0~40 GHz, so they can also be used for wideband or high-speed applications. Measurement results verify the high-frequency performances and confirm the ESD protection ability of LASCR. Therefore, the proposed LASCR can be a good solution for ESD protection.

27

Chapter 4

K/Ka-Band Low Nosie Amplifier

4.1 Introduction

As technology progresses, more important applications are use in the K/Ka band, such as wireless network, short-range automotive radars, and local multipoint distribution service. Considering the sensitivity of the system in RF applications, the low noise receiver is necessary. In the receiver system, low noise amplifier (LNA) is a very important and critical circuit as shown in Fig.

4.1.

Fig. 4.1. Receiver system architecture.

The function of low noise amplifier is to provide enough gain to amplify the weak RF signal received by antenna and suppress the influence of noise generated by subsequent stage at the same time. It can also improve signal to

28

noise ratio (SNR) and let signal without distortion. Thereby allowing received signals can be correctly demodulation out by the subsequent circuit.

Therefore, the needed of accurate transistor small signal model and noise model when design the low noise amplifier is necessary. Because the noise from transistor is the main noise of the overall circuit and may interfere RF signal, then signal will distortion and couldn’t be demodulated by the subsequent stage circuit. Therefore, an accurate transistor small signal model and noise model is very important.

4.2 Source of Transistor Noise

Transistor noise generated by interpreting the results as Brownian motion caused. However, transistors is susceptible noise in the small signal operating conditions. Generally, transistor noise can be divided into thermal noise, distributed gate resistance noise, and flicker noise.

4.2.1 Channel thermal noise

Channel thermal noise is due to the electron perturbations within the transistor channel. Channel electrons excited by the heat and random motion, so that transistor produces random changes in voltage and current. These voltage and current changes produce thermal noise, and then define the effective noise power with equation (4.1)

𝑃_𝑎𝑣 = 𝑘𝑇∆𝑓 (4.1) where k is Boltzmann constant, which is 1.38 × 10⁻²³(J/K). T is the absolute temperature, ∆𝑓 is the noise bandwidth with units of Hz. By equation (4.1) knows that, when the conductor temperature increase, effective noise power will

29

increase.

Analysis the influence of thermal noise in the circuit would equivalent the thermal noise to a parallel noise current source, and must assume the transistor as ideal state without any noise. Schematic diagram is show in Fig. 4.2. The noise power equation is (4.2)

𝐼_𝑛²(f) = 4kTγ𝑔_𝑚 (4.2) where k is Boltzmann constant, which is 1.38 × 10⁻²³(J/K). T is the absolute temperature. 𝑔_𝑚 is the drain transduction value when bias is zero. Value of γ would greater than 1 in the short channel, and would be 2 3⁄ in the long channel.

Fig. 4.2. Transistor channel thermal noise model.

4.2.2 Distributed Gate Resistance Noise

During the CMOS process, the poly layer is used on the gate. Therefore, the gate will produce polysilicon resistors. Equation and model is show in equation (4.3) and Fig. 4.3, respectively.

𝑅_𝑔 = 𝑅_ℎ ^𝑊

3𝑛²𝐿 (4.3) In equation (4.3), 𝑅_ℎ is the polysilicon resistors, n is the number of transistors

30

finger, W and L are the transistors width and length, respectively. The equation of output noise provided by the distributed gate resistance is

𝑉_{𝑛,𝑜𝑢𝑡}² = 4𝑘𝑇^𝑅𝑔

3 (𝑔_𝑚𝑟_𝑜)² (4.4) From equation (4.3) and (4.4), if want to achieve low noise circuit design, use larger number of fingers and lower channel width in the same transistor size can make gate resistance smaller. Thereby reducing the noise generated by the resistor.

Fig. 4.3. CMOS transistors gate resistance model.

4.2.3 Flicker Noise

Flicker noise is the major noise when CMOS transistors operating at low frequencies. The flicker noise mostly occurs between the gate oxide layer and the silicon substrate surface. Due to silicon crystal and the surface at this interface will produce a discontinuous bond, when the current passes will randomly be captured and released, causing transistor drain current unstable and produce flicker noise, but when the frequency greater than a specific frequency,

31 Where K is the process parameters.

4.3 Parameters of Low-Noise Amplifier

4.3.1 Noise Figure

To know the amplifier noise figure (NF), we must first understand the noise factor (F). The definition of noise factor is the input signal-noise ratio dividing the output signal-noise ratio, and can calculated by equation (4.6).

F = ^{𝑆𝑁𝑅𝑖𝑛}

For example, in a two-stage amplifier, equation (4.7) show that two-stage amplifiers noise factor.

𝑁_𝑖𝑛𝐺₂ is the second-stage amplifiers noise factor. So we can use the results of the two-stage amplifier to infer the n-stage amplifier noise factor should be the following equation (4.8).

F = 𝐹₁+^𝐹2−1

𝐺₁ +^𝐹3−1

𝐺₁𝐺₂+ ⋯ + ^𝐹𝑛−1

𝐺₁𝐺₂…𝐺_𝑛−1 (4.8) By observation of equation (4.8), knows that multiple cascading amplifier noise

32

factor is mainly determined by the first-stage amplifier. Therefore, the first-stage amplifier matching network and architecture are the most important things during the design of low-noise amplifier. Other stage of amplifier is primarily responsible for increasing the gain. Finally, we can define the noise figure of the following equation (4.9). F in this equation is noise factor.

NF = 10 log 𝐹 (4.9)

4.3.2 Gain

In the low-noise amplifier design, gain is an important parameter to consider.

If the gain of low-noise amplifier not enough, it could be unable to suppress the noise of subsequent circuit. It also cause the large noise figure and let signal distortion. When design the RF amplifier, there have three kinds of power gain equation (4.10)-(4.12). They are transducer power gain (𝐺_𝑇), operation power gain (𝐺_𝑃), and available power gain (𝐺_𝐴), respectively. Definition of 𝐺_𝑇 is the value of power delivered to the load divided the value of power available from the source. Definition of 𝐺_𝑃 is the value of power delivered to the load divided the value of power input to the network. Definition of 𝐺_𝐴 is the value of power available from the network divided the value of power available from the source.

They also are displayed in Fig. 4.4.

𝐺_𝑇 = ^𝑃𝐿

33

Γ_𝑜𝑢𝑡 = 𝑆₂₂+^{𝑆12𝑆21Γ𝐿}

1−𝑆11Γ𝐿 (4.14)

Fig. 4.4. Two-port network actual power diagram.

4.3.3 Stability

In the design of the amplifier, stability is a very important parameter need to take into consideration. If the amplifier is in an unstable state, characteristic of the circuit will be substantially reduced. Equation (4.15) and (4.16) are the amplifier circuit unconditionally stable definition, if the circuit is fit to these two equation, the amplifier is unconditionally stable.

k =^{1−|𝑆11|2−|𝑆22|2+|∆|2}

2|𝑆₁₂𝑆₂₁| > 1 (4.15)

|∆| = |𝑆₁₁𝑆₂₂− 𝑆₁₂𝑆₂₁| < 1 (4.16)

4.4 Design of K/Ka Band Low-Noise Amplifier

Traditionally, low-noise amplifier architecture most commonly used as a common-source configuration or cascode configuration. Compare the performance of these two configuration can found some features between them.

34

DC supply for cascode configuration is twice times of common-source configuration, so cascode configuration maximum available gain will much higher than the common-source configuration, but the power consumption of the cascode configuration will double, and the minimum noise figure will be more than common-source configuration, too.

Due to hoping to reach the application of low-voltage and low noise figure in this design, so choose the common-source configuration for low-noise amplifier design. On the other hand, to provide the low-noise amplifier has enough gain at K/Ka band to suppress the noise from the subsequent stage. We choice the two-stage cascade common-source amplifier for this study.

RFin

VG VG

VDD

VDD2

RFout

Fig. 4.5. K/Ka-band low noise amplifier architecture.

Fig. 4.5 is the low-noise amplifier architecture of this study. First input stage using a series inductor and a source degeneration inductor to achieve the input noise match and still have a good gain to suppress the noise figure from

Fig. 4.5 is the low-noise amplifier architecture of this study. First input stage using a series inductor and a source degeneration inductor to achieve the input noise match and still have a good gain to suppress the noise figure from

在文檔中 應用於K/Ka頻段積體電路之靜電放電防護設計 (頁 22-0)