Conclusion

The proposed ESD protection device of LASCR has been developed in nanoscale CMOS process for K/Ka-band applications. Verified in silicon chip, LASCR devices with 30um (LASCR_W30_3D and LASCR_W30_5D) and 60um (LASCR_W60_3D and LASCR_W60_5D) width can pass 4kV and 7.5kV HBM ESD tests, respectively, and they have the loss lower than 3dB in K/Ka-band. In fact, LASCR devices exhibit good high-frequency performances between 0~40 GHz, so they can also be used for wideband or high-speed applications. Measurement results verify the high-frequency performances and confirm the ESD protection ability of LASCR. Therefore, the proposed LASCR can be a good solution for ESD protection.

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Chapter 4

K/Ka-Band Low Nosie Amplifier

4.1 Introduction

As technology progresses, more important applications are use in the K/Ka band, such as wireless network, short-range automotive radars, and local multipoint distribution service. Considering the sensitivity of the system in RF applications, the low noise receiver is necessary. In the receiver system, low noise amplifier (LNA) is a very important and critical circuit as shown in Fig.

4.1.

Fig. 4.1. Receiver system architecture.

The function of low noise amplifier is to provide enough gain to amplify the weak RF signal received by antenna and suppress the influence of noise generated by subsequent stage at the same time. It can also improve signal to

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noise ratio (SNR) and let signal without distortion. Thereby allowing received signals can be correctly demodulation out by the subsequent circuit.

Therefore, the needed of accurate transistor small signal model and noise model when design the low noise amplifier is necessary. Because the noise from transistor is the main noise of the overall circuit and may interfere RF signal, then signal will distortion and couldn’t be demodulated by the subsequent stage circuit. Therefore, an accurate transistor small signal model and noise model is very important.

4.2 Source of Transistor Noise

Transistor noise generated by interpreting the results as Brownian motion caused. However, transistors is susceptible noise in the small signal operating conditions. Generally, transistor noise can be divided into thermal noise, distributed gate resistance noise, and flicker noise.

4.2.1 Channel thermal noise

Channel thermal noise is due to the electron perturbations within the transistor channel. Channel electrons excited by the heat and random motion, so that transistor produces random changes in voltage and current. These voltage and current changes produce thermal noise, and then define the effective noise power with equation (4.1)

𝑃_𝑎𝑣 = 𝑘𝑇∆𝑓 (4.1) where k is Boltzmann constant, which is 1.38 × 10⁻²³(J/K). T is the absolute temperature, ∆𝑓 is the noise bandwidth with units of Hz. By equation (4.1) knows that, when the conductor temperature increase, effective noise power will

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increase.

Analysis the influence of thermal noise in the circuit would equivalent the thermal noise to a parallel noise current source, and must assume the transistor as ideal state without any noise. Schematic diagram is show in Fig. 4.2. The noise power equation is (4.2)

𝐼_𝑛²(f) = 4kTγ𝑔_𝑚 (4.2) where k is Boltzmann constant, which is 1.38 × 10⁻²³(J/K). T is the absolute temperature. 𝑔_𝑚 is the drain transduction value when bias is zero. Value of γ would greater than 1 in the short channel, and would be 2 3⁄ in the long channel.

Fig. 4.2. Transistor channel thermal noise model.

4.2.2 Distributed Gate Resistance Noise

During the CMOS process, the poly layer is used on the gate. Therefore, the gate will produce polysilicon resistors. Equation and model is show in equation (4.3) and Fig. 4.3, respectively.

𝑅_𝑔 = 𝑅_ℎ ^𝑊

3𝑛²𝐿 (4.3) In equation (4.3), 𝑅_ℎ is the polysilicon resistors, n is the number of transistors

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finger, W and L are the transistors width and length, respectively. The equation of output noise provided by the distributed gate resistance is

𝑉_{𝑛,𝑜𝑢𝑡}² = 4𝑘𝑇^𝑅𝑔

3 (𝑔_𝑚𝑟_𝑜)² (4.4) From equation (4.3) and (4.4), if want to achieve low noise circuit design, use larger number of fingers and lower channel width in the same transistor size can make gate resistance smaller. Thereby reducing the noise generated by the resistor.

Fig. 4.3. CMOS transistors gate resistance model.

4.2.3 Flicker Noise

Flicker noise is the major noise when CMOS transistors operating at low frequencies. The flicker noise mostly occurs between the gate oxide layer and the silicon substrate surface. Due to silicon crystal and the surface at this interface will produce a discontinuous bond, when the current passes will randomly be captured and released, causing transistor drain current unstable and produce flicker noise, but when the frequency greater than a specific frequency,

31 Where K is the process parameters.

4.3 Parameters of Low-Noise Amplifier

4.3.1 Noise Figure

To know the amplifier noise figure (NF), we must first understand the noise factor (F). The definition of noise factor is the input signal-noise ratio dividing the output signal-noise ratio, and can calculated by equation (4.6).

F = ^{𝑆𝑁𝑅𝑖𝑛}

For example, in a two-stage amplifier, equation (4.7) show that two-stage amplifiers noise factor.

𝑁_𝑖𝑛𝐺₂ is the second-stage amplifiers noise factor. So we can use the results of the two-stage amplifier to infer the n-stage amplifier noise factor should be the following equation (4.8).

F = 𝐹₁+^𝐹2−1

𝐺₁ +^𝐹3−1

𝐺₁𝐺₂+ ⋯ + ^𝐹𝑛−1

𝐺₁𝐺₂…𝐺_𝑛−1 (4.8) By observation of equation (4.8), knows that multiple cascading amplifier noise

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factor is mainly determined by the first-stage amplifier. Therefore, the first-stage amplifier matching network and architecture are the most important things during the design of low-noise amplifier. Other stage of amplifier is primarily responsible for increasing the gain. Finally, we can define the noise figure of the following equation (4.9). F in this equation is noise factor.

NF = 10 log 𝐹 (4.9)

4.3.2 Gain

In the low-noise amplifier design, gain is an important parameter to consider.

If the gain of low-noise amplifier not enough, it could be unable to suppress the noise of subsequent circuit. It also cause the large noise figure and let signal distortion. When design the RF amplifier, there have three kinds of power gain equation (4.10)-(4.12). They are transducer power gain (𝐺_𝑇), operation power gain (𝐺_𝑃), and available power gain (𝐺_𝐴), respectively. Definition of 𝐺_𝑇 is the value of power delivered to the load divided the value of power available from the source. Definition of 𝐺_𝑃 is the value of power delivered to the load divided the value of power input to the network. Definition of 𝐺_𝐴 is the value of power available from the network divided the value of power available from the source.

They also are displayed in Fig. 4.4.

𝐺_𝑇 = ^𝑃𝐿

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Γ_𝑜𝑢𝑡 = 𝑆₂₂+^{𝑆12𝑆21Γ𝐿}

1−𝑆11Γ𝐿 (4.14)

Fig. 4.4. Two-port network actual power diagram.

4.3.3 Stability

In the design of the amplifier, stability is a very important parameter need to take into consideration. If the amplifier is in an unstable state, characteristic of the circuit will be substantially reduced. Equation (4.15) and (4.16) are the amplifier circuit unconditionally stable definition, if the circuit is fit to these two equation, the amplifier is unconditionally stable.

k =^{1−|𝑆11|2−|𝑆22|2+|∆|2}

2|𝑆₁₂𝑆₂₁| > 1 (4.15)

|∆| = |𝑆₁₁𝑆₂₂− 𝑆₁₂𝑆₂₁| < 1 (4.16)

4.4 Design of K/Ka Band Low-Noise Amplifier

Traditionally, low-noise amplifier architecture most commonly used as a common-source configuration or cascode configuration. Compare the performance of these two configuration can found some features between them.

34

DC supply for cascode configuration is twice times of common-source configuration, so cascode configuration maximum available gain will much higher than the common-source configuration, but the power consumption of the cascode configuration will double, and the minimum noise figure will be more than common-source configuration, too.

Due to hoping to reach the application of low-voltage and low noise figure in this design, so choose the common-source configuration for low-noise amplifier design. On the other hand, to provide the low-noise amplifier has enough gain at K/Ka band to suppress the noise from the subsequent stage. We choice the two-stage cascade common-source amplifier for this study.

RFin

VG VG

VDD

VDD2

RFout

Fig. 4.5. K/Ka-band low noise amplifier architecture.

Fig. 4.5 is the low-noise amplifier architecture of this study. First input stage using a series inductor and a source degeneration inductor to achieve the input noise match and still have a good gain to suppress the noise figure from subsequent stage. Between the first stage and second stage, T-model is use to complete the stage-to-stage conjugate match. The second output stage using

35

series capacitance and inductor to complete output conjugate match.

4.4.1 Common-source transistor bias and size analysis

Select the bias of transistor is the first step of amplifier design. In CMOS 0.18μm process, the maximum of common-source configuration 𝑉_𝐷𝐷 is 1.8V, and the gate bias (𝑉_𝐺) is one of the main selection during design. 𝑉_𝐺 choice will affect the value of transduction (𝑔_𝑚), the drain current (𝐼_𝑑), and the noise figure (NF). So the greater 𝑉_𝐺 will cause the greater current and the greater power consumption. According to system requirements, we need to make trade-offs between these three parameters.

Fig. 4.6 is the transistor DC-IV curve. Through the figure we can observe the ID become lower when 𝑉_𝐺𝑆 increase. Then Fig. 4.7 show that the transistor will enter the saturation region when 𝑉_𝐺𝑆 is more than 0.8V, and 𝐼_𝑑 will rapidly increase when 𝑉_𝐺𝑆 is more than 0.4V. In order to prevent excessive power consumption, the smaller 𝐼_𝑑 will be choose in this study. Fig. 4.8 show that there is a minimum of noise figure when 𝑉_𝐺𝑆 is near 0.7V. Based on the above considerations, the final choice of the LNA transistor 𝑉_𝐺𝑆 is 0.7V.

Fig. 4.6. Transistor dc I-V curve.

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Fig. 4.7. Transistor 𝑔_𝑚 and 𝐼_𝑑 curve.

Fig. 4.8. Transistor minimum noise figure curve.

37

The second step is selected transistor size. Transistor has three optional parameters, they are channel length, channel width, and number of finger, respectively. However, the channel length of transistors are usually choice of the smallest value, which can reach a maximum value of transistors transduction. In TSMC 0.18μm CMOS process, the minimum value of channel length is 0.18μm, so the channel length is choose as 0.18μm.

The Maximum of gain (MAG) and minimum of noise figure (𝑁𝐹_𝑚𝑖𝑛) under different channel length is show in Fig. 4.9 and Fig. 4.10, respectively. Fig. 4.9 show that the available maximum gain (MAG) increase with the transistor width, but when the channel width is greater than 5μm, the increase rate of gain become smaller. Therefore, the channel length will design near 5μm. Fig. 4.10 show that when number of finger become larger, the minimum noise figure and power consumption will increases. After consideration of the above conditions, select the channel width of 5μm, the number of finger with 10 as common-source transistor size.

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Fig. 4.9. MAG in different channel width and number of finger.

Fig. 4.10. 𝑁𝐹_𝑚𝑖𝑛 in different channel width and number of finger.

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4.4.2 Matching network design

After deciding the amplifier overall structure, followed by low noise amplifier matching network design. Matching network using inductors and capacitors to achieve.

Fig. 4.11 is the two-stage cascade low-noise amplifier matching network.

Input matching is use the noise match, that noise figure can be minimized. Both of output matching and stage-to-stage matching are use the conjugate match, which can provide the greatest gain. In the low-noise amplifier matching network design, input noise matching network is the most important part of design. If design is not well, it would let the signals which transfer to the post-stage circuit have excessive noise and make signal distortion. Therefore, we prefer to design the input matching network, then design stage-to-stage matching and output matching, finally tuning the circuit.

Noise

Fig. 4.11. Two-stage cascade low-noise amplifier matching network design.

1. Input noise matching

To achieve noise matching, the first step is to find the noise circle and

40

𝑁𝐹_𝑚𝑖𝑛 can be found in the noise circle. Then design the input matching network let the input impedance of 50Ω matched to 𝑁𝐹_𝑚𝑖𝑛 point. First stage noise matching design circuit is show in Fig. 4.12. It is using source degeneration inductance and series a gate inductance to achieve input noise match.

Fig. 4.13 is the simulation of input noise circle. The lowest noise can available at 𝑁𝐹_𝑚𝑖𝑛 impedance point. The step size of noise circle is 0.25dB every lap. In order to let the amplifier get the lowest noise, input port of 50Ω need to reach 𝑁𝐹_𝑚𝑖𝑛 impedance point through the matching network design. The matching network locus plot can be seen from Fig. 4.13.

First, source degeneration inductor would let input impedance increase, make the input impedance conjugate point closer to the 𝑁𝐹_𝑚𝑖𝑛 point, then series a gate inductor. Therefore, that could be able to reach a conjugate match and noise match at the same time, then send the signal to the next stage with low-noise and high-gain.

RFin

Fig. 4.12. First stage noise matching design circuit.

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Fig. 4.13. Input noise match locus plot.

2. First stage and second stage matching

After design the input matching circuit, the first stage and second stage matching would use conjugate match. First, find the first-stage common-source amplifier output impedance point (𝑆₂₂), and then find the second stage common-source amplifier input impedance point (𝑆₁₁). The goal is matching the first-stage common-source amplifier output impedance point (𝑆₂₂) to the second stage common-source amplifier input impedance conjugate point (𝑆₁₁∗). In this study, using a T-model design in Fig. 4.14, which contains two series inductor and a shunt inductor. Fig. 4.15 is

42

matching locus smith chart. Then we can complete the stage-to-stage conjugate match.

Ls

L1

L2

L3

S22 S11* S11

Fig. 4.14. Stage-to-stage matching circuit.

Fig. 4.15. Stage-to-stage matching locus plot.

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3. Output conjugate matching

Final is the output matching design. Output stage will use conjugate match to reach the maximum gain. Fig. 4.16 show that to find the second stage output impedance point (𝑆₂₂), and matching the 50Ω output impedance to the second stage output impedance point (𝑆₂₂), then finished the output matching.

L

C RFout

S22 50Ω

Fig. 4.16. Output matching circuit.

44

Fig. 4.17. K/Ka band low noise amplifier overall architecture figure.

The low-noise amplifier in this study is using 0.18um CMOS process, the overall circuit architecture shown in Fig. 4.17. Simulation of small-signal S-parameters and noise figure is using Agilent ADS (Advanced Design System).

All passive components in the architecture such as transmission lines, inductors, and capacitors are using EM electromagnetic simulation software (HFSS) to complete full-wave electromagnetic simulation, and analysis all simulated results by ADS. The parameters of the components is show in Table 4.1.

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Table 4.1

K/Ka-band low-noise amplifier components parameters

Device Value Device Value

M1 5um / 0.18um Input-stage Lg 529.8 pH

M2 5um / 0.18um Input-stage Ls 220 pH

M3 5um / 0.18um Inter-stage L1 291.2 pH Output-stage Ld 755.5 pH Inter-stage L2 329.0 pH Output-stage Cd 27.6 fF Inter-stage L3 238.3 pH

Fig. 4.18 is the S-parameter simulation result. Small-signal gain (S21) at 24GHz is about 18dB. Input return loss (S11) is greater than 15dB. Output return loss (S22) is greater than 25dB. Fig. 4.19 is the simulation of noise figure, and noise figure is about 3.5dB at 24GHz. Fig. 4.20 is the layout diagram of the chip.

Fig. 4.18. Low-noise amplifier S-parameters simulation result.

46

Fig. 4.19. Low-noise amplifier noise figure simulation result.

Fig. 4.20. Layout top view of low-noise amplifier.

47

4.6 Measurement results

Fig. 4.21 is chip micrograph of K/Ka-band low-noise amplifier. Layout area is 0.75mm × 0.60mm. Chip measurement methods using on wafer measurement mode.

The high-frequency signal input and output terminals using GSG RF probe measurements. DC supply voltage using a power supply, S-parameter using a network analyzer to measure. Noise figure using noise analyzer measurements.

Fig. 4.22 is the low-noise amplifier S-parameter measurement value, the small signal gain at 21GHz is maximum about 9.46dB. Fig. 4.23 is the low-noise amplifier noise figure, value of noise figure between 16.5-26.5 GHz is less than 10dB, and has minimum about 7dB at 21GHz.

Fig. 4.21. Chip micrograph of low-noise amplifier.

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Fig. 4.22. Gain and return loss of the low-noise amplifier.

Fig. 4.23. Noise figure of low-noise amplifier.

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4.7 ESD protection device equipped with LNA

To test the ESD protection ability of the ESD protection device, we also fabricated other three LNA equipped with different kinds of ESD protection device. Fig. 4.24-4.29 are LNA layout diagram and chip micrograph which equipped LASCR, dual diode, and DTSCR, respectively. Fig. 4.30 show that gain of the LNA. Through the figure can be seen LNA without equipped ESD protection device can’t bear 0.5kV ESD HBM test.

At 21GHz, dual diodes_LNA has maximum gain about 11.27dB, DTSCR_LNA has maximum gain about 12.09dB, and LASCR_LNA has maximum gain about 11.61dB, respectively.

Dual diodes_LNA equipped with a N+/PW diode (DN30) and a P+/NW (DP30) diode. Both of the diode width is 30μm. Fig. 4.31-4.33 show that comparison of gain, S₁₁, S₂₂ before and after HBM test, respectively. Dual diodes_LNA has gain of 11.07dB after 1.5kV HBM test and 2.90dB after 2kV HBM test at 21GHz, respectively.

DTSCR_LNA equipped with a SCR and series three diodes. Width of the SCR and diodes are 30um and 15um, respectively. Fig. 4.34-4.36 show that comparison of gain, S₁₁, S₂₂ before and after HBM test, respectively.

DTSCR_LNA has gain of 12.13dB after 2kV HBM test and 0.05dB after 3kV HBM test at 21GHz, respectively.

LASCR_LNA equipped with a SCR, an inductance, and series three diodes.

Width of the SCR and diodes are 30um and 15um, respectively. The value of inductance is 460pH. Fig. 4.37-4.39 show that comparison of gain, S₁₁, S₂₂ before and after HBM test, respectively. LASCR_LNA has gain of 11.3dB after 4kV HBM test and 9.22dB after 5kV HBM test at 21GHz, respectively.

50

Fig. 4.24. Layout top view of LNA equipped dual diode.

Fig. 4.25. Chip micrograph LNA with dual diode.

51

Fig. 4.26. Low-noise amplifier equipped DTSCR layout top view.

Fig. 4.27. Low-noise amplifier with DTSCR chip micrograph.

52

Fig. 4.28. Low-noise amplifier equipped LASCR layout top view.

Fig. 4.29. Low-noise amplifier with LASCR chip micrograph.

53

Fig. 4.30. Gain of the LNA before and after HBM ESD test.

Fig. 4.31. Gain of the dual diodes_LNA before and after HBM ESD test.

54

Fig. 4.32. S₁₁ of the dual diodes_LNA before and after HBM ESD test.

Fig. 4.33. S₂₂ of the dual diodes_LNA before and after HBM ESD test.

55

Fig. 4.34. Gain of the DTSCR_LNA before and after HBM ESD test.

Fig. 4.35. S₁₁ of the DTSCR_LNA before and after HBM ESD test.

56

Fig. 4.36. S₂₂ of the DTSCR_LNA before and after HBM ESD test.

Fig. 4.37. Gain of the LASCR_LNA before and after HBM ESD test.

57

Fig. 4.38. S₁₁ of the LASCR_LNA before and after HBM ESD test.

Fig. 4.39. S₂₂ of the LASCR_LNA before and after HBM ESD test.

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4.8 Discussion

In order to investigate the relationship between the components, frequency, and gain, we re-simulate the LNA with precise parameter to meet the measurement result. Fig. 4.40 shows the low noise amplifier architecture with parasitic capacitance and resistance. The measurement results of this study didn’t fit the simulation results might be caused by components parasitic effect. To find out the parasitic component values, we do the simulation of LNA again.

Simulation of S-parameters are shown in Fig. 4.41. Table 4.2 also shows the components parameters of parasitic capacitance and resistance. The main reason of the operating frequency change is caused by the output-stage parasitic capacitance (C_Ld). Small signal gain is mainly affected by inter-stage capacitance resistances (R2 and R3) and output-stage capacitance resistances (R4 and R5).

RFin

Fig. 4.40. K/Ka-band low noise amplifier architecture with parasitic capacitance and resistance.

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Fig. 4.41. Simulation with precise parameter and measurement result of LNA.

Table 4.2

Low-noise amplifier components parameters of parasitic capacitance and resistance

Device Value Device Value

𝐂_𝐋𝐠 20 fF R1 15 Ω

𝐂_𝐋𝐬 60 fF R2 15 Ω

𝐂_𝐋𝟏 15 fF R3 100 Ω

𝐂_𝐋𝟐 50 fF R4 7.5 Ω

𝐂_𝐋𝟑 20 fF R5 0.5 Ω

𝐂_𝐋𝐝 17 fF

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4.9 Conclusion

This study is using 0.18μm CMOS process to complete the design of K/Ka band low-noise amplifier. Overall circuit architecture is using a two-stage

This study is using 0.18μm CMOS process to complete the design of K/Ka band low-noise amplifier. Overall circuit architecture is using a two-stage

在文檔中 應用於K/Ka頻段積體電路之靜電放電防護設計 (頁 38-0)