Discussion

In order to investigate the relationship between the components, frequency, and gain, we re-simulate the LNA with precise parameter to meet the measurement result. Fig. 4.40 shows the low noise amplifier architecture with parasitic capacitance and resistance. The measurement results of this study didn’t fit the simulation results might be caused by components parasitic effect. To find out the parasitic component values, we do the simulation of LNA again.

Simulation of S-parameters are shown in Fig. 4.41. Table 4.2 also shows the components parameters of parasitic capacitance and resistance. The main reason of the operating frequency change is caused by the output-stage parasitic capacitance (C_Ld). Small signal gain is mainly affected by inter-stage capacitance resistances (R2 and R3) and output-stage capacitance resistances (R4 and R5).

RFin

Fig. 4.40. K/Ka-band low noise amplifier architecture with parasitic capacitance and resistance.

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Fig. 4.41. Simulation with precise parameter and measurement result of LNA.

Table 4.2

Low-noise amplifier components parameters of parasitic capacitance and resistance

Device Value Device Value

𝐂_𝐋𝐠 20 fF R1 15 Ω

𝐂_𝐋𝐬 60 fF R2 15 Ω

𝐂_𝐋𝟏 15 fF R3 100 Ω

𝐂_𝐋𝟐 50 fF R4 7.5 Ω

𝐂_𝐋𝟑 20 fF R5 0.5 Ω

𝐂_𝐋𝐝 17 fF

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4.9 Conclusion

This study is using 0.18μm CMOS process to complete the design of K/Ka band low-noise amplifier. Overall circuit architecture is using a two-stage common-source cascade design to achieve the low–voltage and low-noise demand. Input stage uses the source degeneration inductance and gate inductance to achieve conjugate matching and noise matching at the same time. Stage-to-stage matching using the T-model inductance to achieved conjugate matching.

Output matching uses series inductors and capacitors to achieve conjugate matching. This low-noise amplifier has a maximum gain 9.46dB at 21GHz, the minimum noise figure of 7dB, layout area is 0.75mm × 0.60mm. After adding the ESD protection device of dual diode, low-noise amplifier can bear 1.5kV HBM test, and maximum gain is 11.07dB at 21GHz. DTSCR_LNA can bear 2kV HBM test, and maximum gain is 12.13dB at 21GHz. LASCR_LAN can bear 4kV HBM test, and maximum gain is 11.3dB at 21GHz. Table. 4.3 summarizes out the HBM ESD robustness of each LNA.

Table. 4.3

HBM ESD robustness of LNA

Cell Name HBM ESD Robustness

LNA 0kV

Dual diode LNA 1.5kV

DTSCR_LNA 2kV

LASCR_LNA 4kV

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Chapter 5

Conclusions and Future Works

This chapter summarizes the main results and contributions of this study.

Future works of the inductor-assisted silicon-controlled rectifier for ESD protection design in CMOS process are also provided in the chapter.

5.1 Main Contributions of This Study

In this study, a kind of ESD protection device has been developed in nanoscale CMOS technology for RF ESD protection design. Each of the test devices and low-noise amplifier has been successfully verified in the test chip.

In Chapter 2, some ESD protection devices such as diode and SCR has been introduces. This chapter also show that four discharge path when circuits are stress by ESD.

In Chapter 3, LASCR’s architecture and design process is described in detail. Verified in silicon chip, LASCR devices with 30um (LASCR_W30_3D and LASCR_W30_5D) and 60um (LASCR_W60_3D and LASCR_W60_5D) width can pass 4kV and 7.5kV HBM ESD tests, respectively, and they have the loss lower than 3dB in K/Ka-band. All devices in this chapter are fabricated by 0.18um CMOS process.

In Chapter 4, design of low-noise amplifier has been described in this chapter. It also contains some important parameters and design considerations of LNA. This chapter also introduced the low-noise amplifier design procedure, few kinds of ESD protection devices are co-design with the LNA. All low-noise

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amplifier in this chapter is fabricated in 0.18um CMOS process, and the small-signal gain of the stand-alone LNA circuit has maximum 9.46dB at 21GHz and minimum noise figure at 21GHz for 7dB. After Inductor-Assisted Silicon-Controlled Rectifier (LASCR) has been equipped, the circuit can bear 4kV HBM test. The small-signal gain at 21GHz has maximum of 11.3dB.

The circuit ESD protection function can be achieved without degrade the low-noise amplifier performance, and also can reach 4kV HBM test.

5.2 Future Works

With the continuously scaling CMOS technology, the gate oxide becomes much thinner. ESD become one of the most important reliability issues during mass production, must be taken into consideration. Therefore, all integrated circuits used in the wireless communication products need to be equipped with ESD protection designs. However, ESD protections cause radio-frequency (RF) performance degradation with several undesired effects, such as degrade the small-signal gain of the circuit or takes up too much layout area. Inductor-Assisted Silicon-Controlled Rectifier (LASCR) of this study will be able to overcome these drawbacks. LASCR devices exhibit good high-frequency performance between 0~35GHz, so they can be used for wideband or high-speed applications without degrading the performance of circuit.

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自 傳

研究生張榮堃，生於台中市，家中父母關係良好，一家和樂，

雖然國高中階段的求學路程並非順利，所幸最後進入國立台灣師範 大學應用電子科技學系就讀。然而大學期間還在摸索未來的定位，

以致於成績並非理想，在大三的專題課程選擇了晶片設計的方向，

意外的發現對此頗感興趣。研究所階段幸運的考取國立台灣師範大 學電機工程學系，繼續選擇晶片設計這方向深造，雖然學習能力並 不是頂尖，但也很願意去了解所有相關知識，也喜歡和同學們互相 交換想法和意見。感謝老師的提拔，未來將會繼續深造，願能用己 微薄之力為人類社會創造更好的未來。

69

學 術 成 就

[1] C.-Y. Lin and R.-K. Chang, “On-chip ESD protection designs with SCR-based devices in RF integrated circuits,” IEEE Conf. Consumer Electronics-Taiwan, pp.

15-16, May 2014.

[2] C.-Y. Lin, P.-H. Chang, and R.-K. Chang, “Improving ESD Robustness of PMOS Device with Embedded SCR in 28-nm High-K/Metal Gate CMOS Process,” IEEE Trans. Electron Devices, vol. 62, no. 4, pp. 1349-1352, Apr. 2015.

[3] C.-Y. Lin and R.-K. Chang, “Design of ESD protection device for K/Ka-band applications in nanoscale CMOS process,” accepted by IEEE Trans. Electron Devices.