應用於K/Ka頻段積體電路之靜電放電防護設計

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(1)國立臺灣師範大學電機工程學系碩士論文指導教授：林群祐博士. 應用於 K/Ka 頻段積體電路之靜電放電防護設計 On-Chip ESD Protection Design for K/Ka-Band Applications. 研究生：張榮堃撰中華民國 104 年 7 月.

(2) 應用於 K/Ka 頻段積體電路之靜電放電防護設計. 學生：張榮堃. 指導教授：林群祐博士. 國立臺灣師範大學電機工程學系碩士班. 摘. 要. 本論文設計之電感嵌入矽控整流器的靜電放電防護元件可在共振的頻率之下使電路的小訊號增益損耗降低，只要選擇正確的電感感值便可以達成目標。此外，矽控整流器能在最小的面積下提供最高的靜電放電耐受度，達成較佳的電路靜電放電防護能力。為了驗證靜電放電防護元件在實際電路上的效能，本論文同時設計了一個低雜訊放大器電路，並且裝備本論文所提出之電感嵌入矽控整流器的靜電放電防護元件，在實驗結果比較中，本論文所提出的設計並不會降低電路的小訊號增益。本論文中的所有電路皆使用 0.18um CMOS 製程實現。透過實驗分析比較結果，本論文所提出的設計確實能夠達成良好的靜電放電防護能力，使電路能夠承受 4kV 的人體放電模式之靜電放電測試，證明電路能夠有效地被該元件保護。. 關鍵字：靜電放電耐受度、電感、矽控整流器. I.

(3) On-Chip ESD Protection Design for K/Ka-Band Applications. Student：Chang, Rong-Kun. Advisor：Dr. Lin, Chun-Yu. Department of Electrical Engineering National Taiwan Normal University. All ABSTRACT. An inductor-assisted silicon-controlled rectifier (LASCR) electrostatic discharge (ESD) protection device was designed in this study. The signal loss under the resonant frequency can be reduced by selecting the appropriate inductor in the LASCR. Furthermore, silicon-controlled rectifier has good ESD robustness and small layout area, and let circuit achieve good ESD protection ability. In order to verify the protection ability of ESD protection device on the radio frequency (RF) circuit, a low-noise amplifier (LNA) circuit has been fabricated in this study, which equipped with LASCR ESD protection device. In the experimental results, the proposed design did not degrade the small-signal gain of the LNA circuit. All devices and circuits in this study are fabricated in 0.18um CMOS process. Through analysis and comparison of the experimental results, the proposed design can achieve a good ESD protection ability. In the experimental II.

(4) results, the proposed design can bear 4kV HBM test without degrade the smallsignal gain of the circuit. This proves that the circuit can be effectively protected by the LASCR.. Keywords : electrostatic discharge, inductor, silicon-controlled rectifier.. III.

(5) 致謝碩士班短短兩年的生涯隨著碩士論文的完成而有了完美的句點。首先，感謝我的指導教授林群祐博士，在兩年的時間內帶領我進入靜電放電防護可靠度的研究領域，並且非常有耐心地指導我，讓我有能力來循序漸進的解決問題，同時了解研究本身的內涵。也很感謝老師給了一個機會讓我能參加台積電的計畫，提早體會業界的一些生態作息，並且能夠實際的操作一些量測儀器，對我來說實在受益良多。非常開心能在碩士班兩年的期間內用自己的研究產出期刊論文，同時也考上了國立交通大學電子研究所的博士班，在這些方面老師給予的幫助都非常的多，讓我充實的度過了碩士班的生活，並且朝著人生的下個階段邁進。. 其次，感謝國立交通大學電子工程學系的柯明道教授以及國立台灣師範大學電機工程學系的蔡政翰教授百忙之中抽空擔任我的口試委員，許多意見讓我受益良多，也使得論文更加完善；同時也要感謝國立台灣師範大學電機工程學系的蘇崇彥主任幫我寫了博士班的推薦信，身為系主任的您真的辛苦了。. 再來，這裡要特別感謝瑞安學長，在你趕碩論的期間一直都很願意幫助我解決研究上的問題，不然在新成立的實驗室中真的不知道該如何去面對研究的問題，並且讓我能夠順利地趕在下線時間前完成電路；感謝奈米積體電路與系統實驗室的同學和學弟們，陪伴我度過碩士班的生涯，尤其是偉豪，帶給我許多歡笑，希望未來你也能順利完成學業；感謝 VIP 實驗室的哲揚、鈺棠、英浩、立安、乃魁，有你們一起吃飯、唱歌、打白貓的日子真的很歡樂，也要特別感謝俊霖在後面的一年陪著我，同時幫我解決研究外的許多事情，未來還要繼續麻煩你了，而政鈞很高興我們到了同一 IV.

(6) 個地方，未來一起在交大努力吧；感謝通訊實驗室的鈺錞學長、宜蒲、元杰，有你們就有歡笑，雖然大家未來的路都不同，但願你們都能順利；感謝 RF 實驗室的望龍、家凱、胤廷，類似的研究領域讓我能夠請教你們許多問題，順利克服許多難關；感謝系辦的琇文、嘉安、婷節，在行政方面提供了許多意見以及幫助；還有許許多多幫助過我的人，在此便不一一列舉，但是由衷的感謝你們，因為有你們才能讓我的碩士班生涯如此完整。. 最後，我要感謝親愛的父親張德垣先生、母親曾月珍女士、以及弟弟張榮邗先生，謝謝你們一路走來一直無悔的陪伴著我，給予我許多支持與鼓勵，讓我能夠專心的完成碩士班學位；同時也要感謝住在新竹的張惠娟姑姑一家人和曾月珠阿姨一家人，讓我在新竹實習的時候也能感受到家的溫暖。再次的感謝所有人，沒有你們的幫助以及陪伴，便不會有今日的榮堃，願所有人都能身體健康、事事順心，希望在未來的日子裡還能繼續維繫著你我之間的緣分，讓這份感動繼續延續下去。. 榮堃謹誌於中華民國一零四年七月. V.

(7) 目. 錄. 中文摘要 .............................................................................................................. I 英文摘要 ............................................................................................................. II 致謝 ................................................................................................................... IV 目錄 ................................................................................................................... VI 表目錄 .............................................................................................................VIII 圖目錄 ............................................................................................................... IX Chapter 1. Introduction ................................................................................... 1. 1.1. Motivation ............................................................................................ 1. 1.2. Organization of This Dissertation ........................................................ 2. Chapter 2. ESD Protection Device for RF Applications ................................ 4. 2.1. Introduction .......................................................................................... 4. 2.2. Whole-Chip ESD Protection Design .................................................... 6. 2.3 CMOS ESD Protection Device for RF Circuit .................................... 8 2.3.1 ESD Protection Design with Diodes............................................. 8 2.3.2. ESD Protection Design with SCR ................................................ 9. 2.3.3. ESD Protection Design with Inductor-Triggered SCR ............... 10. Chapter 3. Design of Inductor-Assisted Silicon-Controlled Rectifier ......... 11. 3.1. Introduction ........................................................................................ 11. 3.2. Design of LASCR .............................................................................. 15. 3.3. Comparing Device.............................................................................. 16. 3.4. Simulation Results ............................................................................. 17. 3.5. Experimental Results of Test Devices ............................................... 19. 3.5.1. High-Frequency Performances ................................................... 20. 3.5.2. ESD Robustness .......................................................................... 21. 3.5.3. Failure Analysis .......................................................................... 23. 3.5.4. Leakage ....................................................................................... 26. 3.6. Conclusion .......................................................................................... 26. VI.

(8) Chapter 4. K/Ka-Band Low Nosie Amplifier ............................................... 27. 4.1. Introduction ........................................................................................ 27. 4.2. Source of Transistor Noise ................................................................. 28. 4.2.1. Channel Thermal Noise .............................................................. 28. 4.2.2. Distributed Gate Resistance Noise ............................................. 29. 4.2.3. Flicker Noise ............................................................................... 30. 4.3. Parameters of Low-Noise Amplifier .................................................. 31. 4.3.1. Noise Figure ................................................................................ 31. 4.3.2. Gain ............................................................................................. 32. 4.3.3. Stability ....................................................................................... 33. 4.4. Design of K/Ka-Band Low-Noise Amplifier ..................................... 33. 4.4.1. Common-Source Transistor Bias and Size Analysis .................. 35. 4.4.2. Matching Network Design .......................................................... 39. 1.. Input noise matching ................................................................... 39. 2.. First stage and second stage matching ....................................... 41. 3.. Output conjugate matching ......................................................... 43. 4.5. Simulation Result ............................................................................... 44. 4.6. Measurement Results ......................................................................... 47. 4.7. ESD Protection Device Equipped with LNA ..................................... 49. 4.8. Discussion .......................................................................................... 58. 4.9. Conclusion .......................................................................................... 60. Chapter 5. Conclusions and Future Works ................................................... 61. 5.1. Main Contributions of This Study...................................................... 61. 5.2. Future Works ...................................................................................... 62. 參考文獻 ........................................................................................................... 63 自傳 ................................................................................................................... 68 學術成就 ........................................................................................................... 69. VII.

(9) 表目錄 Table 3.1. Design specification of the proposed LASCR ............................ 16. Table 3.2. Design specification of the proposed DTSCR ............................ 17. Table 3.3. Design specification of the proposed diode ................................ 17. Table 3.4. Design parameters and measurement results of test devices ...... 23. Table 4.1. K/Ka-band low-noise amplifier components parameters ........... 45. Table 4.2. Low-noise amplifier components parameters of parasitic capacitance and resistance ........................................................ 59. Table 4.3. HBM ESD robustness of LNA ................................................. 60. VIII.

(10) 圖目錄 Fig. 2.1. Whole-chip ESD protection for internal circuit............................ 5. Fig. 2.2. Conventional ESD protection with dual diodes............................ 5. Fig. 2.3. Equivalent circuits of (a) HBM and (b) MM ESD tests ............... 7. Fig. 2.4. ESD protection design with diodes............................................... 8. Fig. 2.5. ESD protection design with SCR ................................................. 9. Fig. 2.6. ESD protection design with inductor-triggered SCR ................. 10. Fig. 3.1. SCR cross-sectional view and ESD current paths. ..................... 11. Fig. 3.2. Equivalent circuit of LASCR, where SCR expressed by (a) BJT and (b) diodes. ............................................................................. 12. Fig. 3.3. Equivalent circuit of LASCR...................................................... 13. Fig. 3.4. Co-design of SCR and inductor’s ESD protection circuit. ......... 14. Fig. 3.5. 3D EM simulation of inductor.. .................................................. 15. Fig. 3.6. Equivalent circuit of DTSCR ...................................................... 16. Fig. 3.7. Simulated 𝑆11 and 𝑆21 of test devices. .................................... 19. Fig. 3.8. Simulated voltage/current waveforms of LASCR_W30_5D under (a) normal power-on condition and (b) ESD-like transition. ...... 19. Fig. 3.9. Chip micrograph of LASCR_W30_3D. ..................................... 20. Fig. 3.10. Measured 𝑆11 and 𝑆21 of test devices. .................................... 21. Fig. 3.11. TLP I-V curves of test devices. .................................................. 22. Fig. 3.12. The SEM pictures of the LASCR_W30_3D after +5kV HBM stresses. ....................................................................................... 24. Fig. 3.13. The SEM pictures of the LASCR_W30_5D after +4.5kV HBM stresses. ....................................................................................... 24. Fig. 3.14. The SEM pictures of the LASCR_W60_3D after +8kV HBM stresses. ....................................................................................... 25. Fig. 3.15. The SEM pictures of the LASCR_W60_5D after +8kV HBM stresses. ....................................................................................... 25. Fig. 4.1. Receiver system architecture. ..................................................... 27. IX.

(11) Fig. 4.2. Transistor channel thermal noise model ..................................... 29. Fig. 4.3. CMOS transistors gate resistance model .................................... 30. Fig. 4.4. Two-port network actual power diagram. .................................. 33. Fig. 4.5. K/Ka-band low noise amplifier architecture............................... 34. Fig. 4.6. Transistor dc I-V curve ............................................................... 35. Fig. 4.7. Transistor 𝑔𝑚 and 𝐼𝑑 curve. .................................................... 36. Fig. 4.8. Transistor minimum noise figure curve ...................................... 36. Fig. 4.9. MAG in different channel width and number of finger. ............. 38. Fig. 4.10. 𝑁𝐹𝑚𝑖𝑛 in different channel width and number of finger. .......... 38. Fig. 4.11. Two-stage cascade low-noise amplifier matching network design ..................................................................................................... 39. Fig. 4.12. First stage noise matching design circuit. ................................... 40. Fig. 4.13. Input noise match locus plot. ...................................................... 41. Fig. 4.14. Stage-to-stage matching circuit.. ................................................ 42. Fig. 4.15. Stage-to-stage matching locus plot.. ........................................... 42. Fig. 4.16. Output matching circuit.. ............................................................ 43. Fig. 4.17. K/Ka-band low noise amplifier overall architecture figure. ....... 44. Fig. 4.18. Low-noise amplifier S-parameters simulation result. ................. 45. Fig. 4.19. Low-noise amplifier noise figure simulation result. ................... 46. Fig. 4.20. Layout top view of low-noise amplifier.. ................................... 46. Fig. 4.21. Chip micrograph of low-noise amplifier. ................................... 47. Fig. 4.22. Gain and return loss of the low-noise amplifier. ........................ 48. Fig. 4.23. Noise figure of low-noise amplifier. ........................................... 48. Fig. 4.24. Layout top view of LNA equipped dual diode ........................... 50. Fig. 4.25. Chip micrograph of LNA equipped dual diode. ......................... 50. Fig. 4.26. Layout top view of LNA equipped DTSCR. .............................. 51. Fig. 4.27. Chip micrograph of LNA equipped DTSCR. ............................. 51. Fig. 4.28. Layout top view of LNA equipped LASCR. .............................. 52. Fig. 4.29. Chip micrograph of LNA equipped LASCR. ............................. 52 X.

(12) Fig. 4.30. Gain of the LNA before and after HBM ESD test...................... 53. Fig. 4.31. Gain of the dual diodes_LNA before and after HBM ESD test. 53. Fig. 4.32. S11 of the dual diodes_LNA before and after HBM ESD test... 54. Fig. 4.33. S22 of the dual diodes_LNA before and after HBM ESD test... 54. Fig. 4.34. Gain of the DTSCR_LNA before and after HBM ESD test....... 55. Fig. 4.35. S11 of the DTSCR_LNA before and after HBM ESD test. ....... 55. Fig. 4.36. S22 of the DTSCR_LNA before and after HBM ESD test. ....... 56. Fig. 4.37. Gain of the LASCR_LNA before and after HBM ESD test....... 56. Fig. 4.38. S11 of the LASCR_LNA before and after HBM ESD test. ....... 57. Fig. 4.39. S22 of the LASCR_LNA before and after HBM ESD test. ....... 57. Fig. 4.40. K/Ka-band low noise amplifier architecture with parasitic capacitance and resistance. ......................................................... 58. Fig. 4.41. Simulation with precise parameter and measurement result of LNA. ......................................................................................... 59. XI.

(13) Chapter 1 Introduction. 1.1 Motivation. In recent decade, developments of the wireless technologies are rapid and continued. People already have more than one wireless communication device such as smart phones or tablet PC. Therefore, high quality and low cost processes is necessary. That’s why RF ICs have been widely fabricated in CMOS processes. All CMOS ICs must meet the reliability specifications during mass production. Electrostatic discharge (ESD), which was one of the most important reliability issues and must been taken into consideration. All integrated circuits must be equipped with ESD protection device. As IC technology continuously scales down, thinner gate oxide cause ESD problem getting worse and must be carefully considered. Basic ESD protection circuit consists of a pair of diodes which beside I/O pads and a power-rail ESD clamp circuit. It can provide wholechip ESD protection. However, this design also has some drawback such as parasitic capacitance and would degrade the RF performance of the circuit. ESD protection devices are generally equipped with the circuits which might be stressed by ESD. Typically, low-noise amplifier (LNA) is the input interface of the RF ICs. Therefore, it might easily stressed by the ESD. Thus, the LNA is necessary to equipped ESD protection device. The matching network is very important for LNA. Although the general ESD protection devices such as diodes can provide good protection ability, but the large parasitic capacitances would cause the circuit degrade. Therefore, to 1.

(14) meet a good ESD protection ability without degrade the performance of the circuit is a great challenge. Silicon-controlled rectifier (SCR) is a useful ESD protection device due to some advantages such as high ESD robustness and small layout area. This makes SCR become a highly regarded device in the recent years, but it also has some drawback such as high turn-on voltage. Therefore, to reducing the turn-on voltage is the main study of SCR. Diode strings is a good device which can reduce the turn-on voltage, but it also has the large parasitic capacitance for the RF circuit. In this study, an inductor-assisted silicon-controlled rectifier (LASCR) has been successfully fabricated in 0.18um CMOS process. LASCR can effectively reduce the SCR trigger voltage without degrade the high-frequency performances of the LNA. In 0.18um CMOS process technology, LASCR devices have been successfully verified in silicon chip to achieve 4-7.5kV human-body-model (HBM) ESD robustness with 1-3dB loss in K/Ka-band (18-40GHz). According to the measurement results, the proposed ESD protection device also provides desired ESD robustness without degrading RF performance of LNA.. 1.2 Organization of This Dissertation. In Chapter 2, some ESD protection devices such as diode will be introduced. Four discharge path including positive-to-VSS (PS) mode, negative-to-VSS (NS) mode, positive-to-VDD (PD) mode, and negative-to-VDD (ND) mode of each circuit will be introduced in this chapter. In Chapter 3, inductor-assisted silicon-controlled rectifier (LASCR) ESD 2.

(15) protection devices will be introduced in detail. In this study, all testing devices are fabricated in 0.18um CMOS process. This chapter also includes simulation and measurement results of LASCR. In Chapter 4, K/Ka-band low-noise amplifier (LNA) has been fabricated in 0.18um CMOS process. In this chapter, some parameters of the LNA such as Sparameter and stability will be introduced. Next, the design procedure of LNA will be described, including the selection of transistor and design of the matching network. The LNA will also be equipped with the ESD protection device to measure the ESD robustness of the circuit. In Chapter 5, the conclusions and some suggestions for future investigation have been indicated.. 3.

(16) Chapter 2 ESD Protection Device for RF Applications. 2.1 Introduction. Nanoscale CMOS technologies have been used to implement the highfrequency integrated circuits with the advantages of scaling-down feature size, low power consumption, high integration capability, improving high-frequency characteristics, and low cost for mass production [1]. However, the MOS transistors are very sensitive to the electrostatic discharges (ESD) events [2], [3]. In order to sustain the required ESD robustness, such as 2kV in human-body model (HBM) [4], [5], the on-chip ESD protection circuit must be equipped for the pads that may be stressed by ESD, including the input/output (I/O) pads [6], as shown in Fig. 2.1. Conventional ESD protection devices with large dimensions have large parasitic capacitances. The parasitic capacitance will cause signal loss from the pad to ground. Therefore, the ESD protection device couldn’t introduce too large parasitic capacitance to degrade the circuit performance [7]. The conventional on-chip ESD protection scheme is shown in Fig. 2.2, where dual diodes at I/O pad are assisted with the power-rail ESD clamp circuit to prevent internal circuits from ESD damage [6]-[8]. The diode is typically used as effective on-chip ESD protection device due to the small parasitic loading effect and high ESD robustness [9], [10]. However, as the operating frequency of circuits increase, the parasitic capacitance is more strictly limited. To overcome this challenge, several prior designs have been reported. The ESD 4.

(17) protection designs with T-coil [11] and T-diode [12] have been presented for teen GHz applications. The stacked diodes [13] and inductor-to-ground [14] have been presented for 24GHz applications. Some ESD protection designs for 60GHz applications have been presented, including inductor-to-ground [15], [16], distributed ESD protection [17], modified LC tank [18], inductor-trigger SCR [19], diodes hidden behind an inductor [20], T-coil with distributed ESD diodes [21], and pi-type ESD block [22].. Fig. 2.1. Whole-chip ESD protection for internal circuit.. Fig. 2.2. Conventional ESD protection with dual diodes.. 5.

(18) 2.2 Whole-Chip ESD Protection Design. Electrostatic discharge (ESD) becomes an important issue on the reliability of integrated circuit (IC). The advanced processes obviously degrade the ESD robustness of IC’s in the CMOS technologies. Generally, a typical specification for an RF circuit on human-body-model (HBM) ESD robustness and machinemodel (MM) ESD robustness are 2 kV and 200 V, respectively [23], [24]. Both of them are used to evaluate the robustness of the ESD when the IC has been charged through touching by human body or machine. The equivalent circuits of HBM and MM ESD tests are show in Fig. 2.3(a) and (b), respectively. In the HBM ESD test, the charges stored in the capacitor would be discharged through the 1.5kΩ resistor into the device under test (DUT). On the other hand, the charges stored in the capacitor would be discharged directly into the DUT in the MM ESD test. Therefore, it is necessary to adding the ESD protection circuit beside I/O pads, which provide electrostatic discharge path and keep the circuit without damage from ESD stress. There’s also equipped power-rail ESD clamp circuit between 𝑉𝐷𝐷 and 𝑉𝑆𝑆 to realize whole-chip ESD protection design.. 6.

(19) (a). (b). Fig. 2.3. Equivalent circuits of (a) HBM and (b) MM ESD tests.. 7.

(20) 2.3 CMOS ESD Protection Device for RF Circuit. 2.3.1 ESD Protection Design with Diodes. Forward bias diode is an ESD protection device with good ESD robustness and has been widely used in the design of RF electrostatic discharge protection circuit. Fig. 2.4 show the four ESD-stress modes on I/O pads. When positive electrostatic discharge from I/O pads to 𝑉𝐷𝐷 (positive-to-𝑉𝐷𝐷 , PD), electrostatic current will release by forward bias 𝐷𝑃 . When positive electrostatic discharge from I/O pads to 𝑉𝑆𝑆 (positive-to-𝑉𝑆𝑆 , PS), electrostatic current will flowing through 𝐷𝑃 and then release by the power-rail ESD clamp circuit. When negative electrostatic discharge form I/O pads to 𝑉𝑆𝑆 (negative-to-𝑉𝑆𝑆 , NS), electrostatic current will release by forward bias 𝐷𝑁 . When negative electrostatic discharge from I/O pads to 𝑉𝐷𝐷 (negative-to- 𝑉𝐷𝐷 , ND), electrostatic current will flowing through the power-rail ESD clamp circuit and release by forward bias 𝐷𝑁 . However, the parasitic capacitance of ESD protection diodes would degrade the performance of circuit when circuit operating frequency gradually increase. PD. ND. VDD. DP. I/O Pad. Internal Circuits. Power-Rail ESD Clamp Circuit. DN. VSS. NS. Fig. 2.4. ESD protection design with diodes. 8. PS.

(21) 2.3.2 ESD Protection Design with SCR Silicon-controlled rectifier (SCR) device consists of a lateral NPN and a vertical PNP bipolar transistor to form a 4-layer PNPN structure is shown in Fig. 2.5. This four-layer structure has the same performance with the structure which will occur the latch up problem. SCR has excellent ability to provide the good ESD robustness with minimal layout area. Fig. 2.5 also marked the electrostatic discharge path when this circuit is affected by ESD stress. Compared with the diode, silicon controlled rectifier has smaller parasitic capacitance. Furthermore, advanced process operating voltage gradually decline lets the risk of the latch up gradually reduced. Therefore, SCR becomes a very potentially ESD protection device. In the practical application, Silicon-controlled rectifier must design with the trigger circuit to enhance the turn on speed. The trigger circuit may consist of transistors, diodes, resistors, capacitors and other active and passive components.. VDD. I/O Pad. Internal Circuits P N P N. SCR. PS. VSS. NS. Fig. 2.5. ESD protection design with SCR.. 9. ND PD. Power-Rail ESD Clamp Circuit.

(22) 2.3.3 ESD Protection Design with Inductor-Triggered SCR. When the operating frequency of the circuit is gradually increased to more than ten GHz, the parasitic capacitance of silicon controlled rectifier may still too large to the high-frequency circuits. Thus, Fig. 2.6 is a concept based on silicon-controlled rectifiers parallel with an inductor [25]. This design can lets the signal loss be zero because the equivalent impedance at the resonant frequency is infinite. However, this design requires a MOS switch. This switch is operating at high frequencies and it should turn on when the circuit stressed by ESD. Furthermore, the control signals of this MOS switch required by the power clamp ESD protection circuit. Therefore, this design might be more complex to achieve.. PD. I/O Pad. ND. VDD. NS. Internal Circuits P N P N. PS. VSS. Fig. 2.6. ESD protection design with LTSCR.. 10. Power-Rail ESD Clamp Circuit.

(23) Chapter 3 Design of Inductor-Assisted Silicon-Controlled Rectifier. 3.1 Introduction. The integrated circuits operated in K-band (18-27GHz) and Ka-band (26.540GHz) have been developed for short-range communication [26]-[30]. For example, 24GHz for wireless network solutions [26], 22-29GHz for short-range automotive radars [27], and 22-46GHz for local multipoint distribution service [28], [29]. The ESD protection design for the integrated circuits operated in K/Ka band is needed. In this work, a novel inductor-assisted silicon-controlled rectifier (LASCR) device is proposed for effective on-chip ESD protection in K/Ka-band.. Fig. 3.1. SCR cross-sectional view and ESD current paths.. The proposed LASCR is shown in Fig. 3.1, which consists of an SCR [31], an inductor, and a diode string. The ESD current path from anode to cathode. 11.

(24) consists of P+/N-well/P-well/N+ SCR. The diode string is used to enhance the turn-on efficiency of SCR [32], [33]. The ESD current path from cathode to anode consists of P-well/N-well diode and inductor. The equivalent circuit of the LASCR is shown in Fig. 3.2(a), where 𝑄𝑃𝑁𝑃 is formed by the P+, N-well, and P-well, and the 𝑄𝑁𝑃𝑁 is formed by the N-well, P-well, and N+. As ESD zapping from anode to cathode, the positive-feedback regenerative mechanism of 𝑄𝑃𝑁𝑃 and 𝑄𝑁𝑃𝑁 results in the SCR device highly conductive to make SCR very robust against ESD stresses. Under normal circuit operating condition, the inductor can resonate with the parasitic capacitance.. (a). (b). Fig. 3.2. Equivalent circuit of LASCR, where SCR expressed by (a) BJT and (b) diodes.. To simulate this device by using foundry provided model, the equivalent circuit of the LASCR can be further expressed by P+/N-well diode (𝐷𝑃+⁄𝑁𝑊 ), P12.

(25) well/N-well diode (𝐷𝑃𝑊⁄𝑁𝑊 ), inductor (L), and diode string (𝐷1 , ..., 𝐷𝑛 ), as shown in Fig. 3.2(b). The dimension of SCR depends on the required ESD robustness, and the diode numbers and dimension of diode string depend on the trigger ability. Once the dimension of SCR has been chosen, the inductor can be designed to minimize the high-frequency performance degradation by using L=. 1 𝐶𝑃+⁄𝑁−𝑤𝑒𝑙𝑙×(2𝜋𝑓0 )2. (3.1). where 𝑓0 is the operating frequency and 𝐶𝑃+⁄𝑁𝑊 is the parasitic capacitance of 𝐷𝑃+⁄𝑁𝑊 and is show in Fig. 3.3. Of course, the high-frequency performances are also affected by the parasitic resistances of diodes and inductor, and they can be simulated by using the real diode and inductor models.. I/O Pad. L. CP+/N-well. CN-well/P-well CP-well/N+. VSS Fig. 3.3. Equivalent circuit of LASCR.. Fig. 2.8 shows that electrostatic discharge path of inductor-assisted siliconcontrolled rectifier when the circuit is stressed by ESD. When positive electrostatic discharge from I/O pads to VSS (positive-to-VSS , PS), electrostatic current will release by silicon-controlled rectifier. When positive electrostatic 13.

(26) discharge from I/O pads to VDD (positive-to-VDD , PD), electrostatic current will flows through silicon-controlled rectifier to VSS and then release by power-rail ESD clamp circuit. When negative electrostatic discharge form I/O pads to VSS (negative-to- VSS , NS), electrostatic current will release by inductor and PN junction (N − well⁄P − well) which is in the silicon-controlled rectifier. When negative electrostatic discharge from I/O pads to VDD (negative-to-VDD , ND), electrostatic current will flowing through the power-rail ESD clamp circuit and release by PN junction (N − well⁄P − well ) and inductor. Besides, LASCR provide the bidirectional ESD current paths between I/O pads and VSS , so it can achieve the whole chip ESD protection by using only an LASCR and a powerrail ESD clamp circuit.. Fig. 3.4. Co-design of SCR and inductor’s ESD protection circuit.. 14.

(27) 3.2 Design of LASCR. In this work, all LASCR devices are fabricated in 0.18 CMOS process and shown in Table 3.1. The sizes of SCR are selected as 30um and 60um. Since the circuit which fabricated in 0.18 CMOS process typically operated at 1.8V, the diode number in the diode string should more then 3, so as not to trigger the ESD protection device when the circuit is under the normal operation mode. As the result, the diode numbers in the diode string are selected as 3 and 5, and the size of each diode is 15um or 30um. The CP+⁄NW of 30um and 60um SCR around 30GHz are ~60fF and ~120fF, respectively. Therefore, the values of required L for K/Ka-band applications are 460pH and 230pH, respectively. The simulation of inductor is completed by using HFSS, as shown in Fig. 3.3.. Fig. 3.5. 3D EM simulation of inductor.. 15.

(28) Table 3.1 Design specification of the proposed LASCR SCR. SCR. Diode. Operating. Power-Rail. Frequency. ESD Clamp. (GHz). Circuit. 30. No. Diode Cell Name. Width. Length. Width. (um). (um). (um). Quantity. LASCR_W30_3D. 3 30. 15. LASCR_W30_5D. 5 7. LASCR_W60_3D. 3 60. 30. LASCR_W60_5D. 5. 3.3 Comparing Device. In order to compare the difference between the proposed design and previous designs, this study also fabricated few kinds of diode-triggered SCR (DTSCR) and diode devises. Table 3.2 show that size of SCR are selected to be 30um and 60um, while the diode numbers in the diode string are 3 and 5, the dimension of each diode is 15um or 30um, four devices are not equipped with the power-rail ESD clamp circuit. Fig. 3.6 is the equivalent circuit of DTSCR and can be seen that inductance is the only difference between DTSCR and LASCR. The size of diode device is show in Table 3.3.. Fig. 3.6. Equivalent circuit of DTSCR.. 16.

(29) Table 3.2 Design specification of the proposed DTSCR SCR Width. Diode Width. Cell Name. Power-Rail ESD Diode Quantity. (um). (um). Clamp Circuit. DTSCR_W30_3D. 3 30. 15. DTSCR_W30_5D. 5. DTSCR_W60_3D. 3. No 60. 30. DTSCR_W60_5D. 5. Table 3.3 Design specification of the proposed diode Power Clamp Cell Name. Diode Type. Diode Width (um) Circuit. 𝐍 +⁄𝐏𝐖 Dual Diodes_W30. 30. 𝐏 +⁄𝐍𝐖. Yes. 3.4 Simulation Results. The high-frequency characteristics are simulated by using the microwave circuit simulator ADS with the selected device dimensions. In the two-port simulation, a signal source with 50Ω impedance drives the port 1 and a 50Ω load is connected to the port 2. The port 1, port 2, and the anode of LASCR are connected together, and the cathode of LASCR is connected to ground. The simulated S11 and S21 of test devices are compared in Fig. 3.5. At 30GHz, the. 17.

(30) 30um dual diodes (Dual Diodes_W30) have 2.5dB loss, while the 30um LASCR with three diodes (LASCR_W30_3D), the 30um LASCR with five diodes (LASCR_W30_5D), the 60um LASCR with three diodes (LASCR_W60_3D), and the 60um LASCR with five diodes (LASCR_W60_5D) only have 0.5dB, 0.4dB, 0.8dB, and 0.8dB loss, respectively. Among the K/Ka-band, the loss of each LASCR is lower than 3dB, which is more suitable for ESD protection. The proposed devices under normal power-on conditions and ESD transient events are simulated by using HSPICE. Fig. 3.6(a) shows the HSPICE-simulated voltage/current waveforms of one test device, LASCR_W30_5D, under the normal power-on condition. Under the normal power-on condition, the dc bias of anode is raised from 0V to 1.8V with 0.5ms rise time. The test device is kept off with very low leakage current. Fig. 3.6(b) shows the simulated voltage/current waveforms of LASCR_W30_5D under the ESD transition, where a 0V-to-5V voltage pulse with 10ns rise time is applied to the test device to simulate the fast transient voltage of HBM ESD event. When a positive fasttransient ESD voltage is applied to anode with cathode grounded, the LASCR_W30_5D can be turned on to discharge ESD current from anode to cathode. With the limited voltage height of 5 V in the voltage pulse, the simulation result can check the clamping ability of LASCR before the internal circuit breakdown.. 18.

(31) (a). (b). Fig. 3.7. Simulated 𝑆11 and 𝑆21 of test devices.. (a). (b). Fig. 3.8. Simulated voltage/current waveforms of LASCR_W30_5D under (a) normal power-on condition and (b) ESD-like transition.. 3.5 Experimental Results of Test Devices. Five test devices have been fabricated in a nanoscale CMOS process. All test devices are implemented with ground-signal-ground (G-S-G) pads to facilitate on-wafer two-port S-parameters measurement. Fig. 3.7 shows the chip micrograph of one test device, LASCR_W30_3D. The other LASCR devices. 19.

(32) have almost the same layout arrangement. The cell area of LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D are 100x95um2 , 100x105um2 , 90x90um2 , and 90x100um2 , respectively.. Fig. 3.9. Chip micrograph of LASCR_W30_3D.. 3.5.1 High-Frequency Performances In order to extract the intrinsic characteristics of the test devices in high frequencies, the parasitic effects of the G-S-G pads have been removed by using the de-embedding technique [34]. With the on-wafer two-port measurement, the S-parameters of these test devices have been extracted. The source and load resistances to the test circuits are kept at 50 Ω. The measured S11 and S21 versus frequencies among the test devices are shown in Fig. 3.8. As shown in Fig. 3.8(a), the LASCR devices exhibit good input matching (S11 < -15dB) around 30 GHz, while Dual Diodes_W30 only has S11 = -8.1dB. At 30GHz, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D have 1.3dB, 1.4dB, 1.6dB, and 1.5dB loss, respectively, while Dual Diodes_W30 has 2.7dB loss.. 20.

(33) (a). (b). Fig. 3.10. Measured 𝑆11 and 𝑆21 of test devices.. 3.5.2 ESD Robustness The HBM ESD robustness of each device is tested. The failure criterion is defined as the I-V curve seen between test pads shifting over 30% from its original curve after ESD stressed at every ESD test level. According to the measurement results, LASCR_W30_3D, LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D can pass +4.5kV, +4kV, +7.5kV, and +7.5kV HBM ESD tests, respectively. Besides, these LASCR devices can also pass -4kV, -4kV, 7.5kV, and -7.5kV HBM ESD tests, respectively. The Dual Diodes_W30 can only pass +3kV and -3.5kV HBM ESD tests. To investigate the turn-on behavior and the I-V characteristics in highcurrent regions of the test devices, the transmission line pulsing (TLP) system with a 10ns rise time and a 100ns pulse width is used. The trigger voltage (𝑉𝑡1 ), holding voltage (𝑉ℎ ), and secondary breakdown current (𝐼𝑡2 ) of test devices in the time domain of HBM ESD event can be extracted from the TLP-measured IV curves. The TLP-measured I-V curves of test devices are shown in Fig. 3.9. Once the pulses stressed to the test devices, LASCR_W30_3D and 21.

(34) LASCR_W60_3D (LASCR_W30_5D and LASCR_W60_5D) can be triggered on at ~5V (~7.6V). The 𝑉ℎ of all LASCR devices exceed 𝑉𝐷𝐷 (1.8V in the given CMOS process), which is safe from latchup event. For the currenthandling. ability. of. ESD. protection. devices,. LASCR_W30_3D,. LASCR_W30_5D, LASCR_W60_3D, and LASCR_W60_5D can achieve the TLP-measured 𝐼𝑡2 of 2.4A,2.1A, 4.2A, and 4.0A, respectively, while Dual Diodes_W30 has only 1.8A. The turn-on behavior can ensure the effective ESD protection capability of the proposed LASCR. The standby leakage current of the test devices can also be measured by using the TLP system. At 1.8V bias, all LASCR devices have the leakage current of <1nA. All measurement results of the test devices are summarized in Table 3.4.. Fig. 3.11. TLP I-V curves of test devices.. 22.

(35) Table 3.4. Design Parameters. Design Parameters and Measurement Results of Test Devices. SCR Diode. LASCR_W30. LASCR_W30. LASCR_W60. LASCR_W60. Dual. _3D. _5D. _3D. _5D. Diode_W30. 30μm. 30μm. 60μm. 60μm. 15μm×3. 15μm×5. 30μm×3. 30μm×5. String. 𝑫𝑷 = 𝟑𝟎μm 𝑫𝑵 = 𝟑𝟎μm. Inductor 460pH. 460pH. 230pH. 230pH. 100×95𝛍𝐦𝟐. 100×105𝛍𝐦𝟐. 90×90𝛍𝐦𝟐. 90× 𝟏𝟎𝟎𝛍𝐦𝟐. 20×35𝛍𝐦𝟐. -16.0dB. -16.3dB. -15.4dB. -15.9dB. -8.1dB. -1.3dB. -1.4dB. -1.6dB. -1.5dB. -2.7dB. +4.5kV/-4kV. +4kV/-4kV. +7.5kV/-7.5kV. +7.5kV/-7.5kV. +3kV/-3.5kV. TLP 𝑽𝒕𝟏. 5.1V. 7.6V. 5.0V. 7.6V. N/A. TLP 𝑽𝒉. 2.9V. 2.9V. 3.2V. 3.3V. N/A. TLP 𝑰𝒕𝟐. 2.4A. 2.1A. 4.2A. 4.0A. 1.8A. 0.5nA. 0.2nA. 0.9nA. 0.5nA. <0.1nA. 4.5nA. 4.0nA. 7.9nA. 8.6nA. -. (L) Area 𝑺𝟏𝟏 at 30GHz 𝑺𝟐𝟏 at 30GHz. Measurement Results. HBM ESD Level. Leakage at 1.8V (𝟐𝟓° 𝐂) Leakage at 1.8V (𝟏𝟎𝟎° 𝐂). 3.5.3 Failure Analysis The failure analysis (FA) has been done to seek the failure location. The FA picture of the LASCR_W30_3D after 5kV HBM ESD stress, LASCR_W30_5D after 4.5kV HBM. ESD stress,. LASCR_W60_3D after. 8kV HBM. ESD stress,. and. LASCR_W60_5D after 8kV HBM ESD stress are shown in Figs. 3.12-3.15. After HBM ESD stress, the damaged regions are all located on the SCR device.. 23.

(36) diode string. P+. P+. N+. N+. Fig. 3.12. The SEM pictures of the LASCR_W30_3D after +5kV HBM stresses. diode string. P+. P+. N+. N+. Fig. 3.13. The SEM pictures of the LASCR_W30_5D after +4.5kV HBM stresses. 24.

(37) N+ diode string. P+. N+ P+. Fig. 3.14. The SEM pictures of the LASCR_W60_3D after +8kV HBM stresses.. diode string. N+. N+ P+ P+ N+ P+. Fig. 3.15. The SEM pictures of the LASCR_W60_5D after +8kV HBM stresses.. 25.

(38) 3.5.4 Leakage In order to investigate the influence of temperature on the device, the leakage of LASCR devices at 25° C and 100° C are measured. Table 3.4 also shows that leakage of LASCR devices at different temperatures. At 25° C , leakage of LASCR_W30_3D is 0.5 nA, LASCR_W30_5D is 0.2 nA, LASCR_W60_3D is 0.9 nA, and LASCR_W60_5D is 0.5 nA, respectively. At 100° C, leakage of LASCR_W30_3D is 4.5 nA, LASCR_W30_5D is 4.0 nA, LASCR_W60_3D is 7.9 nA, and LASCR_W60_5D is 8.6 nA, respectively. It can be seen that leakage of the LASCR devices are still small under high temperature.. 3.6 Conclusion. The proposed ESD protection device of LASCR has been developed in nanoscale CMOS process for K/Ka-band applications. Verified in silicon chip, LASCR devices with 30um (LASCR_W30_3D and LASCR_W30_5D) and 60um (LASCR_W60_3D and LASCR_W60_5D) width can pass 4kV and 7.5kV HBM ESD tests, respectively, and they have the loss lower than 3dB in K/Kaband. In fact, LASCR devices exhibit good high-frequency performances between 0~40 GHz, so they can also be used for wideband or high-speed applications. Measurement results verify the high-frequency performances and confirm the ESD protection ability of LASCR. Therefore, the proposed LASCR can be a good solution for ESD protection.. 26.

(39) Chapter 4 K/Ka-Band Low Nosie Amplifier. 4.1 Introduction. As technology progresses, more important applications are use in the K/Ka band, such as wireless network, short-range automotive radars, and local multipoint distribution service. Considering the sensitivity of the system in RF applications, the low noise receiver is necessary. In the receiver system, low noise amplifier (LNA) is a very important and critical circuit as shown in Fig. 4.1.. Fig. 4.1. Receiver system architecture.. The function of low noise amplifier is to provide enough gain to amplify the weak RF signal received by antenna and suppress the influence of noise generated by subsequent stage at the same time. It can also improve signal to. 27.

(40) noise ratio (SNR) and let signal without distortion. Thereby allowing received signals can be correctly demodulation out by the subsequent circuit. Therefore, the needed of accurate transistor small signal model and noise model when design the low noise amplifier is necessary. Because the noise from transistor is the main noise of the overall circuit and may interfere RF signal, then signal will distortion and couldn’t be demodulated by the subsequent stage circuit. Therefore, an accurate transistor small signal model and noise model is very important.. 4.2 Source of Transistor Noise. Transistor noise generated by interpreting the results as Brownian motion caused. However, transistors is susceptible noise in the small signal operating conditions. Generally, transistor noise can be divided into thermal noise, distributed gate resistance noise, and flicker noise.. 4.2.1 Channel thermal noise Channel thermal noise is due to the electron perturbations within the transistor channel. Channel electrons excited by the heat and random motion, so that transistor produces random changes in voltage and current. These voltage and current changes produce thermal noise, and then define the effective noise power with equation (4.1) 𝑃𝑎𝑣 = 𝑘𝑇∆𝑓. (4.1). where k is Boltzmann constant, which is 1.38 × 10−23 (J/K). T is the absolute temperature, ∆𝑓 is the noise bandwidth with units of Hz. By equation (4.1) knows that, when the conductor temperature increase, effective noise power will 28.

(41) increase. Analysis the influence of thermal noise in the circuit would equivalent the thermal noise to a parallel noise current source, and must assume the transistor as ideal state without any noise. Schematic diagram is show in Fig. 4.2. The noise power equation is (4.2) 𝐼𝑛 2 (f) = 4kTγ𝑔𝑚. (4.2). where k is Boltzmann constant, which is 1.38 × 10−23 (J/K). T is the absolute temperature. 𝑔𝑚 is the drain transduction value when bias is zero. Value of γ would greater than 1 in the short channel, and would be 2⁄3 in the long channel.. Fig. 4.2. Transistor channel thermal noise model.. 4.2.2 Distributed Gate Resistance Noise During the CMOS process, the poly layer is used on the gate. Therefore, the gate will produce polysilicon resistors. Equation and model is show in equation (4.3) and Fig. 4.3, respectively. 𝑅𝑔 = 𝑅ℎ. 𝑊 3𝑛2 𝐿. (4.3). In equation (4.3), 𝑅ℎ is the polysilicon resistors, n is the number of transistors 29.

(42) finger, W and L are the transistors width and length, respectively. The equation of output noise provided by the distributed gate resistance is 𝑉𝑛,𝑜𝑢𝑡 2 = 4𝑘𝑇. 𝑅𝑔 3. (𝑔𝑚 𝑟𝑜 )2. (4.4). From equation (4.3) and (4.4), if want to achieve low noise circuit design, use larger number of fingers and lower channel width in the same transistor size can make gate resistance smaller. Thereby reducing the noise generated by the resistor.. Fig. 4.3. CMOS transistors gate resistance model.. 4.2.3 Flicker Noise Flicker noise is the major noise when CMOS transistors operating at low frequencies. The flicker noise mostly occurs between the gate oxide layer and the silicon substrate surface. Due to silicon crystal and the surface at this interface will produce a discontinuous bond, when the current passes will randomly be captured and released, causing transistor drain current unstable and produce flicker noise, but when the frequency greater than a specific frequency,. 30.

(43) flicker noise will be smaller than the thermal noise. This situation can be explained by equation (4.5). 𝑉𝑛 2 =. 𝐾 𝐶𝑜𝑥 𝑊𝐿. ×. 1. (4.5). 𝑓. Where K is the process parameters.. 4.3 Parameters of Low-Noise Amplifier. 4.3.1 Noise Figure To know the amplifier noise figure (NF), we must first understand the noise factor (F). The definition of noise factor is the input signal-noise ratio dividing the output signal-noise ratio, and can calculated by equation (4.6). F=. 𝑆𝑁𝑅𝑖𝑛 𝑆𝑁𝑅𝑜𝑢𝑡. 𝑆𝑖𝑛 ⁄𝑁𝑖𝑛. =. 𝑆𝑜𝑢𝑡 ⁄𝑁𝑜𝑢𝑡. 𝑆𝑖𝑛 ⁄𝑁𝑖𝑛. =. 𝐺𝑆𝑖𝑛 ⁄(𝐺𝑁𝑖𝑛 +𝑁𝑎 ). =1+. 𝑁𝑎 𝐺𝑁𝑖𝑛. (4.6). 𝑆𝑖𝑛 is input signal power, 𝑆𝑜𝑢𝑡 is output signal power, 𝑁𝑖𝑛 is input noise power, 𝑁𝑜𝑢𝑡 is output signal power, G is the amplifier gain, and 𝑁𝑎 is the noise power interior of amplifier. For example, in a two-stage amplifier, equation (4.7) show that two-stage amplifiers noise factor. F=. 𝑁2 𝑁𝑖𝑛 𝐺1 𝐺2. In equation (4.7), 𝐹1 = 1 + 1+. 𝑁𝑎2 𝑁𝑖𝑛 𝐺2. =1+ 𝑁𝑎1. 𝑁𝑖𝑛 𝐺1. 𝑁𝑎1 𝑁𝑖𝑛 𝐺1. +. 𝑁𝑎2 𝑁𝑖𝑛 𝐺1 𝐺2. = 𝐹1 +. 𝐹2 −1 𝐺1. (4.7). is the first-stage amplifiers noise factor, 𝐹2 =. is the second-stage amplifiers noise factor. So we can use the results. of the two-stage amplifier to infer the n-stage amplifier noise factor should be the following equation (4.8). F = 𝐹1 +. 𝐹2 −1 𝐺1. +. 𝐹3 −1 𝐺1 𝐺2. + ⋯+. 𝐹𝑛 −1 𝐺1 𝐺2 …𝐺𝑛−1. (4.8). By observation of equation (4.8), knows that multiple cascading amplifier noise 31.

(44) factor is mainly determined by the first-stage amplifier. Therefore, the first-stage amplifier matching network and architecture are the most important things during the design of low-noise amplifier. Other stage of amplifier is primarily responsible for increasing the gain. Finally, we can define the noise figure of the following equation (4.9). F in this equation is noise factor. NF = 10 log 𝐹. (4.9). 4.3.2 Gain In the low-noise amplifier design, gain is an important parameter to consider. If the gain of low-noise amplifier not enough, it could be unable to suppress the noise of subsequent circuit. It also cause the large noise figure and let signal distortion. When design the RF amplifier, there have three kinds of power gain equation (4.10)-(4.12). They are transducer power gain (𝐺𝑇 ), operation power gain (𝐺𝑃 ), and available power gain (𝐺𝐴 ), respectively. Definition of 𝐺𝑇 is the value of power delivered to the load divided the value of power available from the source. Definition of 𝐺𝑃 is the value of power delivered to the load divided the value of power input to the network. Definition of 𝐺𝐴 is the value of power available from the network divided the value of power available from the source. They also are displayed in Fig. 4.4.. 𝐺𝑇 =. 𝑃𝐿 𝑃𝐴𝑉𝑆. 𝐺𝑃 = 𝐺𝐴 =. 1−|Γ𝑆 |2. = |1−Γ. 𝑃𝐿 𝑃𝑖𝑛. 𝑃𝐴𝑉𝑁 𝑃𝐴𝑉𝑆. 𝑖𝑛 Γ𝑆. 1−|Γ𝐿 |2. × |𝑆21 |2 × |1−S |2. 22 Γ𝐿 |. 2. 1−|Γ𝐿 |2. 1. = |1−Γ. 𝑖𝑛. × |𝑆21 |2 × |1−S |2. 1−|Γ𝑆 |2. = |1−S. 2 11 Γ𝑆 |. 2. 1. × |𝑆21 |2 × |1−Γ. Γ𝑖𝑛 = 𝑆11 +. 32. 22 Γ𝐿 |. 2 𝑂𝑈𝑇 |. 𝑆12 𝑆21 Γ𝐿 1−𝑆22 Γ𝐿. (4.10) (4.11) (4.12) (4.13).

(45) Γ𝑜𝑢𝑡 = 𝑆22 +. 𝑆12 𝑆21 Γ𝐿 1−𝑆11 Γ𝐿. (4.14). Fig. 4.4. Two-port network actual power diagram.. 4.3.3 Stability In the design of the amplifier, stability is a very important parameter need to take into consideration. If the amplifier is in an unstable state, characteristic of the circuit will be substantially reduced. Equation (4.15) and (4.16) are the amplifier circuit unconditionally stable definition, if the circuit is fit to these two equation, the amplifier is unconditionally stable. k=. 1−|𝑆11 |2 −|𝑆22 |2 +|∆|2 2|𝑆12 𝑆21 |. >1. |∆| = |𝑆11 𝑆22 − 𝑆12 𝑆21 | < 1. (4.15) (4.16). 4.4 Design of K/Ka Band Low-Noise Amplifier. Traditionally, low-noise amplifier architecture most commonly used as a common-source configuration or cascode configuration. Compare the performance of these two configuration can found some features between them. 33.

(46) DC supply for cascode configuration is twice times of common-source configuration, so cascode configuration maximum available gain will much higher than the common-source configuration, but the power consumption of the cascode configuration will double, and the minimum noise figure will be more than common-source configuration, too. Due to hoping to reach the application of low-voltage and low noise figure in this design, so choose the common-source configuration for low-noise amplifier design. On the other hand, to provide the low-noise amplifier has enough gain at K/Ka band to suppress the noise from the subsequent stage. We choice the twostage cascade common-source amplifier for this study.. VDD2 VDD. RFout RFin. VG. VG. Fig. 4.5. K/Ka-band low noise amplifier architecture.. Fig. 4.5 is the low-noise amplifier architecture of this study. First input stage using a series inductor and a source degeneration inductor to achieve the input noise match and still have a good gain to suppress the noise figure from subsequent stage. Between the first stage and second stage, T-model is use to complete the stage-to-stage conjugate match. The second output stage using 34.

(47) series capacitance and inductor to complete output conjugate match.. 4.4.1 Common-source transistor bias and size analysis Select the bias of transistor is the first step of amplifier design. In CMOS 0.18μm process, the maximum of common-source configuration 𝑉𝐷𝐷 is 1.8V, and the gate bias (𝑉𝐺 ) is one of the main selection during design. 𝑉𝐺 choice will affect the value of transduction (𝑔𝑚 ), the drain current (𝐼𝑑 ), and the noise figure (NF). So the greater 𝑉𝐺 will cause the greater current and the greater power consumption. According to system requirements, we need to make trade-offs between these three parameters. Fig. 4.6 is the transistor DC-IV curve. Through the figure we can observe the ID become lower when 𝑉𝐺𝑆 increase. Then Fig. 4.7 show that the transistor will enter the saturation region when 𝑉𝐺𝑆 is more than 0.8V, and 𝐼𝑑 will rapidly increase when 𝑉𝐺𝑆 is more than 0.4V. In order to prevent excessive power consumption, the smaller 𝐼𝑑 will be choose in this study. Fig. 4.8 show that there is a minimum of noise figure when 𝑉𝐺𝑆 is near 0.7V. Based on the above considerations, the final choice of the LNA transistor 𝑉𝐺𝑆 is 0.7V.. Fig. 4.6. Transistor dc I-V curve. 35.

(48) Fig. 4.7. Transistor 𝑔𝑚 and 𝐼𝑑 curve.. Fig. 4.8. Transistor minimum noise figure curve. 36.

(49) The second step is selected transistor size. Transistor has three optional parameters, they are channel length, channel width, and number of finger, respectively. However, the channel length of transistors are usually choice of the smallest value, which can reach a maximum value of transistors transduction. In TSMC 0.18μm CMOS process, the minimum value of channel length is 0.18μm, so the channel length is choose as 0.18μm. The Maximum of gain (MAG) and minimum of noise figure (𝑁𝐹𝑚𝑖𝑛 ) under different channel length is show in Fig. 4.9 and Fig. 4.10, respectively. Fig. 4.9 show that the available maximum gain (MAG) increase with the transistor width, but when the channel width is greater than 5μm, the increase rate of gain become smaller. Therefore, the channel length will design near 5μm. Fig. 4.10 show that when number of finger become larger, the minimum noise figure and power consumption will increases. After consideration of the above conditions, select the channel width of 5μm, the number of finger with 10 as common-source transistor size.. 37.

(50) Fig. 4.9. MAG in different channel width and number of finger.. Fig. 4.10.. 𝑁𝐹𝑚𝑖𝑛 in different channel width and number of finger. 38.

(51) 4.4.2 Matching network design After deciding the amplifier overall structure, followed by low noise amplifier matching network design. Matching network using inductors and capacitors to achieve. Fig. 4.11 is the two-stage cascade low-noise amplifier matching network. Input matching is use the noise match, that noise figure can be minimized. Both of output matching and stage-to-stage matching are use the conjugate match, which can provide the greatest gain. In the low-noise amplifier matching network design, input noise matching network is the most important part of design. If design is not well, it would let the signals which transfer to the post-stage circuit have excessive noise and make signal distortion. Therefore, we prefer to design the input matching network, then design stage-to-stage matching and output matching, finally tuning the circuit.. RFin. RFout. Noise Match. Conjugate Match. Conjugate Match. Fig. 4.11. Two-stage cascade low-noise amplifier matching network design.. 1. Input noise matching To achieve noise matching, the first step is to find the noise circle and. 39.

(52) 𝑁𝐹𝑚𝑖𝑛 can be found in the noise circle. Then design the input matching network let the input impedance of 50Ω matched to 𝑁𝐹𝑚𝑖𝑛 point. First stage noise matching design circuit is show in Fig. 4.12. It is using source degeneration inductance and series a gate inductance to achieve input noise match. Fig. 4.13 is the simulation of input noise circle. The lowest noise can available at 𝑁𝐹𝑚𝑖𝑛 impedance point. The step size of noise circle is 0.25dB every lap. In order to let the amplifier get the lowest noise, input port of 50Ω need to reach 𝑁𝐹𝑚𝑖𝑛 impedance point through the matching network design. The matching network locus plot can be seen from Fig. 4.13. First, source degeneration inductor would let input impedance increase, make the input impedance conjugate point closer to the 𝑁𝐹𝑚𝑖𝑛 point, then series a gate inductor. Therefore, that could be able to reach a conjugate match and noise match at the same time, then send the signal to the next stage with low-noise and high-gain.. S11. RFin Lg1 Noise Match. VG1. Fig. 4.12. First stage noise matching design circuit. 40. Ls.

(53) Fig. 4.13. Input noise match locus plot.. 2. First stage and second stage matching. After design the input matching circuit, the first stage and second stage matching would use conjugate match. First, find the first-stage common-source amplifier output impedance point (𝑆22 ), and then find the second stage common-source amplifier input impedance point (𝑆11 ). The goal is matching the first-stage common-source amplifier output impedance point (𝑆22 ) to the second stage common-source amplifier input impedance conjugate point (𝑆11 ∗). In this study, using a T-model design in Fig. 4.14, which contains two series inductor and a shunt inductor. Fig. 4.15 is. 41.

(54) matching locus smith chart. Then we can complete the stage-to-stage conjugate match.. L1. L3. L2. S11* S11. S22 Ls. Fig. 4.14. Stage-to-stage matching circuit.. Fig. 4.15. Stage-to-stage matching locus plot.. 42.

(55) 3. Output conjugate matching Final is the output matching design. Output stage will use conjugate match to reach the maximum gain. Fig. 4.16 show that to find the second stage output impedance point (𝑆22 ), and matching the 50Ω output impedance to the second stage output impedance point (𝑆22 ), then finished the output matching.. C. RFout. L S22. 50Ω. Fig. 4.16. Output matching circuit.. 43.

(56) 4.5 Simulation Result. Cd VG2. RFout. M3 Ld. L1 RFin. L3 M2. M1 L2. Lg. VG1. Ls. VG1. VDD2. VDD1. Fig. 4.17. K/Ka band low noise amplifier overall architecture figure.. The low-noise amplifier in this study is using 0.18um CMOS process, the overall circuit architecture shown in Fig. 4.17. Simulation of small-signal Sparameters and noise figure is using Agilent ADS (Advanced Design System). All passive components in the architecture such as transmission lines, inductors, and capacitors are using EM electromagnetic simulation software (HFSS) to complete full-wave electromagnetic simulation, and analysis all simulated results by ADS. The parameters of the components is show in Table 4.1.. 44.

(57) Table 4.1 K/Ka-band low-noise amplifier components parameters Device. Value. Device. Value. M1. 5um / 0.18um. Input-stage Lg. 529.8 pH. M2. 5um / 0.18um. Input-stage Ls. 220 pH. M3. 5um / 0.18um. Inter-stage L1. 291.2 pH. Output-stage Ld. 755.5 pH. Inter-stage L2. 329.0 pH. Output-stage Cd. 27.6 fF. Inter-stage L3. 238.3 pH. Fig. 4.18 is the S-parameter simulation result. Small-signal gain (S21) at 24GHz is about 18dB. Input return loss (S11) is greater than 15dB. Output return loss (S22) is greater than 25dB. Fig. 4.19 is the simulation of noise figure, and noise figure is about 3.5dB at 24GHz. Fig. 4.20 is the layout diagram of the chip.. Fig. 4.18. Low-noise amplifier S-parameters simulation result. 45.

(58) Fig. 4.19. Low-noise amplifier noise figure simulation result.. Fig. 4.20. Layout top view of low-noise amplifier.. 46.

(59) 4.6 Measurement results. Fig. 4.21 is chip micrograph of K/Ka-band low-noise amplifier. Layout area is 0.75mm × 0.60mm. Chip measurement methods using on wafer measurement mode. The high-frequency signal input and output terminals using GSG RF probe measurements. DC supply voltage using a power supply, S-parameter using a network analyzer to measure. Noise figure using noise analyzer measurements. Fig. 4.22 is the low-noise amplifier S-parameter measurement value, the small signal gain at 21GHz is maximum about 9.46dB. Fig. 4.23 is the low-noise amplifier noise figure, value of noise figure between 16.5-26.5 GHz is less than 10dB, and has minimum about 7dB at 21GHz.. Fig. 4.21. Chip micrograph of low-noise amplifier.. 47.

(60) Fig. 4.22. Gain and return loss of the low-noise amplifier.. Fig. 4.23. Noise figure of low-noise amplifier.. 48.

(61) 4.7 ESD protection device equipped with LNA. To test the ESD protection ability of the ESD protection device, we also fabricated other three LNA equipped with different kinds of ESD protection device. Fig. 4.24-4.29 are LNA layout diagram and chip micrograph which equipped LASCR, dual diode, and DTSCR, respectively. Fig. 4.30 show that gain of the LNA. Through the figure can be seen LNA without equipped ESD protection device can’t bear 0.5kV ESD HBM test. At 21GHz, dual diodes_LNA has maximum gain about 11.27dB, DTSCR_LNA has maximum gain about 12.09dB, and LASCR_LNA has maximum gain about 11.61dB, respectively. Dual diodes_LNA equipped with a N+/PW diode (DN30) and a P+/NW (DP30) diode. Both of the diode width is 30μm. Fig. 4.31-4.33 show that comparison of gain, S11 , S22 before and after HBM test, respectively. Dual diodes_LNA has gain of 11.07dB after 1.5kV HBM test and 2.90dB after 2kV HBM test at 21GHz, respectively. DTSCR_LNA equipped with a SCR and series three diodes. Width of the SCR and diodes are 30um and 15um, respectively. Fig. 4.34-4.36 show that comparison of gain, S11 , S22 before and after HBM test, respectively. DTSCR_LNA has gain of 12.13dB after 2kV HBM test and 0.05dB after 3kV HBM test at 21GHz, respectively. LASCR_LNA equipped with a SCR, an inductance, and series three diodes. Width of the SCR and diodes are 30um and 15um, respectively. The value of inductance is 460pH. Fig. 4.37-4.39 show that. comparison of gain, S11 , S22. before and after HBM test, respectively. LASCR_LNA has gain of. 11.3dB. after 4kV HBM test and 9.22dB after 5kV HBM test at 21GHz, respectively. 49.

(62) Fig. 4.24. Layout top view of LNA equipped dual diode.. Fig. 4.25. Chip micrograph LNA with dual diode.. 50.

(63) Fig. 4.26. Low-noise amplifier equipped DTSCR layout top view.. Fig. 4.27. Low-noise amplifier with DTSCR chip micrograph.. 51.

(64) Fig. 4.28. Low-noise amplifier equipped LASCR layout top view.. Fig. 4.29. Low-noise amplifier with LASCR chip micrograph.. 52.

(65) Fig. 4.30. Gain of the LNA before and after HBM ESD test.. Fig. 4.31. Gain of the dual diodes_LNA before and after HBM ESD test. 53.

(66) Fig. 4.32. S11 of the dual diodes_LNA before and after HBM ESD test.. Fig. 4.33. S22 of the dual diodes_LNA before and after HBM ESD test. 54.

(67) Fig. 4.34. Gain of the DTSCR_LNA before and after HBM ESD test.. Fig. 4.35. S11 of the DTSCR_LNA before and after HBM ESD test. 55.

(68) Fig. 4.36. S22 of the DTSCR_LNA before and after HBM ESD test.. Fig. 4.37. Gain of the LASCR_LNA before and after HBM ESD test. 56.

(69) Fig. 4.38. S11 of the LASCR_LNA before and after HBM ESD test.. Fig. 4.39. S22 of the LASCR_LNA before and after HBM ESD test. 57.

(70) 4.8 Discussion. In order to investigate the relationship between the components, frequency, and gain, we re-simulate the LNA with precise parameter to meet the measurement result. Fig. 4.40 shows the low noise amplifier architecture with parasitic capacitance and resistance. The measurement results of this study didn’t fit the simulation results might be caused by components parasitic effect. To find out the parasitic component values, we do the simulation of LNA again. Simulation of S-parameters are shown in Fig. 4.41. Table 4.2 also shows the components parameters of parasitic capacitance and resistance. The main reason of the operating frequency change is caused by the output-stage parasitic capacitance (CLd ). Small signal gain is mainly affected by inter-stage capacitance resistances (R2 and R3) and output-stage capacitance resistances (R4 and R5).. R5 CL1. CLg. CL3. VG2. R2. CLd. R1 RFin. M2. M1. R3. VG1. RFout. M3. R4 CL2. CLs. VG1. VDD2. VDD1. Fig. 4.40. K/Ka-band low noise amplifier architecture with parasitic capacitance and resistance.. 58.

(71) Fig. 4.41. Simulation with precise parameter and measurement result of LNA.. Table 4.2 Low-noise amplifier components parameters of parasitic capacitance and resistance Device. Value. Device. Value. 𝐂𝐋𝐠. 20 fF. R1. 15 Ω. 𝐂𝐋𝐬. 60 fF. R2. 15 Ω. 𝐂𝐋𝟏. 15 fF. R3. 100 Ω. 𝐂𝐋𝟐. 50 fF. R4. 7.5 Ω. 𝐂𝐋𝟑. 20 fF. R5. 0.5 Ω. 𝐂𝐋𝐝. 17 fF. 59.

(72) 4.9 Conclusion. This study is using 0.18μm CMOS process to complete the design of K/Ka band low-noise amplifier. Overall circuit architecture is using a two-stage common-source cascade design to achieve the low–voltage and low-noise demand. Input stage uses the source degeneration inductance and gate inductance to achieve conjugate matching and noise matching at the same time. Stage-tostage matching using the T-model inductance to achieved conjugate matching. Output matching uses series inductors and capacitors to achieve conjugate matching. This low-noise amplifier has a maximum gain 9.46dB at 21GHz, the minimum noise figure of 7dB, layout area is 0.75mm × 0.60mm. After adding the ESD protection device of dual diode, low-noise amplifier can bear 1.5kV HBM test, and maximum gain is 11.07dB at 21GHz. DTSCR_LNA can bear 2kV HBM test, and maximum gain is 12.13dB at 21GHz. LASCR_LAN can bear 4kV HBM test, and maximum gain is 11.3dB at 21GHz. Table. 4.3 summarizes out the HBM ESD robustness of each LNA.. Table. 4.3 HBM ESD robustness of LNA Cell Name. HBM ESD Robustness. LNA. 0kV. Dual diode LNA. 1.5kV. DTSCR_LNA. 2kV. LASCR_LNA. 4kV. 60.

(73) Chapter 5 Conclusions and Future Works. This chapter summarizes the main results and contributions of this study. Future works of the inductor-assisted silicon-controlled rectifier for ESD protection design in CMOS process are also provided in the chapter.. 5.1 Main Contributions of This Study. In this study, a kind of ESD protection device has been developed in nanoscale CMOS technology for RF ESD protection design. Each of the test devices and low-noise amplifier has been successfully verified in the test chip. In Chapter 2, some ESD protection devices such as diode and SCR has been introduces. This chapter also show that four discharge path when circuits are stress by ESD. In Chapter 3, LASCR’s architecture and design process is described in detail. Verified in silicon chip, LASCR devices with 30um (LASCR_W30_3D and LASCR_W30_5D) and 60um (LASCR_W60_3D and LASCR_W60_5D) width can pass 4kV and 7.5kV HBM ESD tests, respectively, and they have the loss lower than 3dB in K/Ka-band. All devices in this chapter are fabricated by 0.18um CMOS process. In Chapter 4, design of low-noise amplifier has been described in this chapter. It also contains some important parameters and design considerations of LNA. This chapter also introduced the low-noise amplifier design procedure, few kinds of ESD protection devices are co-design with the LNA. All low-noise 61.

(74) amplifier in this chapter is fabricated in 0.18um CMOS process, and the smallsignal gain of the stand-alone LNA circuit has maximum 9.46dB at 21GHz and minimum noise figure at 21GHz for 7dB. After Inductor-Assisted SiliconControlled Rectifier (LASCR) has been equipped, the circuit can bear 4kV HBM test. The small-signal gain at 21GHz has maximum of 11.3dB. The circuit ESD protection function can be achieved without degrade the low-noise amplifier performance, and also can reach 4kV HBM test.. 5.2 Future Works. With the continuously scaling CMOS technology, the gate oxide becomes much thinner. ESD become one of the most important reliability issues during mass production, must be taken into consideration. Therefore, all integrated circuits used in the wireless communication products need to be equipped with ESD protection designs. However, ESD protections cause radio-frequency (RF) performance degradation with several undesired effects, such as degrade the small-signal gain of the circuit or takes up too much layout area. InductorAssisted Silicon-Controlled Rectifier (LASCR) of this study will be able to overcome these drawbacks. LASCR devices exhibit good high-frequency performance between 0~35GHz, so they can be used for wideband or high-speed applications without degrading the performance of circuit.. 62.

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