In this thesis, we propose three kinds of NCs with different properties (Ge, NiSi and MnSiO NCs) to overcome the limitation of conventional NVMs during the scaling down process.
In chapter 3, we proposed a SiGeO stacking structure serving as Ge nanocrystals self-assembled layer for application of NCs NVM. In additional we fond out that pre-annealing-capping oxide (PACO) is a critical step in our experimental process, and then we used the different oxidized competition mechanism between Si and Ge to form Ge NCs embedded in oxide. The uniform and high density (~1012cm-2) of Ge nanocrystals was fabricated after a rapid thermal annealing (RTA) process. Our propose technique compared with traditional Ge NCs process can be efficiently to prevent the over-oxidation phenomenon of Ge NC which reduces the charge trapping ability.
In chapter 4, we used the similar method that oxygen was replaced by nitrogen to form the Ge NCs embedded in SiNx structure. The memory window for the stacked structure with Ge NCs embedded in SiNx layer is larger than Ge NCs embedded in SiOx layer, due to the extra charge trapping centers generated from the surrounding dielectric of Ge NCs. Furthermore, to compare these Ge NCs structures, we found that the Ge NCs embedded in nitride had better charge storage ability and reliability for NVM characteristics.
In chapter 5 and 6, an ease and low temperature fabrication technique of Ni-O-Si and Ni-Si-N NCs was demonstrated for the application of nonvolatile memory in this thesis. This result can be considered that the oxygen plays a critical role during sputter process for the formation of nanocrystal. In addition, the high
12 -2
also found that high density Ni-Si-N NCs embedded in the silicon nitride (SiNx) and larger memory effect. Therefore, by using an internal competition mechanism of charge trapping layer for these elements, we can form a metallic NCs NVM with low temperature process.
In chapter 7, 8 and 9, a RTA with temperature about 500°C and 600°C at short duration was further used to improve the crystalline quality of NCs and memory reliability. Thermal treatment can efficiently reduce the defects (leakage path) in the SiNx which surrounds the nanocrystal. The charge storage layer of NCs embedded in SiNx shows larger memory window and better reliability over NCs embedded in SiOx, due to different distributions of electronic field in the NC and surrounding dielectric by the simulation results. In addition, multi-layer NiSi NCs NVM structure had better charge storage and retention over than single-layer metal nanocrystals under high temperature test, due to the first and second layer of multi-layer with Quantum confinement effect depended by the NC size.
In chapter 10, for dielectric NCs process, we also used the sputter system to fabricate the manganese silicate (MnSiOx) NCs. The XPS results of charge trapping layer can be identified the chemical state of NCs and built the energy band diagram of our produced MnSiOx thin film. Moreover, by the relationship of current density with temperature, the trap assisted tunneling model can be used to extract the trapping level and density of MnSiOx. The oxygen doping concentration will affect the trap level position and also influence the retention characteristics for the reliability test. Double layer MnSiOx NCs NVM also was fabricated and discussed its NVM effect. The double layer was better trapping and keeping charges ability than single layer because the trapped charges must overcome the trap barrier and then escape from NCs due to the trapping mode of dielectric NCs.
Substrate
Tunnel oxide
Floating Gate Blocking Oxide
Control Gate
Source Drain
Figure 1-1 Structure of the conventional floating-gate nonvolatile memory device.
Continuous poly-Si floating gate is used as the charge storage element.
Figure 1-2 Tunnel oxide and operation voltage scaling predicted by the 2007 International Technology Roadmap for Semiconductors.
Figure 1-3 Development of the gate stack of SONOS EEPROM memory devices. The optimization of nitride and oxide films has been the main focus in recent years.
Figure 1-4 Structure of the SONOS nonvolatile memory device. The nitride layer is used as the charge trapping media.
Figure 1-5 Structure of the nanocrystal nonvolatile memory device. The nanocrystals are used as the charge storage element instead of the continuous poly-Si floating gate.
Figure 1-6 Energy band diagrams of (a) Ge, (b) Ni and (c) HfO2 nanocrystals nonvolatile memories. Sub.: Silicon substrate, Box.: Blocking oxide, G: Gate.
Chapter 2
Basic Principles of Nonvolatile Memory
2.1 Programming/Erasing mechanisms of nonvolatile memory
Most novel nonvolatile memories (NVMs), such as nanocrystals and SONOS memories are based on the concept of Flash memory. If a datum has to be stored in a bit of the memory, there are different procedures. The threshold voltage shift of a Flash transistor can be written as [2.1-2.3]:
FC
T C
V =− Q
Δ (2-1)
where Q is the total charge stored in the floating gate, and CFG is the capacitances between the floating-gate (FG) and control gate. The threshold voltage of memory cell can be altered by charging (discharging) the amount of charge into the FG and defined to the two states of the memory cell, i.e., the binary values (“1” and “0”) of the stored bit. Figure 2-1 shows the threshold voltage shift between two states in a Flash memory. The cure A of Fig. 2-1 is an initial state “1” before the programming operation and the cure B is a writing state “0” when negative charges are stored in the FG. There are many solutions to achieve “programming” or “erasing” operation. In general, tunneling effects included with direct tunneling, Fowler-Nordheim tunneling and band to band tunneling and hot carriers injections are the two kinds of operation mechanisms employed in the NVMs. These modes of stored charges transportation mechanisms will lead to difference characteristics for NVMs and the authors will briefly intro them, as follows,
Figure 2-1 I–V curves of an FG device when there is no charge stored in the FG (curve A) and when negative charges are stored in the FG (curve B).
Modes of Stored Charges Transportation 2.1.1. Tunneling effect
Tunneling mechanisms are demonstrated in the quantum mechanics. Basically, carriers tunneling injection must to have available states to exist on the other side of the barrier. If we assume elastic tunneling, this is a reasonable assumption due to the thin oxide thickness involved. In other words, there is no any energy loss during tunneling processes. The tunneling probability is depended on electron barrier height (φ(x)), tunnel dielectric thickness (d ) and effective mass (me), that is express as:
) ) 2 (
exp(
∫
0−
=
d
e dx m T x
η
ϕ (2-2)
The carriers tunneling effect through the tunnel oxide can be attributed to different
applied gate electric field. Hence, Direct tunneling (DT), Fowler-Nordheim tunneling (FN), modified Fowler-Nordheim tunneling (MFN) and trap assistant tunneling (TAT) are the main programming mechanisms employed in the NVM application. Fig. 2-2 shows these four tunnel effects approaches to programming methods.
A. Direct Tunneling effect (DT)
For nanocrystal memories, the control-gate coupling ratio of nanocrystal memory devices is inherently small [2.4]. As a result, FN tunneling cannot serve as an efficient write/erase mechanism when a relatively thick tunnel oxide is used, because the strong electric field cannot be confined in one oxide layer. When the thickness of tunnel oxide is below 5 nm, the direct tunneling is employed in nanocrystal memories instead. In the other hand, the direct tunneling is more sensitive to the barrier width than barrier height which two to four orders of magnitude reduction in leakage current can still be achieved if the metals with large work function, such as Au or Pt [2.5].
B. Fowler–Nordheim Tunneling effect (FN)
The Fowler–Nordheim (FN) tunneling mechanism occurs when applying a strong electric field (in the range of 8–10 MV/cm) across a thin oxide. In these conditions, the energy band diagram of the oxide region is very steep. Therefore, there is a high probability of electrons’ passing through the energy barrier itself. Using a free-electron gas model for the metal and the WKB approximation for the tunneling probability [2.6], one obtains the following expression for current density [2.7]:
⎥⎦ forbidden gap of the dielectric, h is the Planck’s constant, q is the electronic charge, and F is the electric field through the oxide. However, the exponential dependence of
tunnel current on the oxide-electric field causes some critical problems of process control because, for example, a very small variation of oxide thickness among the cells in a memory array produces a great difference in programming or erasing currents, thus spreading the threshold voltage distribution in both logical states.
C. Modified Fowler-Nordheim tunneling (MFN)
Modified Fowler–Nordheim tunneling (MFN) is similar to the traditional FN tunneling mechanism, yet the carriers enter the nitride at a distance further from the tunnel oxide-nitride interface. MFN mechanism is frequently observed in SONOS-type memories. The SONOS-type memory is designed for low-voltage operation (<10V, depending on the Equivalent oxide thickness), a relatively weak electric field cannot enhance charges to inject into the charging trapping layer by DT or FN mechanism.
D. Trap assistant tunneling effect (TAT)
The charge storage mediums with many traps may cause another tunneling mechanism. For example, the charges tunnel through a thin oxide and arrive to the traps of nitride layer at very low electric field in SONOS systems. During trap assisted injection the traps are emptied with a smaller time constant then they are filled. The charge carriers are thus injected at the same distance into the nitride as for MFN injection. Because of the sufficient injection current, trap assistant tunneling may influence in retention [2.8].
DT occur when
Figure 2-2 Four tunnel effects approaches to programming methods described by Hu and White et al.
2.1.2. Channel Hot-Electron Injection (CHEI)
The physical mechanism of CHEI is relatively simple to understand qualitatively.
An electron traveling from the source to the drain gains energy from the lateral electric field and loses energy to the lattice vibrations (acoustic and optical phonons).
At low fields, this is a dynamic equilibrium condition, which holds until the field strength reaches approximately 100kV/cm [2.9]. For fields exceeding this value, electrons are no longer in equilibrium with the lattice, and their energy relative to the conduction band edge begins to increase. Electrons are “heated” by the high lateral electric field, and a small fraction of them have enough energy to surmount the barrier between oxide and silicon conduction band edges. Figure 2-3 shows schematic representation of CHEI MOSFET and the energy-distribution function with different fields. In the other hand, the effective mass of hole is heavier than one of electron. It is too hard to obtain enough energy to surmount oxide barrier. Therefore, hot-hole injection rarely is employed in nonvolatile memory operation. For an electron to overcome this potential barrier, three conditions must hold [2.10].
1) Its kinetic energy has to be higher than the potential barrier.
2) It must be directed toward the barrier.
3) The field in the oxide should be collecting it.
Nevertheless, a description of the injection conditions can be accomplished with two different approaches. The CHEI current is often explained and simulated following the “lucky electron” model [2.11]. This model is based on the probability of an electron’s being lucky enough to travel ballistically in the field G for a distance several times the mean free path without scattering, eventually acquiring enough energy to cross the potential barrier if a collision pushes it toward the Si/SiO2
following events, which are depicted in Figure 2-4 [2.12].
1) The carrier has to be “lucky” enough to acquire enough energy from the lateral electric field to overcome the oxide barrier and to retain its energy after the collision that redirects the electron toward the interface (PΦb).
2) The carrier follows a collision-free path from the redirection point to the interface (PED).
3) The carrier can surmount the repulsive oxide field at the injection point, due to the Schottky barrier lowering effect, without suffering an energy-robbing collision in the oxide (POC).
The current density of CHEI is expressed as
(
b m)
b m ds d
inj E E
I A
I ϕ λ
ϕ
λ −
= ( )2exp (2-4) Here Ids is the channel current and Ad is a constant. φb is the injection barrier and λ is the mean free path associated with the phonon scattering. Em is the lateral electric field at drain.
X E
Sub.
Tunnel oxide
S D
Blocking oxide Gate VGS > 0
VDS > 0
- - -
-Figure 2-3 Schematic cross section of MOSFET. The lateral electric field (E) distribution function is also shown.
Figure 2-4 A schematic energy band diagram describing the three processes involved in electron injection.
2.1.3. Band to Band Tunneling (BTBT)
Band to band tunneling application to nonvolatile memory was first proposed in 1989. I. C. Chen and et al. demonstrated a high injection efficiency (~1%) method to programming EPROM devices [2.13]. Band-to-band Tunneling (BTBT) process occurs in the deeply depleted doped surface region under the gate to drain / gate to source overlap region. In this condition, the band-to-band tunneling current density is expressed as
(a) Band to Band Hot Electron Tunneling Injection
This injection mechanism is used to nonvolatile memory of PMOS structure.
When band-bending is higher than the energy gap of the semiconductor, the tunneling electron from the valence band to the conduction band becomes significant. The mechanism is at the condition for positive gate voltage and negative drain voltage.
Hence, the hot electrons are injected through the tunnel oxide and then recombine the stored electrons as shown in Fig. 2-5.
(b) Band to Band Hot Hole Tunneling Injection
The injection is applied for NMOS nonvolatile memory device. The mechanism is at the condition for negative gate voltage and positive drain voltage. Hence, the hot holes are injected through the tunnel oxide and then recombine the stored electrons as shown in Fig. 2-6.
The electrons (n-type) / holes (p-type) are accelerated by a lateral electric field toward the channel region and some of the electrons with sufficient energy can surmount the potential barrier of SiO2 [2.14-2.16]. Due to the small oxide field, the electron/hole influence through the oxide can easily reach hundreds of coulombs per square centimeter without failure, it means to the improvement reliability of memory
cells.
N-Sub.
Tunnel oxide
S D
Blocking oxide Gate VGS > 0
VDS < 0
+
-- - +
-N-Sub.
Figure 2-5 Schematic sketch and energy band diagram of Band to Band Hot Electron Tunneling Injection.
Figure 2-6 Schematic sketch and energy band diagram of Band to Band Hot Hole Tunneling Injection.
2.1.4. Channel Initiated Secondary Electron Injection (CHISEI)
The main difference between CHE and CHISEL is that CHISEL is highly sensitive to the lateral electrical field and vertical electrical filed. The operation condition is at CHI condition plus negative body voltage (VB). The procedure and the band diagram for the application of CHISEL are as shown in Fig. 2-7. The superior injection of CHISEL operation mode leads to more program efficiency. The improved program efficiency results from the substrate enhanced gate current component.
Under optimized substrate condition, the substrate hot carriers and subsequent injection are expected for the application of low power and high speed.
B B: Second impact ionization Figure 2-7 Schematic sketch and energy band diagram of Channel Initiated Secondary Electron Injection.
2.2 Basic Physical Characteristic of Nanocrystal Memory
The nanocrystal size is about 3 nm ~ 5 nm and hence we must consider that the quantum effect is how to affect the charge storage ability, programming/erasing efficiency and retention. The major quantum effects include with quantum confinement effect and coulomb blockade effect.
2.2.1 Quantum Confinement Effect
The quantum dot is a quasi-zero-dimensional nano-scale object and is also composed by small amount of atoms. The quantum confinement energy depended on nanocrystal size has been studied both experimentally and theoretically with the tight-binding model [2.17]. The quantum confinement effect becomes significant when the nanocrystal size shrinks to the nanometer range, which causes the ground state of nanocrystal to shift to higher energy compared with bulk material [2.18]. This result will reduce the charge storage ability and programming efficiency for the semiconductor nanocrystals. The theoretical ground state shift of semiconductor and metal nanocrystals has been proposed by W. Guan et al. at 2007 [2.19]. The ground state shift (△E) of Ge and Ni nanocrystals are expressed as
252 Where E (∞ ) is the conduction band minimum for bulk Ge and d is the diameter of nanocrystal. For example, a 3 nm Ge nanocrystal can have a conduction band shift of 0.5 eV as compared with bulk Ge, which is significant enough to affect the electrical performance of the nanocrystal memory cell. Figure 2-8 shows the conduction band minimum up-shift of silicon nanocrystal and Fermi level up-shift of metal NC as a function of nanocrystal size by W. Guan’s model.
2.2.2 Coulomb Blockade Effect
When one electron is stored, the nanocrystal potential energy is raised by the electrostatic charging energy e2/2C, where C is the nanocrystal capacitance, which depends mainly on the nanocrystal size, though it also depends on tunnel oxide thickness and control oxide thickness. The capacitance is self-consistently calculated using an electrodynamics method [2.20]. The electron charge will raise the nanocrystal potential energy and reduce the electric field across the tunnel oxide, resulting in reduction of the tunneling current density during the write process. It is more dominant at low programming voltages (< 3V). In a flash memory array, device cells often encounter disturbances with low gate voltage soft-programming. The Coulomb blockade effect can effectively inhibit the electron tunneling at low gate voltage and improve the flash memory array immunity to disturbance. However, the Coulomb blockade effect should be reduced by employing large nanocrystal if large tunneling current and fast programming speed were desired. The Coulomb blockade effect has a detrimental effect on the retention time, since the electrons in the nanocrystal have large tendency to tunnel back into the channel if the nanocrystal potential energy is high in retention mode. In the energy band diagram of Fig. 2-9, the Coulomb blockade charging energy only raises the electrostatic potential of the nanocrystal.
Figure 2-8 Conduction band minimum up-shift of silicon nanocrystal and Fermi level up-shift of metal NC as a function of nanocrystal size by W. Guan’s model [2.19].
Fig. 2-9 Schematic energy band diagram of coulomb blockade effect (a) before electron injection, and (b) after one electron injection.
2.3 Reliability of Nonvolatile Memory
The reliability of nonvolatile memory has two major parts which one is retention and the other is endurance. These reliability tests are very importance for nonvolatile memory application to the portable electronic productions market and they are norm to define the charge loss ratio in the long-term use. In general, NVMs are required to withstand up to 100K-1M program/erase cycles (endurance) with 10-year memory retention. Therefore, in this section, the authors will present the operation mechanisms and related non-ideal factors of retention and endurance tests.
2.3.1 Retention
In any nonvolatile memory technologies, they are essential to retain data in formation for over ten years. This means the loss of charge stored in the storage medium must be as low as possible. For example, in modern Flash cells, FG capacitance is approximately 1 fF. A loss of only 1 fC can cause a 1V threshold voltage shift. If we consider the constraints on data retention in ten years, this means that a loss of less than five electrons per day can be tolerated [2.21].
Possible causes of charge loss are: 1) by tunneling or thermionic emission mechanisms; 2) defects in the tunnel oxide; and 3) detrapping of charge from insulating layers surrounding the storage medium.
First, several discharge mechanisms may be responsible for time and temperature dependent retention behavior of nonvolatile memory devices. Figure 2-10 shows an energy band diagram of SONOS device in the excess electron state [2.22], illustrating
First, several discharge mechanisms may be responsible for time and temperature dependent retention behavior of nonvolatile memory devices. Figure 2-10 shows an energy band diagram of SONOS device in the excess electron state [2.22], illustrating