Reliability of Nonvolatile Memory

The reliability of nonvolatile memory has two major parts which one is retention and the other is endurance. These reliability tests are very importance for nonvolatile memory application to the portable electronic productions market and they are norm to define the charge loss ratio in the long-term use. In general, NVMs are required to withstand up to 100K-1M program/erase cycles (endurance) with 10-year memory retention. Therefore, in this section, the authors will present the operation mechanisms and related non-ideal factors of retention and endurance tests.

2.3.1 Retention

In any nonvolatile memory technologies, they are essential to retain data in formation for over ten years. This means the loss of charge stored in the storage medium must be as low as possible. For example, in modern Flash cells, FG capacitance is approximately 1 fF. A loss of only 1 fC can cause a 1V threshold voltage shift. If we consider the constraints on data retention in ten years, this means that a loss of less than five electrons per day can be tolerated [2.21].

Possible causes of charge loss are: 1) by tunneling or thermionic emission mechanisms; 2) defects in the tunnel oxide; and 3) detrapping of charge from insulating layers surrounding the storage medium.

First, several discharge mechanisms may be responsible for time and temperature dependent retention behavior of nonvolatile memory devices. Figure 2-10 shows an energy band diagram of SONOS device in the excess electron state [2.22], illustrating trap-to-band tunneling, trap-to-trap tunneling, and band-to-trap tunneling, thermal excitation and Poole-Frenkel emission retention loss mechanisms.

These mechanisms may be classified into two categories. The first category contains tunneling processes that are not temperature sensitive (trap-to-band tunneling, trap-to-trap tunneling and band-to-trap tunneling). The second category contains those

mechanisms that are temperature dependent. Trapped electrons may redistribute vertically inside the nitride by Poole–Frenkel emission, which will give rise to a shift in the threshold voltage. Moreover, at elevated temperatures, trapped electrons can also be thermally excited out of the nitride traps and into the conduction band of the nitride (thermal excitation), and drift toward the tunnel oxide, followed by a subsequent tunneling to the silicon substrate.

Figure 2-10 Energy band diagram of a SONOS device in the excess electron state, showing retention loss mechanisms: trap-to-band tunneling (TB), trap-to-trap tunneling (T-T), band-to-trap tunneling (B-T), thermal excitation (TE) and Poole–Frenkel emission (PF). [2.22]

Secondly, the defects generated in the tunnel oxide can be divided into an extrinsic and an intrinsic one. The former is due to defects in the device structure; the latter to the physical mechanisms that are used to program and erase the cell.

Electrons can be trapped in the insulating layers surrounding the storage medium during wafer processing, as a result of the so-called plasma damage, or even during the UV exposure normally used to bring the cell in a well-defined state at the end of

temperature. The charge variation results in a variation of the storage medium potential and thus in channel length decrease [2.23]. The retention capability of Flash memories need to be checked by using accelerated tests that usually adopt screening electric fields and hostile environments at high temperature.

2.3.2 Endurance

Endurance is the number of erase/write operations that the memory will complete and continue to operate as specified in the data sheet. Generally speaking, Flash products are specified for 10⁶ erase/program cycles. Nevertheless, the endurance requirement may be relaxed with the increase of memory density for the other applications. Figure 2-11 shows the Endurance requirements of NAND Flash memories [2.24].

Figure 2-11 Endurance requirements as a function of memory capacity. [2.24]

The endurance requirement is relaxed to 100K cycles for 256 MB density. In the higher density, a certain cell in a block has less possibility to be written and erased since the memory operation on the cell is repeated after using up the whole memory blocks. The endurance requirement is sufficient for the user to take 700 photos with a 1MB size every day for 10 years. A typical result of an endurance test on a single cell

is shown in Fig. 2-12. As the experiment is performed applying constant pulses, the variations of program and erase threshold voltage levels are described as

“program/erase threshold voltage window closure” and give a measure of the tunnel oxide degradation [2.25, 2.26].

Generated defect

Floating Gate

D

S - - - -

-x

x x

Floating Gate

D S

--

--

-x x x

Program Mode

Earse Mode

Figure 2-12 Threshold voltage window closure as a function of program/erase cycles on a single cell due to the degradation of tunnel oxide.

In particular, the reduction of programmed threshold voltage with cycling is due to trap generation in the oxide and to interface state generation at the drain side of the channel. The evolution of the erase threshold voltage reflects the dynamics of net fixed charge in the tunnel oxide as a function of the injected charge. The initial lowering of the erase is due to a pile-up of positive charge which enhances tunneling efficiency, while the long-term increase of the erase is due to a generation of negative traps.

Moreover, a high field stress on thin oxide is known to increase the current density at low electric field. The excess current component, which causes a significant deviation from the current–voltage curves from the theoretical FN characteristics at low field, is known as stress-induced leakage current (SILC). SILC is clearly attributed by stress-induced oxide defects, which leads to a trap assisted tunneling, as shown in Fig. 2-13. The main parameters controlling SILC are the stress field, the amount of charge injected during the stress, and the oxide thickness. For fixed stress conditions, the leakage current increases strongly with decreasing oxide thickness [2.27-2.28].

Figure 2-13 Anomalous stress induced leakage current (SILC) modeling. The leakage is caused by a cluster of positive charge generated in the oxide during erase. [2.24]