Introduction

Nonvolatile NCs (NCs) memories and SONOS-type memories have recently been promising candidates to take the place of the conventional floating gate nonvolatile memory, because the discrete quantum wells and traps as the charge storage media have effectively improved data retention for the scaling down devices [5.1-5.3]. Although the scaling down tunnel oxide (< 4 nm) is defect-free and high quality, it is still difficult to prevent the storage charges to leak into substrate under retention test. Because of the factor of quantum effect, the wave function of stored electrons can appear in the silicon substrate resulting in larger tunneling probability to increase the charge loss for retention state [5.4], [5.5]. In the pervious studies, the high-k materials can be used to increase the physical thickness of tunnel oxide layer and achieve the same efficiency for scaling down process, such as Si₃N₄, HfO₂ and Al2O3 [5.6], [5.8]. Moreover, C. Y. Ng et al. have proposed a densely stacked silicon NC layers to keep the better retention time, because the charges stored in the NCs near the blocking oxide have low tunnel probability to leak into substrate [5.7].

However, there are very few researches to investigate the formation and nonvolatile memory effect of multi-layer metal NCs.

In our work, the formation and charge storage effect of nonvolatile multi-layer nickel-silicide (NiSi) NCs memory (NMLNCM) were revealed. The NCs were formed by the Ni-Si-N thin film and this proposed memory structure was combined with the benefits of SONOS-type and multi-layer NCs. Hence, we used the

NMLNCM structure to compare with single-layer nickel-silicide NCs for the electrical characteristics of capacitance-voltage (C-V), retention and endurance test in this study.

5.2 Experiment

This memory-cell structure was fabricated on a 4 in. p-type silicon (100) wafer.

After a standard RCA process which removed native oxide and micro-particles, a 3-nm-thick tunnel oxide was thermally grown by a dry oxidation process in an atmospheric pressure chemical vapor deposition furnace. Subsequently, a 10-nm-thick nitrogen incorporated Ni0.3Si0.7 layer served as the charge trapping layer was deposited by reactive sputtering of Ni_0.3Si_0.7 commixed target in the Ar (24 SCCM) and N₂ (10 SCCM)environment at room temperature. The dc sputtering power and pressure were set to 80 W and 7.6 mtorr. Here, the ratio of commixed target (Ni:Si) was decided by the volumes of NCs and surrounding dielectric. Next, a rapid thermal annealing (RTA) process was performed in N₂ ambient and the annealing condition was 600^oC for 100sec. After the annealing step, the NCs would self-assemble in the dielectric layer and the single-layer NCs memory structure was formed by capping a 30-nm-thick SiO2 as the blocking oxide. The cross-sectional transmission electron microscope (TEM) and fabrication flow of NCs embedded in the nitride layer are shown in Fig.

5-1.

Moreover, we used this internal competition mechanism of Ni-Si-N thin film to fabricate the second NiSi NCs layer of multi-layer memory sample and the annealing condition imitated the formed state of our first NCs layer. Then, a 20-nm-thick blocking oxide was deposited on the charge trapping layer to completely make a multi-layer NiSi NCs memory. Finally, Al gate electrodes on back and front side of the samples were deposited and patterned for our proposed memory structures. Form

the NMLNCM cross-sectional TEM image of Fig. 5-2, it is found that the first deposited NCs layer was separated to two layers and we believed this phenomenon was caused by a partial of NiSi NCs diffusing into SiN_x during the second RTA process (the conjectured formation flow of multi-layer NCs structure is also shown in Fig. 5-2) [5.9-5.11]. Therefore, the upper-layer NC size (5-6 nm) is larger than lower-layer (2-3 nm) and we can use this material characteristic to fabricate the multi-layer NCs. By TEM image analysis, there were totally three layers of NCs in this proposed memory structure and the physical thickness of memory cell was the same with single-layer memory structure. Because of this, we were very interested in the nonvolatile memory effect of multi-layer compared with single-layer NCs.

5.3 Results and discussion

Figure 5-3(a) shows the C-V characteristics of single-layer NCs structure and its memory window is only about 4.0 V under ±10 V gate voltage operation. However, the multi-layer NCs structure is clearly observed that the memory windows of 5 V and 13 V can be obtained under ±5 V and ±10 V operation, respectively, as shown in Fig.

5-3(b). The C-V hysteresis loops are counterclockwise, which is due to injection of electrons from the deep inversion layer and injection of holes from the deep accumulation layer of Si substrate [5.12]. The memory window of multi-layer NC structure was much larger than the single-layer NCs at the same voltage sweeping (±10 V) condition. The enhancement of storage capacity was attributed to the high density number of NCs (three-dimensional structure) and strong coupling with conduction channel of metal NCs which was related to the high dielectric constant of charge trapping layer [5.13], [5.14]. In addition, the difference of flat-band voltage between single-layer and multi-layer was also due to strong coupling with conduction

gate control ability in our work. Moreover, the large charge storage ability at scale-down devices can be maintained for the multi-layer structure with NCs embedded in the nitride.

The endurance characteristics of multi-layer NCs and single-layer NCs are provided in Fig. 5-4. Pulses condition of V_G - V_FB = ±5 V for 0.1 ms were applied to evaluate endurance characteristics for the Program/Erase cycles operations. In the endurance test, first, we used this pulse condition to stress our samples and then programmed to a program state or erased to an erase state. After that, we used the read mode to detect the flat band voltage, V_FB (Read mode: The V_FB is obtained by comparing the C-V curves from a charged state or a quasi-neutral state). Figures 5-4(a) and (b) all show the negligible degradation of memory window up to 10⁶ P/E cycles for the multi-layer structure and single-layer. In the endurance test, our proposed memory structures had the advantages for the nonvolatile memory application.

Further analysis of the reliability indicated that the charge retention properties of single-layer and multi-layer NCs memory structures at 27°C and 85°C are demonstrated in Figs. 5-5(a) and (b), respectively. This measurement results were carried out using a fixed gate voltage stress (± 5 V for 10 ms at 27°C and 85°C) and the shift in the flat band voltage as a function of time is obtained by comparing the C-V curves. Form Fig. 5-5(a), we used an extrapolation to give a long-term predictable result (solid and dotted line) after 1000s (stable region of retention) [5.15].

We find that single-layer and multi-layer NiSi NCs all have good chare storage ability and get up to 10 years at room temperature, as shown in Fig. 5-5(a).

However, a serious condition of 85°C can show the advantages of multi-layer NiSi NCs memory and it is found that the charge loss ratio of multi-layer is much lower than single-layer NCs. In this study, we found the leakage currents of single and multi layer NCs memories were very small. Therefore, the blocking oxide was enough

to block the stored electrons to leak into the Al gate. If the stored electrons loss is due to lateral migration effect, the retention test of single and multi layer NCs memories under 85℃ will have the same results. The biggest difference of single and multi layer NCs memory is the position of main stored carriers. The position of main stored carriers for only single layer NCs memory is like the first NCs layer of multi-layer NCs memory. However, the position of main stored carriers for multi-layer NCs memory is the third NCs layer.

Hence, based on the TEM images, we established a energy band diagram of multi-layer NCs embedded in SiN_x layer (as shown in Fig. 5-6) to consider that the reason was due to the charges stored in the upper-layer NCs (the third layer of multi-layer structure) that can be suppressed to leak into substrate under thermal test by the coulomb blockade effect and energy level quantization of the lower-layer NCs (the first and second layers of multi-layer structure) [5.16, 5.17]. The coulomb blockade effect was cause by the carriers existed in second layer NCs (as shown in the second layer of energy band diagram) and this stored charge reduced the electron loss probability from the third layer to the first layer. In addition, the energy level quantization of NCs is limited to the size and effective mass of NC by the theoretical simulation of W. Guan et al. [5.17]. Hence, in this model, the ground states (Fermi level) of first and second layer of multi-layer structure were higher than the third layer because their NC size was smaller than 3 nm. This Fermi level shift can partially suppress the electrons stored in the third NC layer to leak into the first and second NC layers under thermal test. We also depicted this physical phenomenon in the Fig. 5-6 to appear that the nonvolatile multi-layer nickel-silicide NCs memory can effectively keep carriers in the charge trapping layer for a harsh environment.

5.4 Conclusion

In this study we adopted the Ni-Si-N thin film to easy fabricate the NiSi NCs embedded in SiN layer after a RTA process and also proposed a nonvolatile NiSi NCs memory with multi-layer using low thermal budget. This multi-layer NCs structure exhibited superior memory performance for the charge storage capacity and reliability more than single-layer NCs sample. A larger memory window of 13 V was clearly observed after ±10V voltage sweep and the retention can get up to 10 y for next-generation nonvolatile memory application. We also provided an energy band diagram of multi-layer NCs structure to display the predominance of NMLNCM at scaling down process. In addition, this formation technique of charge trapping structure was also suitable for the low temperature substrate on the flexible electronics application.

Figure 5-1 Cross-sectional transmission electron microscope and fabrication flow of NiSi NCs embedded in the nitride layer (Single-layer NCs nonvolatile memory).

Figure 5-2 Cross-sectional transmission electron microscope and fabrication flow of NiSi NCs embedded in the nitride layer (Multi-layer NCs nonvolatile memory).

Figure 5-3 Capacitance-voltage (C-V) hystereses of memory structure with (a) single-layer and (b) multi-layer NCs. The memory windows of (a) 4.0 V and (b) 13.0 V can be obtained under ±10 gate voltage operation, respectively.

Figure 5-4 Endurance characteristics of (a) multi-layer NiSi NC memory and (b) single-layer NiSi NC memory. Pulses condition of VG - VFB = ±5 V and 0.1 ms.

Figure 5-5 Retention characteristics of the NCs memory structure with (a) room temperature, 27°C and (b) 85°C. The dotted line and solid line are the extrapolated value of retention data after 1000 s, which this range is a steady state.

Figure 5-6 Energy bond diagram of multi-layer NiSi NCs embedded in SiNx. The ground states of first and second layer of multi-layer structure were caused by the energy level quantization effect.

Chapter 6

Nonvolatile Memory Effect of Single-layer and Dual Layer Manganese Silicate (MnSiOx) Nanocrystals

6.1 Introduction

Recently, nonvolatile memory (NVM) devices are moving toward high density cell array, low operation voltage, and good reliability. However, the conventional NVM with a floating gate (FG) structure cannot efficaciously prevent data loss in terms of reliability trials for the future scaling down process of tunneling oxide engineering [6.1]. Hence, the next-generation NVM is needed to employ discrete traps or quantum wells as charge storage media to improve retention time. The silicon-oxide-nitride-oxide semiconductor (SONOS) type and nanocrystals (NCs) memory structures have been currently proposed [6.2, 6.3]. In the past few years, many research have shown the high-k material served as charge trapping layer as the potential candidates for replacing the SiN layer [6.4] , and also demonstrated various NCs to provide the charge storage node, such as silicon (Si), germanium (Ge ) and metallic NCs [6.5, 6.6]. Additionally, to use dielectric NCs with high-k material are also investigated by C. H. Chien et al., such as hafnium oxide (HfO2) and Cerium oxide (CeO2) NCs [6.7, 6.8]. These dielectric NCs NVMs are similar to the SONOS-type NVMs, but have more separable trap distribution due to NC structure.

Hence, in this study, we have proposed a dielectric NC, manganese silicate (MnSiOx), and successfully fabricated it by a simple process flow. This MnSiOx NCs are considered that the charges are stored in the discrete traps of dielectric NCs and the distribution of storage charges are dispersed resulting in a lower Coulomb repulsive force in the charge trapping layer. Therefore, good data retention of MnSiOx

NCs for the next-generation NVMs will be discussed.

6.2 Experiment

Figures 6-1 exhibits schematics of the experimental procedures. The fabrication of NCs NVM structures were started with a thermal dry oxidation at 950°C to form a tunnel oxide about 5 nm on p-type (100) Si wafer which had been removed native oxide and micro-particles by RCA process, and then 1-nm-thick a-Si and 9-nm-thick Mn0.2Si0.8 served as a charge tapping layer were deposited by reactive sputtering in the Ar [24 SCCM (SCCM denotes cubic centimeter per minute at STP)] ambiance at room temperature. Before the rapid thermal annealing (RTA) process at 800°C for 30 s in the O2 ambiance, the charge trapping layer was capped by a 10-nm-thick oxide using the plasma enhanced chemical vapor deposition system at 300°C (PACO process). The RTO process was performed to cause the self-assembly of MnSiOx NCs in the charge trapping layer. After RTO process, a 20-nm-thick blocking oxide was also deposited by PECVD. This sample was denoted the sample C.

In addition, we changed the fabrication process of charge trapping layer which was deposited 1-nm-thick a-Si and 9-nm-thick Mn0.2Si0.8 by sputtering in the Ar/O2

(24/1 SCCM) ambiance at room temperature. The RTA process at 800°C for 30 s in the N2 ambiance was performed to cause the self-assembly of MnSiOx NCs in the charge trapping layer. According to previous studies, contrary to conventional RTO process, sputtering in the Ar/O2 ambiance can avoid over oxidation [6.9]. After RTN process, a 30-nm-thick blocking oxide was deposited by PECVD at 300°C. This sample was denoted the sample D. The sample C and D were finally deposited Al gate electrodes to form a metal/oxide/insulator/oxide/silicon (MOIOS) structure, as shown in Fig. 6-1. Electrical characteristics of the capacitance-voltage (C-V) hysteresis were also measured by HP4284 precision LCR meter with high frequency of 1 MHz.

Moreover, transmission electron microscope (TEM) and x-ray photoelectron spectroscopy (XPS) were adopted for the microstructure analysis and chemical material analysis of NCs.

6.3 Results and Discussion

6.3.1 Material and electrical characteristics of Mn silicate (MnSiOx) NC NVMs Figures 6-2(a) and (c) show the cross-sectional TEM images of NCs embedded in oxide layer of sample C and D. From the plane-view image of TEM analysis in Fig.

6-2(b), the NC diameter of sample C is approximately 8-10 nm and the density of the NCs is estimated to be about 8.09×10¹¹ cm^-2. The crystallized NCs with obviously visible lattice images are evident in the insets. Furthermore, the average NC diameter of sample D is approximately 5-6 nm and the area density of the NCs is estimated to be about 2.33×10¹² cm⁻², as shown in Fig. 6-2(c). In these cross-sectional TEM analyses, it was obviously found that less Mn atoms reacted with tunnel oxide during the RTA process due to the first deposited 1-nm-thick a-Si that protected our tunnel oxide.

In our work, the chemical composition of the NCs is demonstrated by XPS analysis using an Al Kα (1486.6 eV) x-ray radiation, as shown in Fig. 6-3. Fig. 6-3(a) exhibits the XPS Mn 2p core-level photoemission spectra that indicated the component is possibly MnSiO3 (642.3 eV) or manganese oxide, not Mn silicide (it cannot find any signal position is lower than 640 eV) [6.10]. The O 1s peak shows Mn silicate centered at 531±0.2 eV from Fig.6-3(b) [6.11]. According to the previous research, Mn oxide is centered on the values below 530 eV by the XPS O 1s analysis [6.12].

We can believe that the main component of NCs in this trapping layer is Mn silicate (MnSiO).

reactions involving Mn silicate and SiO2 formation. Here are some allowed chemical reactions to be listed below [6.13, 6.14].

Si + O2 → SiO2 ΔG298K0 = -732.94 KJ/mol (6-1) Mn + 1/2 O2 → MnO ΔG973K0 = -615.03 KJ/mol (6-2) MnO + SiO2 → MnSiO3 ΔG298K0 = -1244.7 KJ/mol (6-3) MnO + 1/6 O2 → 1/3 Mn3O4 ΔG973K0 = -206.34 KJ/mol (6-4) According to these chemical reactions by Gibbs free energy analysis, Mn prefers forming MnO compound first and then MnO reacts with SiO to form the MnSiO3 NC embedded in oxide.

Figure 6-4 shows capacitance-voltage (C-V) hysteresis of MOIOS structure for the (a) sample C and (b) D. The memory windows of two samples are nearly equal to 1 and 2.5 V under VG-VFB= ±5 V dash line and ±10 V solid line gate voltage operation, respectively. The C-V hysteresis slope of MOIOS structure by the sample D shows less interface damage of tunneling oxide at RTN process. For the sample C, we extrapolate a large number of oxygen diffuse into tunneling oxide and re-oxidize the surface of Si-substrate at RTO process. Here, the sample C and D all presented the same charge storage ability under C-V measurement.

Endurance characteristics of the sample C and D NVM structures are shown in Fig.6-5. Pulses conditions are set at VG−VFB= ± 10V for 10ms. From the data trend of sample C in Fig.6-5(a), it is found that the degeneration of the memory window is serious after 10⁶ Program/Erase (P/E) cycles and keeps 67% compared with the initial memory window. However, the memory window of sample D can keep 86% after 10⁶ Program/Erase (P/E) cycles test, as shown in Fig. 6-5(b). We consider that the endurance results are also to verify the evidence of re-oxidation of Si-substrate in RTO process for sample C.

Figure 6-6 shows charges (electron) remained rate of the sample C and D NVM structures. The charges (electron) remained rate of the sample D (52%) is better than sample C (32%). Here, we also analyzed the oxygen concentration of NCs of sample C and D whose ratios are 70% and 58% by ECSA results. Hence, it is considered that oxygen content of charge trapping center affects the trap level position in the NCs and we will discuss it by our building energy band diagram of Mn silicate NC [6.15, 6.16].

6.3.2 Energy band diagram and trapping level of Mn silicate (MnSiOx) NCs We are most concerned for the energy band diagram and trapping level position of Mn silicate (MnSiOx). Hence, we used the intersection of two straight line which segments-one was fitted to the linear portion of the valence band (VB) leading edge and the other one was fitted to the background channels between the VB and the Fermi level by the Kraut’s method for oxides and high k materials [6.17, 6.18]. Figure 6-7 shows the results that the valence-band spectrum of P-type Si (100), 5 nm SiO2/

P-type Si (100) and 5 nm MnSiOx/ P-type Si (100) by XPS analysis. The valence band offset between MnSiOx and P-type Si (100) is estimated to be about 2.8 eV.

In the dielectric thin films, Plasmon and band to band transitions of XPS signals are appeared in the lower kinetic energy side of primary core-line peaks by the corresponding loss energy. The energy loss for the Plasmon excitation is generally much larger than the energy of excitation from the valence band maximum to the conduction band minimum. Therefore, the band gap values like the high-k dielectric can be determined from the threshold energy of the energy-loss spectrum for O1s and N 1s [6.19, 6.20]. The O 1s photoelectrons energy-loss spectra for 5 nm-thick thermal oxide and 5nm-thick MnSiOx is demonstrated in Fig. 6-8. The band-gap values of thermally grown SiO2 and MnSiOx can be thereby determined to 8.9 eV and ~5.8 eV

sub. is expressed as

ΔEC = Eg (MnSiOx) – ΔEV – Eg (Si) (6-5) where Eg (band gap of MnSiOx), ΔEV (valence band offset) and Eg (band gap of Si) are 5.8, 2.8 and 1.12 eV, respectively. Hence the conduction band offset between MnSiOx and Si is 1.9 eV, as shown in Fig. 6-8. The complete energy band diagram of

ΔEC = Eg (MnSiOx) – ΔEV – Eg (Si) (6-5) where Eg (band gap of MnSiOx), ΔEV (valence band offset) and Eg (band gap of Si) are 5.8, 2.8 and 1.12 eV, respectively. Hence the conduction band offset between MnSiOx and Si is 1.9 eV, as shown in Fig. 6-8. The complete energy band diagram of