Results and discussion

3.1.3.1 Chemical analyses and formation mechanism of Ge nanocrystals

Figure 3-3(a) shows a cross-sectional TEM image of sample A and presents the Ge nanocrystals embedded in oxide layer containing spherical and separated Ge nanocrystals. However, Fig. 3-3(a) shows a kind of double Ge nanocrystal layer. This is a non-ideal result for our fabrication. If we well-control the content of Ge, the double Ge nanocrystal layer maybe become only single Ge nanocrystal layer. In addition, the average diameter of the nanocrystals is approximately 5-6 nm and the area density of the nanocrystals is estimated to be about 1.73×10¹² cm^-2 by TEM analysis.

For the formation of Ge nanocrystals, it was necessary to take into consideration the Gibbs free energy of Si–O and Ge–O at 900^oC.Because of the smaller Gibbs free energy of Si–O (-805 kJ mol^-1) compared with Ge–O (-666 kJ mol^-1) [3.15], the oxygen atoms can interact with the Si atoms easier than with the Ge atoms in the Si1.33Ge0.67O2 layer during the RTA process. This result could be attributed that an internal competition reaction induced the self-assembled effect of Ge nanocrystals in the Si1.33Ge0.67O2 layer, which was dependent on the amount of oxygen of charge trapping layer. The formation mode would be expressed as

2 <2 +

=

+GeO Ge SiO x

SiO_{x x} (3-2) During the thermal treatment, Si atoms will move and bond with oxygen of GeOx resulting in the self-assembled effect of Ge nanocrystals. Figure 3-3(b) shows the XPS analysis of Ge 3d before and after RTA process. In this Ge 3d orbit, the peak is shifted form Ge-O bond (31 eV) to Ge-Ge bond (29 eV) during RTA process.

Figure 3-4(a) shows a cross-sectional TEM of Si1.33Ge0.67O2 thin layer after the RTA process at O2 ambiance (sample B) and the XPS analysis of charge trapping

layer indicates that only GeO2 peak (1220 eV) is existed in the Ge 2p spectra, as shown in Fig. 3-4(b). This result was different to sample A and it was attributed to the excess oxidation during RTA process at O2 ambiance. The chemical reaction of formation of GeO2 nano-dots was expressed as

2

Here, an over-oxidation phenomenon of Ge nanocrystal was to completely form GeO2 nano-dots embedded in the oxide. Therefore, according these experiment results, the Ge nanocrystals embedded in oxide could be formed at the lower thermal budget (short annealing time) and no use of further high pressure H2 treatment or steam process in our experimental method. We successfully used this internal competition reaction between the oxygen, silicon and germanium to prevent the over-oxidation phenomenon of Ge nanocrystals in our work.

3.1.3.2 Electrical characteristics of Ge nanocrystals embedded in oxide

Figures 3-5 shows the electrical characteristics of C-V hysteresis under ± 5 gate voltage operation with (a) Ge nanocrystal embedded in oxide (sample A, use of PACO step), (b) GeO2 nano-dots embedded in oxide (sample B, use of PACO step), and (c) sample A (no use of PACO step). In this case, the memory window for C-V measurement was influenced by PACO process as shown in Fig. 3-5(c), because the Ge atoms of charge trapping layer had out-diffused phenomenon during RTA process by the secondary ion mass spectrometer (SIMS) analysis, as shown in Fig. 3-6 [3.16, 3.17].In Fig. 3-6, it is found that the counts of Ge signal of “no use of PACO (sample A)” are lower than the sample A. Hence, we must use the PACO step to avoid the Ge atoms out-diffusion and keep higher Ge concentration in the charge trapping layer to get better charge storage ability. From Figs. 3-5(a) and (b), it is found that the memory windows of sample A and sample B exhibit 1.0 and 0.5 V under ± 5 gate voltage

operation, respectively. It is perceived that the hysteresis is counterclockwise, due to injection of electrons from the deep inversion layer and discharge of electrons from the deep accumulation layer of Si substrate [3.19]. Moreover, the Ge nanocrystals embedded in oxide presents the superior charge storage ability under ± 10 gate voltage operation, as shown in Fig. 3-5(a). According to the energy band diagrams of Fig. 3-7, we considered that the charge storage ability of semiconductor nanocrystals was decided by the trap density of charge trapping layer. Therefore, except the self-trap of Ge nanocrystals, the surrounding dielectric of nanocrystals also would provide the trap states for the stored charge injection. Due to the better electronic property of Ge nanocrystals embedded in oxide, we would detail to study its programming/erasing characteristics, endurance and retention tests later.

Programming/erasing characteristics of the Ge nanocrystals embedded in oxide under ±5 V gate voltage are shown in Fig. 3-8. The flat band voltage shift is increased as the programming/erasing duration is increased. Moreover, the defined memory window 1.0 V can be obtained at programming/erasing time ~10^-5 s under ±5 V operation. However, the programming/erasing characteristics were found that the flat band voltage shift shown the saturation phenomenon after programming/erasing time

~10^-3 s. This result was due to the Coulomb blockade effect that stored charges were existed in nanocrystal and raised the nanocrystal potential to block the other charge injection. Our proposed memory device revealed a high speed programming/erasing time for further nonvolatile memory application.

To further investigate the reliability of Ge nanocrystals embedded in oxide, Fig.

3-9 presents the endurance characteristics of Ge nanocrystals embedded in oxide under the pulse conditions of VG - VFB = ±5 V for 1 ms. The flat-band voltage can be defined by using the C-V hysteresis under ± 10 gate voltage operation. From Fig. 3-8, it is found that the variation of memory window is stable after 10⁶ P/E cycles for

using the Si1.33Ge0.67O2 layer to form the Ge nanocrystals NVMs. Hence, we used the internal competition reaction method which this technique could be fabricated a good high frequency operation of Ge nanocrystal NVM in our research.

The retention of nonvolatile nanocrystal memory structure with sample A is illustrated in Fig. 3-10. The retention mensuration was performed at room temperature by operating a ± 15 V gate voltage stress for 10 s and measured up to 10⁴ sec. The flat band voltage shift (△Vfb) was obtained by comparing the C-V curves from the charged carries state and quasi-neutral state. We found that the charge holding ratio of Ge nanocrystals embedded in oxide, 25%, after 10ys by analyzing the extrapolation value of retention data (dotted line for program and erase states). Here, the stable charge storage was conserved and the memory window also was retained 1.5V after 10ys. In the previous research, the memory effect for nanocrystals embedded in dielectric is resulted from (1) interface states between the silicon substrate, (2) traps inside the dielectric layer, (3) nanocrystal confined state, and (4) interface states between nanocrystals and the surrounding dielectric. [3.20, 3.21]. The charge retention ability of the deep trap is better than shallow tarp due to lower charge escaping probability for the deep trap. Hence, the rapidly decay in the retention test is due to the charge stored in shallow trap states which is higher energy compared with silicon substrate leading to charges escape to substrate [3.22, 3.23]. This remainder memory window of 1.5 V was enough to define the data information “1” and “0”

according by ITRS road map.