5.3 Device Fabrication
6.3.2 Self-Heating Effect
The SHE is related with the thermal conductivity of the substrate and power dissipation. The thermal conductivity of Si is 155 W/m-K at 300 K, so Joule’s heat generated inside the bulk device can be transferred to the Si substrate. However, the thermal conductivity of SiO2 is only 1.4 W/m-K, which is two orders of magnitude smaller than that of Si. Since poly-Si TFTs or SOI MOSFETs are fabricated on a glass or SOI substrate, the accumulated Joule heat can not be dissipated via the buried SiO2
layer during device operation and then causes an increase in the device temperature.
In recent years, the effect of the electrical-current-induced Joule self-heating on the device characteristics is studied by device simulation or electrical measurement (pulsed I-V and ac conductance methods) [8, 19-20]. These results indicate that the
device temperature can substantially increase with an increase of the power density dissipated in the device. The ION values of the dc I-V characteristics are smaller than those of the pulsed I-V characteristics due to the phonon-limited mobility reduction induced by the SHE, especially for the high driving capability. From our previous discussion, we have fabricated high-performance poly-Si NW TFTs with the superior current driving capability. Furthermore, for high-level applications in the future, poly-Si TFTs will be operated under pulsed bias in the real condition. Therefore, the influence of the self-heating phenomenon on their turn-on characteristics should be investigated by the pulsed I-V measurements.
For the pulsed I-V measurement system of the model Agilent B1530A, it has a remote-sense and switch unit (RSU) to perform dc measurements by the source monitor unit (SMU), a WGFMU for pulsed I-V measurement, and a wave monitor function by the V monitor. The schematic diagram of the pulsed I-V measurement system is shown in Fig. 6-8(a). The gate and drain terminals of the device are connected to the WGFMU channel 1 and WGFMU channel 2, respectively. During the pulsed IDS-VGS measurement, the gate bias is a pulsed sweep, and the drain bias is a constant voltage. The WGFMU channel 1 forces the pulsed gate bias, and the WGFMU channel 2 simultaneously senses the IDS. Figure 6-8(b) shows the definition of the pulse waveform. In addition to the basic pulse parameters, the measurement delay time and the averaging time are necessary to confirm the measurement accuracy.
The base voltage is set to the VGS at which the device is biased at the turn-off state.
Figure 6-9(a) shows an example of the voltage waveform monitored by the V monitor as a function of time. The pulse width and period are set to 1 μsec and 2 μsec, respectively. The rise and fall times are both 100 nsec. The pulsed gate bias sweeps from -0.5 V to 1.5 V, and the constant drain bias is 1 V. It is reasonable that the
measured voltage value sensed with an oscilloscope is ten times smaller than the actual applied voltage owing to the voltage attenuator within the V monitor. Figure 6-9(b) shows an enlarged view of Fig. 6-9(a), and the output waveform corresponds to the user-defined waveform. Overshoot and oscillation phenomena of the pulsed gate bias are not observed, therefore, the accurate output waveform is confirmed by an Agilent infiniium DSO80204B oscilloscope. Furthermore, in addition to the gate voltage waveform monitored by the V monitor, we also simultaneously measure the gate voltage waveform by another external probe to observe if the resistance-capacitance (RC) time constant delay of the gate pad would alter the waveform, as shown in Fig. 6-10(a) and 6-10(b). The pulsed gate bias sweeps from 0 V to 4 V, and other pulse parameters are the same as those of Fig. 6-9(a). According to Fig. 6-10(b), the RC time constant delay of the gate pad is almost zero and can be neglected in practice.
Before measuring the SHE of our high-performance poly-Si NW TFTs, we measure the SHE of the bulk MOSFET and SOI MOSFET at first. The pulse width and period are set to 1 μsec and 2 msec, respectively. The rise and fall times are both 100 nsec. The measurement delay time and the averaging time are set to 200 nsec and 700 nsec, respectively. Therefore, the turn-on time is 0.9 μsec while the turn-off time is 1.9988 msec. In other words, the device has 1.9988 msec to dissipate the heat produced during the turn-on time of 0.9 μsec. To study the SHE, the dc I-V characteristics of the device are also measured and compared with its pulsed I-V characteristics. Figure 6-11(a) and 6-11(b) show the measurement results of the n-type bulk MOSFET with a poly-Si/oxynitride gate stack and p-type SOI MOSFET with a poly-Si/SiO2 gate stack, respectively. Obviously, the SHE does not occur in the n-type bulk MOSFET with LG/W= 75 nm/1 μm owing to the high-thermal-conductive Si
substrate. The pulsed I-V characteristics are the same as the dc I-V characteristics even if the driving current density is as high as 1322 μA/μm at VGS= 1.904 V and VDS= 1.2 V. On the contrary, for the p-type SOI MOSFET with LG/W= 1 μm/10 μm, the SHE occurs and becomes apparent as the driving current density is only equal to 138.4 μA/μm at VGS= -4 V and VDS= -7 V. The relative current amplitude is defined as the current difference between pulsed I-V and dc I-V measurements divided by the current of the pulsed I-V measurement. The relative current amplitude of the p-type SOI MOSFET is 4.28 % at VGS= -4 V and VDS= -7 V. According to these measurement results, we consider that the pulsed I-V measurement system is reliable to study the self-heating phenomenon. These pulse parameters are fixed to execute the next pulsed I-V measurements.
Next, we study the SHE in our n-type NH3-passivated poly-Si NW TFTs with a poly-Si/TEOS oxide stack. The detailed process flow has been described in chapter 5.
Figure 6-12 compares the pulsed I-V and dc I-V curves of the n-type poly-Si NW TFT with LG/W= 300 nm/1 μm. The SHE does not take place because the ION of 30 μA/μm is not high enough to produce Joule heating. Therefore, the SHE can only be observed in high-performance poly-Si TFTs with the higher driving capability. Figure 6-13 and 6-14 show the pulsed I-V and dc I-V curves of the n-type poly-Si NW TFT with LG/W= 30 nm/35 nm and LG/W= 30 nm/120 nm, respectively. For these two figures, as the ION is smaller than 50 μA/μm, the pulsed I-V and dc I-V curves totally overlap with each other. When the SHE occurs with high ION, the pulsed I-V curve gradually deviates from the dc I-V curve. From Fig. 6-13, we observe that the pulsed I-V curve shows higher ION than those of the dc I-V curve, which is similar to that observed in SOI MOSFETs. At VGS= 9.09 V and VDS= 1 V, the pulsed current is 4.5 % higher than the dc current. However, according to Fig. 6-14, we find that the ION measured
by the pulsed I-V technique at VGS= 8.9 V and VDS= 1 V is about 5.21 % lower than in the dc measurement. The reason why the SHE results in different dc I-V behaviors is related to the current transport mechanism in poly-Si TFTs described in 5.3.6. For the n-type poly-Si NW TFT with LG/W= 30 nm/35 nm, it can be regarded as a single-crystal-like device, and its current transport mechanism is the drift-diffusion current. Therefore, when Joule heating raises the temperature of the device during the dc I-V measurement, its ION values decrease due to the phonon-limited mobility degradation. On the other hands, the ION of the n-type poly-Si NW TFT with LG/W=
30 nm/120 nm is governed by thermionic emission over the grain-boundary barrier.
Hence, its ION values increase with an increase of the device temperature induced by Joule heating. As a result, the on-current transport mechanism in poly-Si TFTs plays an important role in the Joule heating process. Figure 6-15 and 6-16 show the pulsed I-V and dc I-V curves of n-type poly-Si NW TFTs with different pulse width. It is reasonable that their pulsed I-V curves are close to their dc I-V curves with increasing the pulse width. Our high-performance poly-Si NW TFT with LG/W= 30 nm/35 nm can operate at high switching speeds without the driving capability degradation.
Figure 6-17 compares the pulsed I-V and dc I-V curves of the n-type poly-Si NW TFT combined with the HfO2 gate dielectric, and its LG/W is equal to 40 nm/20 nm, respectively. The highest ION value of 945 μA/μm can be obtained at VGS= 4 V and VDS= 1 V. In addition to the SHE, we also observe the IDS fluctuation in the pulsed I-V measurement. The IDS fluctuation with discrete levels can be attributed to oxide traps or interface traps in the gate stack, which is called RTN. Figure 6-18 shows an example of the RTN signal observed in the n-type poly-Si NW TFT combined with the HfO2 gate dielectric. Its detailed physical mechanism is discussed in chapter 7.
6.4 Conclusions
The smallest poly-Si NW TFT combined with the HfO2 gate dielectric is demonstrated for the first time. The SCE is well controlled owing to the structure of the HfO2 gate dielectric, the ultra-thin poly-Si NW, and the omega-shaped gate structure. The gate controllability could be further enhanced by scaling the EOT.
Moreover, the S/D parasitic resistance can be reduced by the Ni-silicided S/D.
Therefore, the high-performance poly-Si NW TFT, especially for the ultra-high driving capability of 549 μA/μm, can be achieved without using the MILC and the ELA technology. Furthermore, as the device size of the poly-Si TFT continuously scales down, the SHE starts to occur due to a high driving capability. The relationship between the SHE and the on-current transport mechanism of poly-Si TFTs has been investigated in this chapter. If the on-current transport mechanism of poly-Si TFTs is dominated by thermionic emission above the grain-boundary potential barrier, the ION
degradation can be observed during the pulsed I-V measurement. This phenomenon is commonly seen in large-area and small-grain poly-Si TFTs. On the contrary, for small-area and large-grain poly-Si TFTs, once its on-current transport mechanism is transformed into the drift-diffusion model, its SHE phenomenon is the same as that observed in SOI MOSFETs.
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Table 6-1 Comparison of three n-type MSB poly-Si TFTs.
Device ID A B C
Poly-Si channel
thickness 10 nm 8 nm 45 nm
Grain-boundary
trap density 5.266x1012 cm-2 5.266x1012 cm-2 9.907x1012 cm-2 Gate dielectric HfO2 (10 nm) SiO2 (25 nm) SiO2 (45 nm)
VTH (V) 4.784 4.557 10.68
S.S. (mV/Dec.) 606 933 1637
DIBL (V/V) 2.283 3.143 5.384
Fig. 6-1 Main process flow of the n-type poly-Si NW TFT combined with the HfO2
gate dielectric: (a) after the active area definition, (b) after the HfO2
deposition, (c) after a double spacer formation, and (d) the final device structure.
LG= 40 nm
buried SiO2 TSi= 10 nm
fully Ni-silicided S/D
poly-Si NW channel THfO2= 10 nm
50 nm
Fig. 6-2 (a) Cross-sectional TEM image along the channel direction of the n-type poly-Si NW TFT combined with the HfO2 gate dielectric with LG/W= 40 nm/20 nm.
TSiO2= 3 nm
10 nm
Fig. 6-2 (b) Enlarged view of Fig. 6-2(a) showing a-3 nm-thick amorphous interfacial oxide layer between the HfO2 gate dielectric and the poly-Si NW channel.
20 nm
W= 20 nm
buried SiO2 poly-Si gate
poly-Si NW channel HfO2
gate dielectric
Fig. 6-3 (a) Cross-sectional TEM image along the gate direction of the n-type poly-Si NW TFT combined with the HfO2 gate dielectric with LG/W= 40 nm/20 nm.
poly-Si gate
poly-Si channel buried SiO2
THfO2= 10 nm
20 nm
THfO2= 2 nm
Fig. 6-3 (b) Cross-sectional TEM image of the near GAA device with LG/W= 1 μm/200 nm.
-5 0 5 10 15
Fig. 6-4 Comparison of the typical non-sintered transfer characteristics of the device A, device B, and device C with LG/W= 5 μm/10 μm.
0.10 0.12 0.14 0.16 0.18 0.20 0.22 -19.5 density of the device B.
-2 0 2 4 6
Fig. 6-6 Non-sintered and sintered transfer characteristics of poly-Si NW TFTs combined with HfO2 gate dielectric, and their LG/W= 90 nm/20 nm.
-2 -1 0 1 2 3
Fig. 6-7 Typical sintered transfer and output characteristics of poly-Si NW TFTs combined with HfO2 gate dielectric, and their LG/WG = 40 nm/20 nm.
Fig. 6-8 (a) Connection of pulsed I-V measurements using the WGFMU channel 1 and WGFMU channel 2.
Fig. 6-8 (b) Timing chart of the pulse waveform with the definition of the pulse parameters.
V DS 0.1 V
V GS 0.2 V
Fig. 6-9 (a) Example of the monitored voltage waveform as a function of time. The gate bias is a pulsed sweep, and the drain bias is a constant voltage.
2 μsec 1 μsec
Fig. 6-9 (b) Enlarged view of 6-9(a) showing the output waveform corresponds to the user-defined waveform.
V monitor
External probe
Fig. 6-10 (a) Gate voltage waveforms monitored by the V monitor and the external probe as a function of time.
V monitor
External probe
Fig. 6-10 (b) Enlarged view of 6-10(a) showing the RC time constant delay of the gate pad can be neglected during pulsed I-V measurements.
-1 0 1 2 0
400 800 1200 1600
I DS (μA/μm)
VGS (V)
n-type bulk MOSFET-LG/W= 75 nm/1 μm dc I-V
pulsed I-V: 1 μsec
VDS= 1.2 V
Fig. 6-11 (a) Pulsed I-V and dc I-V curves of the n-type bulk MOSFET with LG/W=
75 nm/1 μm.
-4 -3 -2 -1 0 1 2
-160 -120 -80 -40 0
I DS (μA/μm)
VGS (V)
p-type SOI MOSFET-LG/W= 1 μm/10 μm dc I-V
pulsed I-V: 1 μsec VDS= -7 V
Fig. 6-11 (b) Pulsed I-V and dc I-V curves of the p-type SOI MOSFET with LG/W= 1 μm/10 μm.
0 1 2 3 4 5 6 7 8 9 10
n-type poly-Si NW TFT-LG/W= 30 nm/35 nm dc I-V
pulsed I-V: 1 μsec
VDS= 1 V
Fig. 6-13 Pulsed I-V and dc I-V curves of the n-type poly-Si NW TFT with LG/W=
30 nm/35 nm.
0 1 2 3 4 5 6 7 8 9 10
n-type poly-Si NW TFT-LG/W= 30 nm/35 nm dc I-V
pulsed I-V: 1 μsec pulsed I-V: 100 μsec pulsed I-V: 10 msec
Fig. 6-15 Pulsed I-V curves with different pulse width of the n-type poly-Si NW TFT with LG/W= 30 nm/35 nm.
0 1 2 3 4 5 6 7 8 9 10
n-type poly-Si NW TFT-LG/W= 30 nm/120 nm dc I-V
pulsed I-V: 1 μsec pulsed I-V: 100 μsec pulsed I-V: 10 msec
Fig. 6-16 Pulsed I-V curves with different pulse width of the n-type poly-Si NW TFT with LG/W= 30 nm/120 nm.
Fig. 6-17 Pulsed I-V and dc I-V curves of the n-type poly-Si NW TFT combined with the HfO2 gate dielectric, and its LG/W is equal to 40 nm/20 nm.
0.0000 0.0005 0.0010 0.0015 0.0020 18
19 20
HfO2 poly-Si NW TFT-L
G/W= 40 nm/20 nm VGS-VTH= 2.23 V and VDS= 1 V
I DS (μA)
Time (sec)
Fig. 6-18 Example of the RTN signal observed in the n-type poly-Si NW TFT with the HfO2 gate dielectric, and its LG/W is equal to 40 nm/20 nm.
Chapter 7
Random Telegraph Noise in Small-Area Poly-Si Nanowire Thin-Film Transistors
7.1 Introduction
The impact of LG scaling (LG < 100 nm) on poly-Si NW TFTs with different multi-gate structures has been studied in chapter 5 and 6. These devices exhibit excellent I-V characteristics and good short-channel characteristics. Recent successes in fabricating small-area poly-Si NW TFTs have opened up the possibility of producing the poly-Si-based 3D IC and 3D stackable TFT Flash memories in the future. Therefore, the noise properties of small-area poly-Si NW TFTs should also be simultaneously considered, especially for application in analog IC. LFN, 1/f noise, is the main noise component for these highly scaled devices since it increases as the reciprocal of the gate area [1]. The LFN in large-area poly-Si TFTs has been deeply investigated by several researchers [2-6]. On poly-Si TFTs, the carrier number fluctuation model as in single-crystalline MOSFETs was first proposed to explain the measured low-frequency 1/f-type noise spectra [2-3]. In this model, the spectra density of the drain current (ID) noise is caused by the dynamic trapping and detrapping of free carriers into slow oxide traps [2]. However, C. A. Dimitriadis et al.
found that only the carrier number fluctuation model was not adequate to explain all experimental noise data of their poly-Si TFTs, especially in the low ID region [4].
They considered that the power spectrum of the ID noise is also caused by the