In this dissertation, the main research topics can be divided into two parts. The first part contains the C-doping effects on the thermal stability of Ni silicide, the Ni-silicide-contacted junction characteristics, and the formation of SiC alloys. The process technologies and characteristics of GAA poly-Si NW TFTs are discussed in the second part.
In the first chapter of this dissertation, we briefly review the development of CMOS technology. To reduce the S/D series resistance and avoid SCEs, S/D engineering is necessary to achieve low parasitic resistance contacts and the abrupt doping profile. The advantages and disadvantages of the C-doping effects in Si are
also described in detail. The C-doping technology is a promising candidate for the fabrication of the ultra-shallow Ni-silicide-contacted junction. To relax several scaling barriers, 3D IC composed of poly-Si TFTs is one of the possible solutions. Therefore, the evolution of poly-Si NW TFTs is briefly introduced. High-performance poly-Si TFTs with a small device area are needed to build 3D IC. Furthermore, two main issues including the SHE and RTN phenomena in small-area poly-Si TFTs should be resolved in the near future.
In chapter 2, we study the impact of C and dopant atoms on the thermal stability of Ni silicide by using different C I/I technologies. A novel I/I technology, plasma immersion ion implantation (PIII), is used to implant C ions into the Si substrate surface. The thermal stability and formation of Ni silicide are dependent on the implantation and silicide-forming conditions. These experimental results will be discussed in this chapter.
In chapter 3, the influence of C atoms on the Ni-silicide-contacted Schottky and n+/p junctions is discussed in detail. The reverse-bias leakage current mechanism of the C-doped Ni-silicide-contacted Schottky junction is considered as the increased thermionic-field emission. Furthermore, the agglomeration of the Ni-silicide film and the diffusion of Ni atoms into the depletion region result in an increase of the reverse-bias leakage current of the C-doped Ni-silicide-contacted n+/p junction.
In chapter 4, we propose a low-temperature C I/I technology followed by solid phase epitaxy (SPE) regrowth to fabricate SiC alloys. Different SPE annealing technologies are employed to recrystallize the amorphous Si layer. High substitutional C concentration (Csub) can be obtained by process optimization. We find that excess C concentration in Si leads to incomplete recrystallization and P redistribution phenomena.
In chapter 5, we successfully fabricate the smallest GAA poly-Si NW TFT with LG of 30 nm. Good electrical characteristics are demonstrated by structural engineering. The agglomeration of thin Ni-silicide films in the S/D regions can still be improved by the C I/I technology. The difference of current transport mechanisms in large-area and small-area poly-Si TFTs is clarified. The device characteristics can be further improved by using an ammonia (NH3) plasma treatment.
In chapter 6, to reduce the EOT, the HfO2 high-κ gate dielectric is first introduced into poly-Si NW TFTs. Excellent device characteristics can be achieved, especially for high driving capability. Two SHE phenomena related to different current transport mechanisms are observed in large-area and small-area poly-Si TFTs.
In chapter 7, the two-level and complex RTN phenomena can be both observed in our small-area poly-Si NW TFTs for the first time. They can arise from the slow trap or the fast trap. We also derive the carrier number fluctuation model induced by the grain-boundary trap. Model accuracy is determined by high-temperature measurements.
Finally, in chapter 8, we will summarize important conclusions of this thesis.
Future works are also suggested in this chapter.
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Table 1-1 Doping process technology requirements reported by the 2010 ITRS update for bulk microprocessor unit (MPU) [9].
Year of production 2011 2012 2013 2014 2015
MPU physical gate length (nm) 24 22 20 18 17 Drain extension junction depth (nm) 10.5 9.5 8.7 8 7.3 Maximum allowable parasitic series
resistance (Ω/□) 160 140 130 110 110
Maximum drain extension sheet
resistance (Ω/□) 660 680 750 810 900
Extension lateral abruptness
(nm/decade) 2.8 2.4 2.3 2 1.8
Contact junction depth (nm) 29 26.7 24.7 22 19.8 Allowable junction leakage (μA/μm) 0.1 0.1 0.1 0.1 0.1 Maximum silicon consumption (nm) 14.5 13.4 12.4 11 9.9 Silicide thickness (nm) 17.9 16.2 14.7 13 12 Contact silicide sheet resistance (Ω/□) 9.1 9.9 10.8 12.1 13.5 Contact maximum resistivity (Ω-cm2) 8x10-8 4x10-8 2x10-8 1x10-8 8x10-9
Table 1-2 Utility of the substitutional C atom, the interstitial C atom, and C/I clusters in Si.
Utility Needed C-related elements Gettering of Au and Cu C/I clusters
Elimination of secondary defects substitutional C atom and interstitial C atom Suppression of B and P diffusion substitutional C atom and interstitial C atom Improvement of the thermal stability
of NiSi
segregated C atoms at the NiSi grain boundaries and NiSi/Si interface Application of SiC S/D stressors substitutional C atom
Formation of deep-level defects interstitial C atom and C/I clusters Formation of neutral scattering centers C/I clusters
Fig. 1-1 Future evolution of the MOSFET including device structures and materials [6]. Where PD SOI and FD SOI represent partially depleted silicon-on-insulator and fully depleted silicon-on-insulator, respectively.
MuGFET and MuCFET are the abbreviation for multi-gate FET and multi-channel FET, respectively.