Effect of NH 3 -Plasma Treatment

5.3 Device Fabrication

5.4.6 Effect of NH 3 -Plasma Treatment

It is well known that the NH3-plasma passivation can effectively improve the device characteristics of poly-Si TFTs because the grain-boundary defects of the poly-Si film and the interface states at the poly-Si/SiO2 interface are passivated by hydrogen and nitrogen [7]. The decrease in the grain-boundary scattering results in an increase in carrier mobility and the ION. The VTH and S.S. are also improved, as well as the IOFF originating at the grain-boundary defects. Therefore, in order to further improve the device performance, the NH3-plasma treatment process is performed on our GAA poly-Si NW TFTs.

Figure 5-23(a) compares the transfer characteristics of the smallest n-type MSB device with LG/W= 30 nm/35 nm before and after the NH3 plasma passivation. After the NH3-plasma treatment process, the transfer characteristics of the n-type MSB device are drastically improved and has excellent performance compared to those of the non-NH3-passivated n-type MSB device. The VTH, S.S., and DIBL values decrease to 0.97 V, 224 mV/Dec., and 0.895 V/V, respectively. Before the NH3-plasma treatment process, grain-boundary barriers play important role on current transport and the barriers close to the drain electrode can be reduced more effectively as the VDS increases. Therefore, the DIBL effect is apparent. After the NH3-plasma

treatment process, the grain-boundary barriers are lowered. The transport of electrons becomes dominated by the source-to-channel barrier, and the drain electric field has less influence on the source-to-channel barrier lowering owing to the GAA structure.

Therefore, the DIBL effect can be improved. The Ion/Ioff current ratio is raised to 5x10⁷ at VDS= 1V. We believe that the VTH, S.S., DIBL, and ION values could be further improved by scaling EOT to get better gate controllability. The severe gate-induced-drain-leakage (GIDL) off-state currents may result from the excess encroachment of Ni silicide. Figure 5-23(b) shows the typical output characteristics of the NH3-passivated n-type MSB device with LG/W= 30 nm/35 nm. The normalized ION (IDS/WEFF) at VGS-VTH= 5 V and VDS= 1 V is 187 μA/μm. If normalized to the drawn channel width, the driving current can be as high as 459 μA/μm. As we compared the device characteristics of the NH3-passivated n-type MSB device with the state-of-the-art poly-Si TFTs listed in references [8-11], our device shows the best driving current value due to the ultra-short LG and fully Ni-silicided S/D.

5.5 Conclusions

The smallest workable GAA poly-Si NW TFT with the ultra-short LG of 30 nm has been successfully demonstrated. Thanks to the UTB and GAA structures, the channel electric potential can be well controlled by the gate electrode in spite of a rather thick TEOS gate oxide. The MSB S/D structure reduces the thermal budget and also helps the control of SCEs and reduction of parasitic resistance. Although the grain-boundary defect density can be reduced with device scaling, the electron mobility is still limited by other scattering mechanisms. Owing to the UTB device structure, Coulomb scattering and surface roughness scattering can have a very strong influence on the electron mobility. The high density of interface traps at the

poly-Si/SiO2 interface and significant surface roughness results in low electron mobility. As a result, low interface trap density and control of surface roughness of poly-Si are both needed to improve the electron mobility for poly-Si NW TFTs with the ultra-short LG. From the transfer characteristics of the smallest GAA poly-Si NW TFT measured at various temperatures, it reveals that the on-state current transport mechanism of poly-Si TFTs is no longer limited by thermionic emission and transforms to drift-diffusion transport. The influence of grain-boundary barrier height on the turn-on behavior of the smallest GAA poly-Si NW TFT is ignored at VDS= 1 V, so the smallest GAA poly-Si NW TFT can be regarded as the single-crystal-like device. The additional NH3 plasma treatment was adopted to effectively passivate the grain boundary defects and/or interface states, and it exhibits excellent device characteristics. These results indicate the GAA poly-Si NW TFT would be promising for the 3D IC or SOP field in the near future.

References

[1] S. D. Bortherton, “Polycrystalline Silicon Thin Film Transistor,” Semicond. Sci.

Technol., vol. 10, no. 6, pp. 721-738, 1995.

[2] M. Stewart, R. Howell, L. Pires, and M. Hatalis, “Polysilicon TFT technology for active matrix OLED displays,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 845-851, 2001.

[3] S. D. S. Malhi, H. Shichijo, S. K. Banerjee, R. Sundaresan, M. Elahy, G. P.

Pollack, W. F. Richardson, A. H. Shah, L. R. Hite, R. H. Womack, P. K.

Chatterjee, and H. W. Lam, “Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon,” IEEE Trans.

Electron Devices, vol. 32, no. 2, pp. 258-281, 1985.

[4] E. K. Lai, H. T. Lue, Y. H. Hsiao, J. Y. Hsieh, C. P. Lu, S. Y. Wang, L. W. Yang, T. Yang, K. C. Chen, J. Gong, K. Y. Hsieh, R. Liu, and C. Y. Lu, “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” in IEDM Tech. Dig., 2006, pp. 1-4.

[5] S. Y. Oh, C. G. Ahn, J. H. Yang, W. J. Cho, W. H. Lee, H. M. Koo, and S. J. Lee,

“Thee-dimensionally stacked poly-Si TFT CMOS inverter with high quality laser crystallized channel on Si substrate,” Solid State Electron., vol. 52, no. 3, pp.

372-376, 2008.

[6] C. J. Su, H. C. Lin, and T. Y. Huang, “High-performance TFTs with Si nanowire channels enhanced by metal-induced lateral crystallization,” IEEE Electron Device Lett., vol. 27, no. 7, pp. 582-584, 2006.

[7] F. S. Wang, M. J. Tsai, and H. C. Cheng, “The effects of NH3 plasma passivation on polysilicon thin-film transistors,” IEEE Electron Device Lett., vol. 16, no. 11, pp. 503-505, 1995.

[8] T. C. Liao, S. W. Tu, M. H. Yu, W. K. Lin, C. C. Liu, K. J. Chang, Y. H. Tai, and H. C. Cheng, “Novel Gate-All-Around Poly-Si TFTs With Multiple Nanowire Channels,” IEEE Electron Device Lett., vol. 29, no. 8, pp. 889-891, 2008.

[9] J. T. Sheu, P. C. Huang, T. S. Sheu, C. C. Chen, and L. A. Chen, “Characteristics of Gate-All-Around Twin Poly-Si Nanowire Thin-Film Transistors,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 139-141, 2009.

[10] H. H. Hsu, T. W. Liu, L. Chan, C. D. Lin, T. Y. Huang, and H. C. Lin,

“Fabrication and Characterization of Multiple-Gated Poly-Si Nanowire Thin-Film Transistors and Impacts of Multiple-Gate Structures on Device Fluctuations,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 3063-3069, 2008.

[11] M. Im, J. W. Han, H. Lee, L. E. Yu, S. Kim, C. H. Kim, S. C. Jeon, K. H. Kim, G. S. Lee, J. S. Oh, Y. C. Park, H. M. Lee, and Y. K. Choi, “Multiple-Gate CMOS Thin-Film Transistor With Polysilicon Nanowire,” IEEE Electron Device Lett., vol. 29, no. 1, pp. 102-105, 2008.

[12] T. M. Pan and T. W. Wu, “Effects of Oxynitride Buffer Layer on the Electrical Characteristics of Poly-Silicon TFTs Using Pr2O3 Gate Dielectric,” IEEE Trans.

Electron Devices, vol. 55, no. 6, pp. 1379-1385, 2008.

[13] C. P. Lin, B. Y. Tsui, M. J. Yang, R. H. Huang, and C. H. Chien,

“High-performance poly-silicon TFTs using HfO2 gate dielectric,” IEEE Electron Device Lett., vol. 27, no. 5, pp. 360-363, 2006.

[14] B. Y. Tsui and C. P. Lin, “Process and characteristics of modified Schottky barrier (MSB) p-channel FinFETs,” IEEE Trans. Electron Devices, vol. 52, no.

11, pp. 2455-2462, 2005.

[15] M. W. Ma, T. S. Chao, C. J. Su, W. C. Wu, K. H. Kao, and T. F. Lei,

“High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With TaN/HfO2 Gate Stack Structure,” IEEE Electron Device Lett., vol. 29, no. 6, pp. 592-594, 2008.

[16] C. C. Tsai, Y. J. Lee, K. Y. Chiang, J. L. Wang, I. C. Lee, H. H. Chen, K. F. Wei, T. K. Chang, B. T. Chen, and H. C. Cheng, “Polycrystalline silicon thin-film transistors with location-controlled crystal grains fabricated by excimer laser crystallization,” Appl. Phys. Lett., vol. 91, no. 20, p. 201903, 2007.

[17] S. W. Lee, T. H. Ihn, and S. K. Joo, “Fabrication of high-mobility p-channel poly-Si thin film transistors by self-aligned metal-induced lateral crystallization,”

IEEE Electron Device Lett., vol. 17, no. 8, pp. 407-409, 1996.

[18] J. P. Colinge, “Novel gate concepts for MOS devices,” in Proc. ESSDERC, 2004, pp. 45-49.

[19] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M.

Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys., vol. 53, no. 2, pp. 1193-1202, 1982.

[20] H. Iwai, T. Ohguro, and S. Ohmi, “NiSi salicide technology for scaled CMOS,”

Microelectron. Eng., vol. 60, no. 1, pp. 157-169, 2002.

[21] K. Asano, Y. K. Choi, T. J. King, and C. M. Hu, “Patterning Sub-30-nm MOSFET Gate with I-Line Lithography,” IEEE Trans. Electron Devices, vol. 48, no. 5, pp. 1004-1006, 2001.

[22] D. Deduytsche, C. Detavernier, R. L. V. Meirhaeghe, and C. Lavoie,

“High-temperature degradation of NiSi films: Agglomeration versus NiSi2

nucleation,” Appl. Phys. Lett., vol. 98, no. 3, p. 033526, 2005.

[23] Z. Zhang, Z. Qiu, R. Liu, M. Ostling, and S. L. Zhang, “Schottky-barrier height tuning by means of ion implantation into preformed silicide films followed by drive-in anneal,” IEEE Electron Device Lett., vol. 28, no. 7, pp. 565-568, 2007.

[24] J. M. Larson and J. P. Snyder, “Overview and status of metal S/D Schottky-barrier MOSFET technology,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1048-1058, 2006.

[25] Q. T. Zhao, U. Breuer, E. Rije, St. Lenk, and S. Mantl, “Tuning of NiSi/Si Schottky barrier heights by sulfur segregation during Ni silicidation,” Appl. Phys.

Lett., vol. 86, no. 6, p. 062108, 2005.

[26] D. Connelly, C. Faulkner, P. A. Clifton, and D. E. Grupp, “Fermi-level depinning for low-barrier Schottky source/drain transistors,” Appl. Phys. Lett., vol. 88, no. 1, p. 012105, 2006.

[27] S. D. Kim, C. M. Park, and J. C. S.Woo, “Advanced model and analysis for series resistance in sub-100 nm CMOS including poly depletion and overlap doping gradient effect,” in IEDM Tech. Dig., 2000, pp. 723-726.

[28] S. T. Hsu, “A simple method to determine series resistance and K factor of an MOS field effect transistor,” RCA Rev., vol. 44, no. 3, pp. 424-429, 1983.

[29] B. Y. Tsui, C. P. Lu, and H. H. Liu, “Method for Extracting Gate-Voltage-Dependent Source Injection Resistance of Modified Schottky Barrier (MSB) MOSFETs,” IEEE Electron Device Lett., vol. 29, no. 9, pp.

1053-1055, 2008.

[30] C. Y. Chen, J. W. Lee, S. D. Wang, M. S. Shieh, P. H. Lee, W. C. Chen, H. Y.

Lin, K. L. Yeh, and T. F. Lei, “Negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors,” IEEE Trans.

Electron Devices, vol. 53, no. 12, pp. 2993-3000, 2006.

[31] F. Gamiz, J. B. Roldan, P. C. Cassinello, and P. Cartujo, “Role of surface-roughness scattering in double gate silicon-on-insulator inversion layers,” J. Appl. Phys., vol. 41, no. 12, pp. 2357-2362, 1994.

[32] H. C. Lin, W. C. Chen, C. D. Lin, and T. Y. Huang, “Performance enhancement in double-gated poly-Si nanowire transistors with reduced nanowire channel thickness,” IEEE Electron Device Lett., vol. 30, no. 6, pp. 644-646, 2009.

Table 5-1 Summary of main device parameters of the state-of-the-art

gate Tri-gate Ω-shaped Single

gate Single

Table 5-2 Comparison of various crystallization techniques.

location non-controllable controllable controllable Advantages 1. simplicity

2. low cost Disadvantages 1. high

crystallization 2. high intragrain

defect density

Fig. 5-1 Main process flow of the GAA poly-Si NW TFT integrated with the MSB S/D: (a) after the oxide opening region definition, (b) after the TEOS gate oxide deposition, (c) after a double spacer formation, and (d) the final device structure.

(a)

poly-Si gate

wet oxide

Si substrate 50 nm

poly-Si gate

TEOS gate oxide poly-Si NW

W= 35 nm

wet oxide 20 nm

(b)

Fig. 5-2 (a) Cross-sectional TEM image of the GAA poly-Si NW TFT along the gate direction with LG/W= 200 nm/35 nm. (b) Enlarged cross-sectional view of (a).

L_G= 30 nm

T_Si= 8 nm

poly-Si gate

wet oxide NiSi S/D poly-Si

TEOS gate oxide

50 nm

(a)

50 nm

(b)

Fig. 5-3 (a) Cross-sectional TEM image of the GAA poly-Si NW TFT along the channel direction with LG/W= 30 nm/35 nm. (b) Plan-view TEM of the ultra-thin poly-Si channel.

(a)

(b)

Fig. 5-4 Top-view SEM image of the active area: (a) after EBL and (b) after the PR ashing process with the ashing time of 40 sec.

(a)

(b)

Fig. 5-5 Top-view SEM image of the active area after the PR ashing process with the ashing time of 140 sec: (a) LER degradation and (b) the broken line.

50 nm

wet oxide

NiSi S/D (19 nm)

Fig. 5-6 Cross-sectional TEM image of the NiSi film at S/D pad regions.

30 35 40 45 50 55 60

40 80 120 160 200

NiSi(102) NiSi(211)NiSi(112)

NiSi(200)NiSi(002)

Intensity (counts/sec)

2θ (deg)

NiSi(103) NiSi(013)

Fig. 5-7 XRD spectra of the NiSi film on SiO2/Si substrate after completing the device fabrication.

Gate

Source Drain

Fig. 5-8 Top-view SEM image of the fabricated poly-Si NW TFT with LG/W= 30 nm/500 nm.

Fig. 5-9 AFM image of the NiSi film at S/D pad regions.

Gate

Source Drain

Fig. 5-10 Top-view SEM image of the NiSi film at S/D pad regions implanted with C ions at 1 keV to a dose of 5x10¹⁵ cm^-2.

Fig. 5-11 (a) Transfer characteristics of the smallest SB device with LG/W= 30 nm/35 nm.

0.0 0.2 0.4 0.6 0.8 1.0

Fig. 5-11 (b) Output characteristics of the smallest SB device with LG/W= 30 nm/35 nm.

Fig. 5-12 (a) Transfer characteristics of the smallest n-type MSB device with LG/W=

30 nm/35 nm.

0.0 0.2 0.4 0.6 0.8 1.0 0

50 100 150 200 250 300

V_GS-V_TH= 1, 2, 3, 4, 5 V n-type MSB S/D-L

G/W= 30 nm/35 nm

I DS (μA/μm)

VDS (V)

Fig. 5-12 (b) Output characteristics of the smallest n-type MSB device with LG/W=

30 nm/35 nm.

R

V

＇ V

＇

R

V

I

Fig. 5-13 Equivalent circuit diagram of the ELM.

-5 0 5 10

Fig. 5-14 Linear-region transfer characteristics with different external load resistors of the smallest n-type MSB device with LG/W= 30 nm/35 nm.

0.0 200.0k 400.0k 600.0k 800.0k 0.0

0.00 0.05 0.10 0.15 0.20 0.25 0.0

0.2 0.4 0.6 0.8 1.0

n-type MSB S/D-LG/W= 30 nm/35 nm

-R LO (kΩ-μm)

(VGS-V

TH-0.5V

DS)^-1 (V)^-1 R_T~ 0.299 kΩ-μm μEFF~ 33.8 cm²/V-sec

Fig. 5-16 -RL0 versus (VGS-VTH-0.5VDS)^-1 plot of the smallest n-type MSB device with LG/W= 30 nm/35 nm.

Gate

Source Drain

NiSi NW

Fig. 5-17 Top-view SEM image of the fabricated poly-Si NW TFT with LG/W= 30 nm/35 nm.

30 nm 60 nm 80 nm 100 nm 160 nm 0.0

0.5 1.0 1.5 2.0 2.5

Physical Gate Length V TH (V)

n-type MSB S/D-W= 35 nm

Fig. 5-18 (a) Statistics of the VTH values of the n-type MSB devices with fixed W=

35 nm and various LG.

30 nm 60 nm 80 nm 100 nm 160 nm 100

200 300 400 500 600 700

Physical Gate Length

DIBL (mV/V)

n-type MSB S/D-W= 35 nm

Fig. 5-18 (b) Statistics of the DIBL values of the n-type MSB devices with fixed W=

35 nm and various LG.

30 nm 60 nm 80 nm 100 nm 160 nm 0

100 200 300 400

Physical Gate Length I ON (μA/μm)

n-type MSB S/D-W= 35 nm

Fig. 5-18 (c) Statistics of the ION values of the n-type MSB devices with fixed W= 35 nm and various LG.

35 nm 60 nm 80 nm 120 nm 0.0

0.5 1.0 1.5 2.0

2.5 n-type MSB S/D-L

G= 30 nm

Physical Channel Width V TH (V)

Fig. 5-19 (a) Statistics of the VTH values of the n-type MSB devices with fixed LG= 30 nm and various W.

35 nm 60 nm 80 nm 120 nm 100

200 300 400 500 600

700 n-type MSB S/D-LG= 30 nm

Physical Channel Width

DIBL (mV/V)

Fig. 5-19 (b) Statistics of the DIBL values of the n-type MSB devices with fixed LG= 30 nm and various W.

35 nm 60 nm 80 nm 120 nm 0

100 200 300

400 n-type MSB S/D-L

G= 30 nm

Physical Channel Width I ON (μA/μm)

Fig. 5-19 (c) Statistics of the ION values of the n-type MSB devices with fixed LG= 30 nm and various W.

-5 0 5 10

Fig. 5-20 (a) Temperature-dependent transfer characteristics of the n-type MSB device with LG/W= 5 μm/5 μm.

Fig. 5-20 (b) Temperature-dependent transfer characteristics (linear scale) of the n-type MSB device with LG/W= 5 μm/5 μm biased at VDS= 0.05 V.

0 5 10

Fig. 5-20 (c) Temperature-dependent transfer characteristics (linear scale) of the n-type MSB device with LG/W= 5 μm/5 μm biased at VDS= 1 V.

Fig. 5-21 (a) Temperature-dependent transfer characteristics of the smallest n-type MSB device with L /W= 30 nm/35 nm.

0 5 10

Fig. 5-21 (b) Temperature-dependent transfer characteristics (linear scale) of the n-type MSB device with LG/W= 30 nm/35 nm biased at VDS= 0.05 V.

Fig. 5-21 (c) Temperature-dependent transfer characteristics (linear scale) of the n-type MSB device with LG/W= 30 nm/35 nm biased at VDS= 1 V.

-5 0 5 10

Fig. 5-22 Temperature-dependent transconductance characteristics of the n-type MSB device with LG/W= 30 nm/35 nm biased at VDS= 1 V.

Fig. 5-23 (a) Transfer characteristics of the smallest n-type MSB device with LG/W=

30 nm/35 nm before and after the NH3 plasma passivation.

0.0 0.2 0.4 0.6 0.8 1.0 0

50 100 150 200

V_GS-V_TH= 1 V V_GS-V_TH= 3 V VGS-V

TH= 5 V

I DS (μA/μm)

V_DS (V)

Fig. 5-23 (b) Typical output characteristics of the NH3-passivated n-type MSB device with LG/W= 30 nm/35 nm.

Chapter 6 Fabrication and Electrical Characteristics of Poly-Si Nanowire Thin-Film Transistors with

the High-κ Gate Dielectric

6.1 Introduction

The high driving capability and low-operation voltage are necessary for high-performance poly-Si TFTs. In chapter 5, we have successfully demonstrated the smallest GAA poly-Si NW TFTs with the high driving capability. However, its high VTH and S.S. values are not suitable for low-voltage operation. For conventional poly-Si TFTs, the SiO2 gate dielectric is usually formed by a PECVD technique. The CVD SiO2 is used as the gate dielectric instead of thermal SiO2 because enhanced grain-boundary oxidation leads to non-uniform thermal oxidation along the poly-Si channel. In addition, thermal oxidation at high temperature is not compatible with the low-temperature poly-Si TFT process. The quality of CVD SiO2 is worse than that of thermal SiO2, so the gate dielectric thickness of CVD SiO2 must be thick enough to prevent high gate leakage currents. Thicker CVD SiO2 gate dielectric results in the higher VTH and S.S. values. Therefore, in this chapter, we focus on the scaling of the EOT by using the high-κ gate dielectric. In recent years, poly-Si TFTs with various high-κ gate dielectrics, such as HfO2 and praseodymium oxide (Pr2O3), have been proposed to reduce the EOT [1-2], but the gate electrodes they used are close to planar

structures. In this study, the HfO2 gate dielectric and the novel omega-shaped gate structure are both integrated into poly-Si NW TFTs for the first time. We investigate the short-channel characteristics of poly-Si NW TFTs with LG down to 40 nm.

Furthermore, we also use the UTB structure to achieve high performance. Most research on SOI MOSFETs with the UTB structure has shown excellent electrical characteristics [3-4], so the concept of the UTB structure could be easily extended to poly-Si TFTs. Several studies also indicate reducing the channel thickness of poly-Si TFTs can also achieve higher ION, lower IOFF, steeper S.S., and lower VTH [5-6]. One issue of the ultra-thin TSi is the degradation of its film quality. After the SPC process, the thinner poly-Si film consists of the smaller grain size and thus higher grain-boundary trap density [5]. Therefore, the channel thickness of the published SPC poly-Si TFTs is just thinned to 20 nm [7]. The other issue of poly-Si TFTs with the ultra-thin channel thickness is the high parasitic resistance at the S/D regions.

Both of these issues degrade the driving capability of poly-Si TFTs, so the metal S/D is also used in our study to alleviate the concerns of high parasitic S/D resistance.

Hence, the low VTH and steep S.S. values and the high driving capability can be simultaneously obtained via the optimization of the device structures and process technologies.

The SHE in SOI MOSFETs has been studied for many years [8-9], and it can reduce carrier mobility and the corresponding decrease of the ION owing to Joule heating. Joule heating is proportional to the square of current density, so the SHE of high-performance poly-Si TFTs should be considered due to their high current driving capability. In this work, pulsed I-V measurements are used, for the first time, to observe the self-heating phenomenon of our high-performance poly-Si NW TFTs with various active area sizes.

6.2 Device Fabrication

Figure 6-1 shows the key fabrication steps of poly-Si NW TFTs combined with the HfO2 gate dielectric, and its detailed process flow is described below. This device is called device A. The process steps before the gate dielectric deposition are the same as those described in section 5.3. After the standard RCA cleaning process, a metal-organic CVD (MOCVD) system was used to deposit a 10-nm-thick HfO2 gate dielectric (THfO2= 10 nm) at 500 °C. A 200-nm-thick un-doped amorphous-Si film was sequentially deposited by a LPCVD system and etched to define the gate pattern, and the omega-shaped gate structure was formed owing to the recessed and undercut etching of the buried SiO2 by several cleaning steps. Then, a double spacer consisting of a 20-nm-thick TEOS SiO2 and a 20-nm-thick Si3N4 was formed by a PECVD system and RIE. Phosphorous ions were implanted into the amorphous-Si gate electrode at 60 keV to a dose of 5x10¹⁵ cm^-2. This ion implantation process also amorphize the HfO2 gate dielectric at the S/D regions so that it can be removed easier.

After removing the HfO2 layer by a mixture of 95% isopropyl alcohol (IPA) and 5%

HF [10], the implanted dopants in the gate electrode were activated in N2 ambient at 600 °C for 12 hr. To reduce the S/D series resistance, the metal S/D was fabricated by a low-temperature process. After removing the native oxide on the phosphorus-doped poly-Si gate and S/D regions by DHF solutions, an 8-nm-thick Ni film was evaporated by electron-beam evaporation. Next, a two-step Ni-silicidation process was employed to form the n-type MSB S/D (as described in section 5.3) [11]. Some devices underwent a sintering process in forming gas (95 % N2 and 5 % hydrogen (H2)) at 400 °C for 30 min. Finally, PECVD oxide passivation, contact-hole patterning, Al metallization steps were performed to complete device fabrication. In

addition, the MOS capacitor with an area of 50x50 μm² was fabricated by using the same process flow to extract the EOT and the κ value of the HfO2 gate dielectric.

Figure 6-2(a) shows the device structure along the channel direction inspected by a TEM. The LG, TSi, and THfO2 are 40 nm, 10 nm, and 10 nm, respectively. The fully Ni-silicided S/D is successfully fabricated. Figure 6-2(b) shows an enlarged view of

在文檔中碳摻雜製程與高性能多晶矽奈米線薄膜電晶體之研究 (頁 141-175)