3.2 Junction Fabrication
4.3.2 Substitutional C Concentration and Sheet Resistance
The Rs values of various samples with different implantation energies, doses, temperatures, and annealing conditions are summarized in Table 4-2. Figure 4-8 shows the HRXRD rocking curves as a function of the implantation energy. The diffraction angle of the SiC peak is higher than that of the Si (004) peak because the lattice constant (a) of SiC is smaller than that of Si (aSi= 0.543 nm). The C ion implantation is performed at 5 °C with a dose of 5x1015 cm-2. After RTA annealing at 700 °C for 120 sec, both of the Rs and Csub values continuously increase with increasing the implantation energy from 3 keV to 7 keV, as shown in Fig. 4-8. The Csub value of 0.973 % is obtained as the implantation energy is at 7 keV, but its Rs
value increases to 270.5 Ω/□. The high Rs value is attributed to the incomplete recrystallization and the reductions of the P concentration and activation as mentioned before. As the implantation energy is increased from 3 keV to 7 keV, the increased overlap between the C and P doping profiles results in the higher Rs values. The Csub
value is highly associated with the amorphous layer thickness and the degree of amorphization. The thicker amorphous layer and total amorphization can cause the higher Csub value after SPE regrowth. Hence, the higher Csub value can be obtained with higher energy implantation of C. If the implantation energy is increased from 7 keV to 9 keV, the extracted Csub value is saturated at 1.047 %, as shown in Fig. 4-9.
Its implantation and annealing condition are labeled in the figure.
Next, we discuss the effect of the C implantation dose on the Rs and Csub values.
Figure 4-10 compares the HRXRD rocking curves of the RTA-annealed samples with two different implantation doses. A further increasing in the C implantation dose increases the thickness of the amorphous layer and the degree of amorphization.
Therefore, the high Csub value is expected to be obtained with increasing the C ion dose of 8x1015 cm-2, but the ratio of substitutional to total C concentration is decreased. An increase in substitutional C concentration is accompanied by an increase in interstitial C concentration. From Fig. 4-10, the SiC peak becomes broader with much lower intensity with increasing the C ion dose to 8x1015 cm-2. The decreased peak intensity suggests that the recrystallized SiC region has the poor crystal quality. The local change in the recrystallization rate induced by high C concentration can lead to a large number of crystal defects, such as dislocations, stacking faults, and twins [20]. The highest Rs value of 391 Ω/□ in Table 4-2 provides another evidence for the poor crystal quality. Hence, for obtaining the higher quality SiC layer, the C implantation dose should not exceed 5x1015 cm-2.
Figure 4-11 shows the implantation temperature dependence of the HRXRD rocking curves of the RTA-annealed samples. The XTEM image of the sample implanted with C (7 keV/5x1015 cm-2 at 5 °C) and P (17 keV/5x1015 cm-2) ions is shown in Fig. 4-12. Similar to Fig. 4-2, total amorphization is also reached at the
implantation temperature of 5 °C. Its amorphous-layer thickness is 49 nm, the same as that presented in Fig. 4-2. However, as compared to Fig. 4-2, the a/c interface shown in Fig. 4-12 reveals rough and low contrast. Therefore, after SPE annealing at 750 °C for 120 sec, the Csub value of the RTA-annealed sample implanted at -15 °C is slightly higher than that of the RTA-annealed sample implanted at 5 °C. The highest Csub
value of 1.046 % can be achieved by using a low-temperature C ion implantation technology at -15 °C.
Figure 4-13 presents the annealing temperature dependence of the HRXRD spectra of the RTA-annealed samples for fixed annealing time of 120 sec. The Csub
value continuously increases from 0.88 % to 1.027 % until the annealing temperature is increased to 750 °C. Moreover, the crystal quality of the recrystallized SiC region, as well as the Rs values listed in Table 4-2, can be improved by thermal annealing at higher temperatures. Nevertheless, once the annealing temperature exceeds 750 °C, the SiC peak is gradually close to the Si peak. Because most of the substitutional C atoms diffuse into the interstitial sites at higher temperatures, the Csub value decreases and even near zero at 850 °C. Therefore, the annealing temperature of 750 °C is suitable for SiC formation. Figure 4-14 presents the annealing time dependence of the HRXRD spectra of the RTA-annealed samples annealed at a fixed temperature of 750
°C. Further annealing results in the metastable state towards thermal equilibrium.
Hence, the Csub value will slightly decrease with little increase in the annealing time.
Too much thermal budget will cause the metastable state returns to thermal equilibrium, as shown in Fig. 4-15. When additional RTA annealing at the higher temperature of 1000 °C for 1 sec or furnace annealing at 750 °C for prolonged annealing time of 1 hr is performed, no obvious SiC peak can be observed.
The Rs values of the PLA-annealed samples with differing laser energy density and number of incident laser pulses are summarized in Table 4-3. Lower laser energy and a small number of incident laser pulses are insufficient to totally recrystallize the amorphous Si layer, so the Rs values higher than 1000 Ω/□ are measured. Increasing energy density and number of incident laser pulses can activate P dopants and reduce the Rs values. However, their HRXRD rocking curves indicate no C atoms are located at substitutional sites, as shown in Fig. 4-16. These HRXRD experimental results do not correspond to the previously reported experimental HRXRD data under similar experimental conditions [10, 21]. The possible reason is explained as follows. Since PLA was carried out in a low vacuum environment (~2x10-2 Torr= 2.666 Pa), there is still residual oxygen (O) in the chamber. It has been reported that O can interact with vacancy (V) to form the V-O defect in a 10-4 Pa working pressure during high-energy pulsed laser irradiation with multiple pulses [22]. The V-O defects can react with the substitutional C atoms to form CO complexes and volatile carbon oxides [22].
Therefore, to obtain the high Csub values, the PLA process must be performed in an oxygen-free environment to prevent C precipitation.
4.4 Conclusions
In this chapter, the SiC alloy is successfully fabricated by using the low-temperature C ion implantation followed by RTA annealing. The highest Csub
value of 1.046 % can be obtained via process optimization. For SiC S/D stressors, the C-implanted concentration in Si should be carefully optimized. It is useless to dope excess C atoms in Si because most of them will occupy interstitial sites instead of substitutional sites to form generation and scattering centers. Furthermore, the excess C-implanted concentration will result in incomplete recrystallization during the SPE
process and significant reductions of the P concentration in the recrystallized SiC region. Both of them cause an increase in the Rs values of the recrystallized SiC region. The critical amorphization dose decreases with decreasing implantation temperature, so the low-temperature C ion implantation only needs a lower implantation dose to achieve self amorphization without using PAI or heavier C cluster ions. A lower implantation dose can also help reduce the excess C-implanted concentration and Cint. Therefore, if the implantation temperature can be further reduced to lower temperature, the low-temperature C ion implantation has the potential to simultaneously achieve high Csub with high substitutional-to-total C ratio and low Rs. After SiC formation, it is important to note that the high thermal budget process should be avoided to eliminate C precipitation in Si.
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Table 4-1 Comparison of two fabricating methods of SiC S/D stressors.
Fabrication method Si recess etch and selective SiC epitaxy
C ion implantation and SPE
Throughput low high
Process complexity complex easy
Process cost high low
Highest reported Csub 2.3 % [8] 2.2 % [11]
Design stressor shape yes no
Doping method in-situ doping ion implantation
Table 4-2 Summary of the Rs (Ω/□) values of the RTA-annealed and furnace-annealed samples with different implantation energies, doses, temperatures, and annealing conditions.
SPE
Table 4-3 Summary of the Rs (Ω/□) values of the PLA-annealed samples with different laser energy densities and number of incident laser pulses. Before PLA annealing, these samples were implanted with C (9 keV/5x1015 cm-2 at -15 °C) and P (17 keV/5x1015 cm-2) ions.
Laser energy (mJ/cm2) 10 pulses 15 pulses 20 pulses
200 --- --- high Rs (non-measureable) 240 --- --- high Rs (non-measureable) 300 --- --- high Rs (non-measureable) 340 --- --- high Rs (non-measureable)
400 226900 234400 1125
440 41500 11240 738
500 647 649 383
540 445 360 328
0 50 100 150 200 1017
1018 1019 1020 1021 1022
as-implanted
P C
Concentration (atoms/cm3 )
Depth (nm)
Fig. 4-1 SIMS depth profile of the as-implanted sample implanted with C (7 keV/5x1015 cm-2 at -15 °C) and P (17 keV/5x1015 cm-2) ions.
Si substrate amorphous Si (49 nm) as-implanted
20 nm
Fig. 4-2 XTEM image of the as-implanted sample implanted with C (7 keV/5x1015 cm-2 at -15 °C) and P (17 keV/5x1015 cm-2) ions.
0 50 100 150 200 1017
1018 1019 1020 1021 1022
RTA @ 750 oC/120 sec
P C
Concentration (atoms/cm3 )
Depth (nm)
Fig. 4-3 SIMS profile of the RTA-annealed (750 °C/120 sec) sample implanted with C (7 keV/5x1015 cm-2 at -15 °C) and P (17 keV/5x1015 cm-2) ions.
amorphous Si (22 nm)
Si substrate RTA @ 750 oC/120 sec
20 nm
SPE regrowth (27 nm)
EOR defect
Fig. 4-4 XTEM image of the RTA-annealed (750 °C/120 sec) sample implanted with C (7 keV/5x1015 cm-2 at -15 °C) and P (17 keV/5x1015 cm-2) ions.
50 nm
amorphous Si (26 nm) Si substrate
RTA @ 750 oC/120 sec
oxide capping layer
Fig. 4-5 XTEM image of the RTA-annealed (750 °C/120 sec) sample implanted only with C (7 keV/5x1015 cm-2 at -15 °C) ions.
amorphous Si Si substrate
furnace annealing @ 750 oC/1 hr
50 nm
oxide capping layer
Fig. 4-6 XTEM image of the furnace-annealed (750 °C/1 hr) sample implanted with C (7 keV/5x1015 cm-2 at -15 °C) and P (17 keV/5x1015 cm-2) ions.
0 50 100 150 200
Fig. 4-7 Comparison of the SIMS profiles of the as-implanted and RTA-annealed (750 °C/120 sec) samples implanted with C (7 keV/5x1015 cm-2 at -15 °C)
Fig. 4-8 Energy dependence of the HRXRD rocking curves of the RTA-annealed (700 °C/120 sec) samples implanted with C and P (17 keV/5x1015 cm-2) ions.
34.0 34.5 35.0 35.5
Fig. 4-9 Energy dependence of the HRXRD rocking curves of the RTA-annealed (750 °C/120 sec) samples implanted with C and P (17 keV/5x1015 cm-2)
Fig. 4-10 Dose dependence of the HRXRD rocking curves of the RTA-annealed (750
°C/120 sec) samples implanted with C and P (17 keV/5x1015 cm-2) ions.
34.0 34.5 35.0 35.5 101
103 105 107 109
7 keV/5x1015 cm-2
@ 5 oC
Csub= 1.046 % 7 keV/5x1015 cm-2
@ -15 oC
Intensity (a.u.)
Bragg Angle (deg) RTA @ 750 oC/120 sec
Csub= 1.027 %
Fig. 4-11 Implantation temperature dependence of the HRXRD rocking curves of the RTA-annealed (750 °C/120 sec) samples implanted with C and P (17 keV/5x1015 cm-2) ions.
Si substrate amorphous Si (49 nm)
20 nm
as-implanted
Fig. 4-12 XTEM image of the as-implanted sample implanted with C (7 keV/5x1015 cm-2 at 5 °C) and P (17 keV/5x1015 cm-2) ions.
34.0 34.5 35.0 35.5
Fig. 4-13 HRXRD spectra of the RTA-annealed samples implanted with C and P (17 keV/5x1015 cm-2) ions after RTA annealing at various temperatures for 120 sec.
Fig. 4-14 HRXRD spectra of the RTA-annealed samples implanted with C and P (17 keV/5x1015 cm-2) ions after RTA annealing at 750 °C for different annealing time.
34.0 34.5 35.0 35.5
Fig. 4-15 HRXRD spectra of the RTA-annealed and furnace-annealed samples implanted with C and P (17 keV/5x1015 cm-2) ions.
Fig. 4-16 HRXRD spectra of the PLA-annealed samples implanted with C and P (17 keV/5x1015 cm-2) ions.
Chapter 5
Fabrication and Electrical Characteristics of Gate-All-Around Poly-Si Nanowire Thin-Film
Transistors
5.1 Introduction
Low temperature poly-Si TFTs have been studied for several years and successfully used as pixel and driving IC in AM-LCDs and AM-OLED displays [1-2].
However, in order to apply poly-Si TFTs to SOP display, their device characteristics are needed to be further improved. Furthermore, 3D IC and 3D Flash memory have several advantages for relaxing device scaling down issues [3-4], which could be realized by using the poly-Si TFT technology. Therefore, for these applications, high-performance poly-Si TFTs are required.
To achieve high performance, poly-Si TFTs with various fabrication processes and device structures have been extensively investigated to reduce grain-boundary defects of the poly-Si film and eliminate SCEs. Large-grain poly-Si TFTs are extensively researched by different recrystallization technologies including ELA and MILC instead of conventional SPC [5-6]. Large-grain poly-Si TFTs with low grain-boundary defect density can enhance the carrier mobility and suppress the leakage current. Furthermore, it is well known that the NH3 plasma treatment process is able to reduce grain-boundary defects and effectively improve the device
characteristics of poly-Si TFTs [7]. Various poly-Si NW TFTs with different multi-gate structures were proposed by many researchers [8-11]. The main advantage of these device structures is suppressing SCEs by increasing the control ability of the gate electrode. The device parameters of several high-performance poly-Si TFTs published in recent years are summarized in Table 5-1 [5-6, 10-13]. Although great progress has been achieved, the device performance of poly-Si TFTs is still poorer than that of the devices fabricated on single crystalline Si. This chapter will review these high-performance poly-Si TFTs and discuss advantages and disadvantages of them. Based on these discussions, the aim of this study is to achieve high-performance poly-Si TFTs by structural engineering.
Furthermore, the LG of most of the published poly-Si TFTs is usually larger than or equal to 1 μm, so the short-channel behavior of poly-Si TFTs is not clear. As poly-Si TFTs are applied in the 3D IC or 3D Flash memory technology in the future, LG scaling of poly-Si TFTs should be achieved simultaneously for high layout efficiency as logic or memory devices. Therefore, the device characteristics of poly-Si TFTs with the ultra-short LG must be investigated. Although the poly-Si NW TFT with LG down to 20 nm and the omega-shaped gate electrode has been reported, the switching characteristics are poor [11]. In this chapter, we successfully fabricate the smallest GAA poly-Si NW TFT with LG of 30 nm. Good electrical characteristics are obtained by the poly-Si NW, GAA, and MSB S/D structures [14]. Short-channel and narrow-width characteristics of our fabricated devices are investigated. The current transport mechanism is clarified by high-temperature measurements. Finally, the effect of the NH3 plasma treatment on the device characteristics is also discussed.