In this section, we first discuss how to achieve high-performance poly-Si TFTs by structural engineering, which can be divided into three parts: (a) recrystallization techniques, (b) short-channel characteristics, and (c) driving capability.
(a) Recrystallization techniques
Reducing the number of the grain boundary in the poly-Si channel region is the basic strategy to achieve high performance. Therefore, several recrystallization techniques including the SPC, ELA, and MILC technologies were studied to enlarge the grain size of the poly-Si channel film [5-6]. The comparison of these recrystallization techniques are listed in Table 5-2. For large-area poly-Si TFTs, the device characteristics of the ELA and MILC poly-Si TFTs are superior to those of the SPC poly-Si TFTs because of their larger grain size and fewer grain boundaries throughout their channel regions [5-6]. However, the ELA process has two drawbacks, such as its high initial cost and process complexity [15]. The MILC grains contain small amounts of metal contamination and high intragrain defect density, which can deteriorate the device characteristics [16]. In addition to the enlargement of the grain size, device scaling also helps reduce the number of the grain boundary in the poly-Si channel region. If the active device area is compatible with the average grain size, it is possible to have few grain boundaries in the poly-Si channel region. Hence, despite using SPC technology, good device characteristics may still be obtained by device scaling. SPC crystallization technology is a promising technique due to its simplicity, low cost, excellent uniformity, and large-area capacity [17]. In this work, we use the SPC crystallization technology instead of other grain-enhancement techniques to investigate the effect of device scaling on the device characteristics of poly-Si TFTs.
(b) Short-channel characteristics
Most high-performance poly-Si TFTs have LG lager than 1 μm to avoid SCEs, so excellent subthreshold swing (S.S.) and drain-induced-barrier-lowering (DIBL) values can be obtained [5-6, 12]. To reduce LG while keeping good SCEs, the natural length (λ) concept of conventional Si MOSFETs is introduced into poly-Si TFTs [18]:
ox
where Cox is the gate capacitance per unit area. εox and εSi are the relative permittivity of the gate dielectric and the Si channel region, respectively, and Tox and TSi are the physical thickness of the gate dielectric and the Si or poly-Si channel region, respectively. The value, N, means the number of the gate electrodes. The physical meaning of λ is the extension of the electric field lines from the drain electrode in the Si channel region. In addition to an increase of the number of the gate electrodes, reducing the poly-Si film thickness and EOT also results in shorter λ. If λ is 5 to 10 times smaller than LG, SCEs can be well controlled. The device characteristics of poly-Si NW TFTs with the multi-gate structures were investigated [10-11]. As LG
scales from 400 nm to 100 nm, SCEs can be effectively eliminated. Moreover, the high-κ gate dielectric extensively used in conventional Si MOSFETs was also integrated into poly-Si TFTs to reduce the EOT and eliminate SCEs [12-13].
Reference [13] using the HfO2 gate dielectric also reveals good SCEs as LG is scaled down to 100 nm. The ultra-short-channel characteristics (LG < 100 nm) of poly-Si TFTs have seldom been reported in the literature but become very important for device scaling in the future. In this work, the ultra-thin and narrow poly-Si body, the multi-gate structure, and the HfO2 gate dielectric are completely integrated together
on our ultra-short-channel poly-Si NW TFTs, thus good short-channel characteristics can be demonstrated by structural engineering.
(c) Driving capability
Some driving current (ION) values listed in Table 5-1 are still lower than 100 μA/μm due to their relatively long LG (LG ≧ 1 μm), unless the drain electrode is intentionally biased at higher voltages to raise their ION values. Therefore, for low-voltage operation, the driving capability of poly-Si TFTs is needed to be improved. The linear-region drain-to-source current (IDS) equation of poly-Si TFTs deduced by J. Levinson et al. is shown below [19]:
(
GS TH)
DS where μEFF is the field-effect mobility, W is the physical channel width, VB is the effective grain-boundary barrier height, κΒ is Boltzmann’s constant, T is absolute temperature, and VGS, VTH, and VDS are the gate, threshold, and drain voltages, respectively. Based on the Levinson’s current model, the high driving capability can be obtained by increasing μEFF and Cox or decreasing LG, VB, and VTH. Various grain-enhancement technologies mentioned before can effectively raise μEFF and lower VB and VTH. Similarly, EOT scaling not only suppresses SCEs but also enhances the driving capability. The LG scaling, i.e. device scaling, is another direct method to enhance the driving capability. However, LG scaling may degrade the driving capability if the parasitic S/D resistance effect occurs. Once the ultra-thin poly-Si film thickness and/or the poly-Si NW channel are adopted to suppress SCEs, the parasitic series resistance effect is more apparent. The standard self-aligned Ni-silicide process used in the current Si MOSFETs can be applied in poly-Si TFTs to relax the series resistance issue [20]. For our ultra-short-channel poly-Si NW TFTs,the fully-Ni-silicided S/D is successfully formed during the MSB S/D process.
Therefore, the high driving capability can also be achieved by structural engineering.